diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt | 1684 |
1 files changed, 841 insertions, 843 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 4c2a41024..7d82f190a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.305853 # Number of seconds simulated -sim_ticks 5305853045500 # Number of ticks simulated -final_tick 5305853045500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.305855 # Number of seconds simulated +sim_ticks 5305855051000 # Number of ticks simulated +final_tick 5305855051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178751 # Simulator instruction rate (inst/s) -host_op_rate 342595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8842177355 # Simulator tick rate (ticks/s) -host_mem_usage 856496 # Number of bytes of host memory used -host_seconds 600.06 # Real time elapsed on the host -sim_insts 107261902 # Number of instructions simulated -sim_ops 205578300 # Number of ops (including micro ops) simulated +host_inst_rate 186796 # Simulator instruction rate (inst/s) +host_op_rate 357991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9246678170 # Simulator tick rate (ticks/s) +host_mem_usage 1105624 # Number of bytes of host memory used +host_seconds 573.81 # Real time elapsed on the host +sim_insts 107186053 # Number of instructions simulated +sim_ops 205419480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11415232 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11415232 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9161984 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9161984 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 178363 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 178363 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 143156 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 143156 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2151441 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2151441 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1726769 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1726769 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3878211 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3878211 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 178363 # Number of read requests accepted -system.mem_ctrls.writeReqs 143156 # Number of write requests accepted -system.mem_ctrls.readBursts 178363 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 143156 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11360576 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 54656 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9153536 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11415232 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9161984 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 854 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 108 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11371136 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11371136 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9131456 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9131456 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 177674 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 177674 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 142679 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 142679 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2143130 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2143130 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1721015 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1721015 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3864145 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3864145 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 177674 # Number of read requests accepted +system.mem_ctrls.writeReqs 142679 # Number of write requests accepted +system.mem_ctrls.readBursts 177674 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 142679 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11313280 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 57856 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9121152 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11371136 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9131456 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 904 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 135 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 10856 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 10881 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 10729 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11226 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11595 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 12060 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 11357 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10544 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 10640 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 10408 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 10338 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 14247 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 10851 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10291 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 10803 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10683 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 8741 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 8453 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 8515 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 9195 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9530 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9557 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 9142 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 8665 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 8844 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 8855 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 8455 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 9314 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 8873 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 8616 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 9161 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 9108 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 10805 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10794 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10981 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11389 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11550 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 12175 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 10978 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10407 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10706 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 10369 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10514 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 13718 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 10819 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10294 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10714 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10557 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8779 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8773 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8745 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9209 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9395 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9648 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8754 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8594 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 8776 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 8713 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 8651 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9041 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 8739 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8605 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9111 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 8985 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5305852911000 # Total gap between requests +system.mem_ctrls.totGap 5305854916500 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 178363 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 177674 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 143156 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 177440 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 69 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 142679 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 176703 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 67 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2057 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2808 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8578 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9141 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8600 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9229 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9219 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8361 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9057 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9077 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8449 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8526 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8348 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8471 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8060 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8092 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8178 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 7986 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 125 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 114 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 101 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 94 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 84 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 73 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 33 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 27 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 19 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 9 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2059 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2790 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8563 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9122 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8572 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9212 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9228 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9034 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9060 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8413 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8500 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8357 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8453 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8029 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8097 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8147 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 7952 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 85 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 89 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 75 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 64 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 28 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 18 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -184,213 +184,211 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 60721 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 337.841076 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 199.411090 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 344.057801 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20489 33.74% 33.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 14673 24.16% 57.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6364 10.48% 68.39% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3396 5.59% 73.98% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2745 4.52% 78.50% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1826 3.01% 81.51% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1362 2.24% 83.75% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1430 2.36% 86.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8436 13.89% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 60721 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 7928 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.388118 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 317.537098 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 7922 99.92% 99.92% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::1024-2047 2 0.03% 99.95% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::2048-3071 2 0.03% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 60336 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 338.676213 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 200.551275 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 343.723517 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20068 33.26% 33.26% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 14736 24.42% 57.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6373 10.56% 68.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3491 5.79% 74.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2657 4.40% 78.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1861 3.08% 81.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1364 2.26% 83.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1338 2.22% 86.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8448 14.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 60336 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 7897 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.382170 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.489285 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 7891 99.92% 99.92% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 7928 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 7928 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 18.040363 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.696882 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 3.983964 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5814 73.34% 73.34% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 14 0.18% 73.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 181 2.28% 75.79% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 14 0.18% 75.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 36 0.45% 76.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 489 6.17% 82.59% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 149 1.88% 84.47% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 53 0.67% 85.14% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 653 8.24% 93.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 113 1.43% 94.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 3 0.04% 94.84% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.01% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 312 3.94% 98.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 4 0.05% 98.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 10 0.13% 99.12% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 5 0.06% 99.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 9 0.11% 99.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 9 0.11% 99.41% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 2 0.03% 99.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.47% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 4 0.05% 99.52% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 5 0.06% 99.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.65% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 6 0.08% 99.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 2 0.03% 99.75% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 1 0.01% 99.76% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 2 0.03% 99.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::46 1 0.01% 99.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.92% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 1 0.01% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::49 2 0.03% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 3 0.04% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 7928 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1963261998 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5291555748 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 887545000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11060.07 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 7897 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 7897 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 18.047106 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.696875 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 4.065797 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 5800 73.45% 73.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 169 2.14% 75.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 20 0.25% 75.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 37 0.47% 76.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 500 6.33% 82.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 145 1.84% 84.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 43 0.54% 85.13% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 653 8.27% 93.40% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 111 1.41% 94.81% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 12 0.15% 94.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 19 0.24% 95.20% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 304 3.85% 99.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 7 0.09% 99.14% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 3 0.04% 99.18% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 6 0.08% 99.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 2 0.03% 99.35% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.40% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 3 0.04% 99.46% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 7 0.09% 99.54% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 3 0.04% 99.62% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 2 0.03% 99.72% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 1 0.01% 99.81% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 9 0.11% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::52 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 7897 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1934453242 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5248890742 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 883850000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 10943.33 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29810.07 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 2.14 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 29693.33 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 2.13 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2.14 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.03 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.94 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 141459 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 118352 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.69 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 82.74 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 16502455.25 # Average gap between requests -system.mem_ctrls.pageHitRate 81.05 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 231139440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 126117750 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 696134400 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 465251040 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 149731396200 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3052164794250 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3549966942360 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 669.066980 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5077378950000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 177173880000 # Time in different power states +system.mem_ctrls.avgWrQLen 24.42 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 140774 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 118177 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.64 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.91 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 16562526.08 # Average gap between requests +system.mem_ctrls.pageHitRate 81.10 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 229839120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 125408250 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 694816200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 465892560 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 149179147425 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3052653894750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3549901616145 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 669.053686 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5078195767000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 51294057500 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 50484766750 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 227911320 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 124356375 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 688428000 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 461544480 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 149042883510 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3052768752750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3549865985715 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 669.047952 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5078391595500 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 177173880000 # Time in different power states +system.mem_ctrls_1.actEnergy 226301040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 123477750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 683982000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 457624080 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 148537848690 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3053216437500 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3549798288900 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 669.034212 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5079136661250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 50287445500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 49544125250 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10611706091 # number of cpu cycles simulated +system.cpu0.numCycles 10611710102 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 59111887 # Number of instructions committed -system.cpu0.committedOps 113456709 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 106426265 # Number of integer alu accesses +system.cpu0.committedInsts 59039296 # Number of instructions committed +system.cpu0.committedOps 113305650 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 106292214 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu0.num_func_calls 1016173 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 10055603 # number of instructions that are conditional controls -system.cpu0.num_int_insts 106426265 # number of integer instructions +system.cpu0.num_func_calls 1017385 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 10037497 # number of instructions that are conditional controls +system.cpu0.num_int_insts 106292214 # number of integer instructions system.cpu0.num_fp_insts 48 # number of float instructions -system.cpu0.num_int_register_reads 200823032 # number of times the integer registers were read -system.cpu0.num_int_register_writes 90335124 # number of times the integer registers were written +system.cpu0.num_int_register_reads 200616677 # number of times the integer registers were read +system.cpu0.num_int_register_writes 90211380 # number of times the integer registers were written system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 61044422 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44109295 # number of times the CC registers were written -system.cpu0.num_mem_refs 12452626 # number of memory refs -system.cpu0.num_load_insts 7522002 # Number of load instructions -system.cpu0.num_store_insts 4930624 # Number of store instructions -system.cpu0.num_idle_cycles 10088968020.334099 # Number of idle cycles -system.cpu0.num_busy_cycles 522738070.665901 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049261 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950739 # Percentage of idle cycles -system.cpu0.Branches 11433567 # Number of branches fetched -system.cpu0.op_class::No_OpClass 130284 0.11% 0.11% # Class of executed instruction -system.cpu0.op_class::IntAlu 100735872 88.79% 88.90% # Class of executed instruction -system.cpu0.op_class::IntMult 86129 0.08% 88.98% # Class of executed instruction -system.cpu0.op_class::IntDiv 56904 0.05% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatCvt 16 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::MemRead 7517799 6.63% 95.65% # Class of executed instruction -system.cpu0.op_class::MemWrite 4930624 4.35% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 60966470 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44030878 # number of times the CC registers were written +system.cpu0.num_mem_refs 12456031 # number of memory refs +system.cpu0.num_load_insts 7518228 # Number of load instructions +system.cpu0.num_store_insts 4937803 # Number of store instructions +system.cpu0.num_idle_cycles 10088651138.334099 # Number of idle cycles +system.cpu0.num_busy_cycles 523058963.665901 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049291 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950709 # Percentage of idle cycles +system.cpu0.Branches 11416966 # Number of branches fetched +system.cpu0.op_class::No_OpClass 131109 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 100580264 88.77% 88.88% # Class of executed instruction +system.cpu0.op_class::IntMult 86269 0.08% 88.96% # Class of executed instruction +system.cpu0.op_class::IntDiv 57079 0.05% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatCvt 16 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::MemRead 7514027 6.63% 95.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 4937803 4.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 113457628 # Class of executed instruction +system.cpu0.op_class::total 113306567 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10608768454 # number of cpu cycles simulated +system.cpu1.numCycles 10608777066 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48150015 # Number of instructions committed -system.cpu1.committedOps 92121591 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88447957 # Number of integer alu accesses +system.cpu1.committedInsts 48146757 # Number of instructions committed +system.cpu1.committedOps 92113830 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88441893 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu1.num_func_calls 1752470 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8220366 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88447957 # number of integer instructions +system.cpu1.num_func_calls 1752446 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8219760 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88441893 # number of integer instructions system.cpu1.num_fp_insts 48 # number of float instructions -system.cpu1.num_int_register_reads 171418672 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73201138 # number of times the integer registers were written +system.cpu1.num_int_register_reads 171408328 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73196137 # number of times the integer registers were written system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 50927853 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 32747912 # number of times the CC registers were written -system.cpu1.num_mem_refs 14125902 # number of memory refs -system.cpu1.num_load_insts 9133895 # Number of load instructions -system.cpu1.num_store_insts 4992007 # Number of store instructions -system.cpu1.num_idle_cycles 10273983246.713898 # Number of idle cycles -system.cpu1.num_busy_cycles 334785207.286102 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031557 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968443 # Percentage of idle cycles -system.cpu1.Branches 10582274 # Number of branches fetched -system.cpu1.op_class::No_OpClass 169782 0.18% 0.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 77660290 84.30% 84.49% # Class of executed instruction -system.cpu1.op_class::IntMult 98483 0.11% 84.59% # Class of executed instruction -system.cpu1.op_class::IntDiv 71910 0.08% 84.67% # Class of executed instruction +system.cpu1.num_cc_register_reads 50924734 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 32745964 # number of times the CC registers were written +system.cpu1.num_mem_refs 14124901 # number of memory refs +system.cpu1.num_load_insts 9133293 # Number of load instructions +system.cpu1.num_store_insts 4991608 # Number of store instructions +system.cpu1.num_idle_cycles 10274072284.207695 # Number of idle cycles +system.cpu1.num_busy_cycles 334704781.792306 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031550 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968450 # Percentage of idle cycles +system.cpu1.Branches 10581617 # Number of branches fetched +system.cpu1.op_class::No_OpClass 169787 0.18% 0.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 77653530 84.30% 84.49% # Class of executed instruction +system.cpu1.op_class::IntMult 98479 0.11% 84.59% # Class of executed instruction +system.cpu1.op_class::IntDiv 71918 0.08% 84.67% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::FloatCvt 16 0.00% 84.67% # Class of executed instruction @@ -417,17 +415,17 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.67% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.67% # Class of executed instruction -system.cpu1.op_class::MemRead 9129754 9.91% 94.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 4992007 5.42% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 9129153 9.91% 94.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 4991608 5.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92122242 # Class of executed instruction +system.cpu1.op_class::total 92114491 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 857753 # Transaction distribution -system.iobus.trans_dist::ReadResp 857753 # Transaction distribution -system.iobus.trans_dist::WriteReq 36065 # Transaction distribution -system.iobus.trans_dist::WriteResp 36065 # Transaction distribution +system.iobus.trans_dist::ReadReq 842290 # Transaction distribution +system.iobus.trans_dist::ReadResp 842290 # Transaction distribution +system.iobus.trans_dist::WriteReq 35657 # Transaction distribution +system.iobus.trans_dist::WriteResp 35657 # Transaction distribution system.iobus.trans_dist::MessageReq 1791 # Transaction distribution system.iobus.trans_dist::MessageResp 1791 # Transaction distribution system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) @@ -440,15 +438,15 @@ system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.p system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 66 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 964 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14814 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 742772 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 729402 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 158 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1702492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1671974 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5284 # Packet count per connected master and slave (bytes) @@ -456,9 +454,9 @@ system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.p system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 396 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 28 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30330 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 384 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 30418 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12448 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) @@ -466,8 +464,8 @@ system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.p system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 85378 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1791218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 84154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1759476 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) @@ -478,15 +476,15 @@ system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 33 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1928 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7407 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1485538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1458798 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 316 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1970762 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1935448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3394 # Cumulative packet size per connected master and slave (bytes) @@ -494,9 +492,9 @@ system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 198 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 14 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15471 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15165 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15515 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15209 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) @@ -504,53 +502,53 @@ system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 51075 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2028533 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 50000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 50463 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 1992607 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10224000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9032500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 154500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 940000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 97500 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 56000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 52500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 20660000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 20247500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 700937500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 458718000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1276000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1157500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 31144500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 30508000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 23664000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 20468500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 468374820 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 369412820 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 7594080 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 7528580 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 1329500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 1593000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2404400 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2422900 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2023552000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1846190500 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 60655000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 57610000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). @@ -567,48 +565,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10895286 # delay histogram for all message -system.ruby.delayHist::mean 0.442462 # delay histogram for all message -system.ruby.delayHist::stdev 1.830078 # delay histogram for all message -system.ruby.delayHist | 10293202 94.47% 94.47% | 1309 0.01% 94.49% | 600320 5.51% 100.00% | 166 0.00% 100.00% | 230 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10895286 # delay histogram for all message +system.ruby.delayHist::samples 10891010 # delay histogram for all message +system.ruby.delayHist::mean 0.442869 # delay histogram for all message +system.ruby.delayHist::stdev 1.830823 # delay histogram for all message +system.ruby.delayHist | 10288616 94.47% 94.47% | 1282 0.01% 94.48% | 600649 5.52% 100.00% | 161 0.00% 100.00% | 257 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10891010 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152835089 +system.ruby.outstanding_req_hist::samples 152756591 system.ruby.outstanding_req_hist::mean 1.000166 system.ruby.outstanding_req_hist::gmean 1.000115 -system.ruby.outstanding_req_hist::stdev 0.012900 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152809653 99.98% 99.98% | 25436 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152835089 -system.ruby.latency_hist::bucket_size 256 -system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 152835088 -system.ruby.latency_hist::mean 3.434218 -system.ruby.latency_hist::gmean 3.107238 -system.ruby.latency_hist::stdev 5.763390 -system.ruby.latency_hist | 152826003 99.99% 99.99% | 6324 0.00% 100.00% | 2683 0.00% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 152835088 +system.ruby.outstanding_req_hist::stdev 0.012901 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152731162 99.98% 99.98% | 25429 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152756591 +system.ruby.latency_hist::bucket_size 128 +system.ruby.latency_hist::max_bucket 1279 +system.ruby.latency_hist::samples 152756590 +system.ruby.latency_hist::mean 3.433707 +system.ruby.latency_hist::gmean 3.107293 +system.ruby.latency_hist::stdev 5.733578 +system.ruby.latency_hist | 152719525 99.98% 99.98% | 28048 0.02% 99.99% | 2695 0.00% 100.00% | 3637 0.00% 100.00% | 2109 0.00% 100.00% | 523 0.00% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.latency_hist::total 152756590 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 150173511 +system.ruby.hit_latency_hist::samples 150094333 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150173511 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 150173511 -system.ruby.miss_latency_hist::bucket_size 256 -system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 2661577 -system.ruby.miss_latency_hist::mean 27.933971 -system.ruby.miss_latency_hist::gmean 22.542647 -system.ruby.miss_latency_hist::stdev 36.007178 -system.ruby.miss_latency_hist | 2652492 99.66% 99.66% | 6324 0.24% 99.90% | 2683 0.10% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 2661577 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 11100819 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 532265 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11633084 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 68582952 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 323144 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 68906096 # Number of cache demand accesses +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150094333 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 150094333 +system.ruby.miss_latency_hist::bucket_size 128 +system.ruby.miss_latency_hist::max_bucket 1279 +system.ruby.miss_latency_hist::samples 2662257 +system.ruby.miss_latency_hist::mean 27.885506 +system.ruby.miss_latency_hist::gmean 22.530762 +system.ruby.miss_latency_hist::stdev 35.745831 +system.ruby.miss_latency_hist | 2625192 98.61% 98.61% | 28048 1.05% 99.66% | 2695 0.10% 99.76% | 3637 0.14% 99.90% | 2109 0.08% 99.98% | 523 0.02% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.miss_latency_hist::total 2662257 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 11119260 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 532503 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11651763 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 68488995 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 323914 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 68812909 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -618,13 +616,13 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 15 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12795046 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313851 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108897 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 57694694 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 492317 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58187011 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 16 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12794938 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313574 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108512 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 57691140 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 492266 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58183406 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -635,71 +633,71 @@ system.ruby.l1_cntrl1.prefetcher.partial_hits 0 system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl1.fully_busy_cycles 7 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2434372 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227205 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2661577 # Number of cache demand accesses -system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2435460 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 226797 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2662257 # Number of cache demand accesses +system.ruby.l2_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.029987 -system.ruby.network.routers0.msg_count.Control::0 855409 -system.ruby.network.routers0.msg_count.Request_Control::2 42371 -system.ruby.network.routers0.msg_count.Response_Data::1 883866 -system.ruby.network.routers0.msg_count.Response_Control::1 509923 -system.ruby.network.routers0.msg_count.Response_Control::2 507294 -system.ruby.network.routers0.msg_count.Writeback_Data::0 298509 -system.ruby.network.routers0.msg_count.Writeback_Data::1 176 -system.ruby.network.routers0.msg_count.Writeback_Control::0 170526 -system.ruby.network.routers0.msg_bytes.Control::0 6843272 -system.ruby.network.routers0.msg_bytes.Request_Control::2 338968 -system.ruby.network.routers0.msg_bytes.Response_Data::1 63638352 -system.ruby.network.routers0.msg_bytes.Response_Control::1 4079384 -system.ruby.network.routers0.msg_bytes.Response_Control::2 4058352 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21492648 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12672 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1364208 -system.ruby.network.routers1.percent_links_utilized 0.057152 -system.ruby.network.routers1.msg_count.Control::0 1806168 -system.ruby.network.routers1.msg_count.Request_Control::2 40332 -system.ruby.network.routers1.msg_count.Response_Data::1 1830141 -system.ruby.network.routers1.msg_count.Response_Control::1 1256659 -system.ruby.network.routers1.msg_count.Response_Control::2 1255808 -system.ruby.network.routers1.msg_count.Writeback_Data::0 276119 -system.ruby.network.routers1.msg_count.Writeback_Data::1 194 -system.ruby.network.routers1.msg_count.Writeback_Control::0 942229 -system.ruby.network.routers1.msg_bytes.Control::0 14449344 -system.ruby.network.routers1.msg_bytes.Request_Control::2 322656 -system.ruby.network.routers1.msg_bytes.Response_Data::1 131770152 -system.ruby.network.routers1.msg_bytes.Response_Control::1 10053272 -system.ruby.network.routers1.msg_bytes.Response_Control::2 10046464 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880568 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 13968 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7537832 -system.ruby.network.routers2.percent_links_utilized 0.091505 -system.ruby.network.routers2.msg_count.Control::0 2839493 -system.ruby.network.routers2.msg_count.Request_Control::2 81198 -system.ruby.network.routers2.msg_count.Response_Data::1 2891200 -system.ruby.network.routers2.msg_count.Response_Control::1 1848800 -system.ruby.network.routers2.msg_count.Response_Control::2 1763102 -system.ruby.network.routers2.msg_count.Writeback_Data::0 574628 -system.ruby.network.routers2.msg_count.Writeback_Data::1 370 -system.ruby.network.routers2.msg_count.Writeback_Control::0 1112755 -system.ruby.network.routers2.msg_bytes.Control::0 22715944 -system.ruby.network.routers2.msg_bytes.Request_Control::2 649584 -system.ruby.network.routers2.msg_bytes.Response_Data::1 208166400 -system.ruby.network.routers2.msg_bytes.Response_Control::1 14790400 -system.ruby.network.routers2.msg_bytes.Response_Control::2 14104816 -system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41373216 -system.ruby.network.routers2.msg_bytes.Writeback_Data::1 26640 -system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8902040 -system.ruby.network.routers3.percent_links_utilized 0.006812 -system.ruby.network.routers3.msg_count.Control::0 177916 -system.ruby.network.routers3.msg_count.Response_Data::1 276580 -system.ruby.network.routers3.msg_count.Response_Control::1 130228 +system.ruby.network.routers0.percent_links_utilized 0.030013 +system.ruby.network.routers0.msg_count.Control::0 856417 +system.ruby.network.routers0.msg_count.Request_Control::2 42660 +system.ruby.network.routers0.msg_count.Response_Data::1 884950 +system.ruby.network.routers0.msg_count.Response_Control::1 510141 +system.ruby.network.routers0.msg_count.Response_Control::2 507455 +system.ruby.network.routers0.msg_count.Writeback_Data::0 298492 +system.ruby.network.routers0.msg_count.Writeback_Data::1 178 +system.ruby.network.routers0.msg_count.Writeback_Control::0 170402 +system.ruby.network.routers0.msg_bytes.Control::0 6851336 +system.ruby.network.routers0.msg_bytes.Request_Control::2 341280 +system.ruby.network.routers0.msg_bytes.Response_Data::1 63716400 +system.ruby.network.routers0.msg_bytes.Response_Control::1 4081128 +system.ruby.network.routers0.msg_bytes.Response_Control::2 4059640 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21491424 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12816 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1363216 +system.ruby.network.routers1.percent_links_utilized 0.057139 +system.ruby.network.routers1.msg_count.Control::0 1805840 +system.ruby.network.routers1.msg_count.Request_Control::2 40537 +system.ruby.network.routers1.msg_count.Response_Data::1 1830038 +system.ruby.network.routers1.msg_count.Response_Control::1 1255303 +system.ruby.network.routers1.msg_count.Response_Control::2 1254313 +system.ruby.network.routers1.msg_count.Writeback_Data::0 276120 +system.ruby.network.routers1.msg_count.Writeback_Data::1 190 +system.ruby.network.routers1.msg_count.Writeback_Control::0 940436 +system.ruby.network.routers1.msg_bytes.Control::0 14446720 +system.ruby.network.routers1.msg_bytes.Request_Control::2 324296 +system.ruby.network.routers1.msg_bytes.Response_Data::1 131762736 +system.ruby.network.routers1.msg_bytes.Response_Control::1 10042424 +system.ruby.network.routers1.msg_bytes.Response_Control::2 10034504 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880640 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 13680 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7523488 +system.ruby.network.routers2.percent_links_utilized 0.091475 +system.ruby.network.routers2.msg_count.Control::0 2839469 +system.ruby.network.routers2.msg_count.Request_Control::2 81710 +system.ruby.network.routers2.msg_count.Response_Data::1 2890401 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+system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 368 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1110838 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21298056 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14602536 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 985240 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14094144 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 26496 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8886704 +system.ruby.network.routers6.throttle3.link_utilization 0.005259 +system.ruby.network.routers6.throttle3.msg_count.Control::0 177212 +system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97371 +system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15060 system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47545 -system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1423328 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7045560 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 122304 +system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1417696 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7010712 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 120480 system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers6.throttle4.link_utilization 0.000255 system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 809 @@ -881,176 +879,176 @@ system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 3738 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6112062 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.754100 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.339998 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5536581 90.58% 90.58% | 390 0.01% 90.59% | 574653 9.40% 99.99% | 162 0.00% 100.00% | 217 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6112062 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6109475 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.754420 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.340404 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5533989 90.58% 90.58% | 406 0.01% 90.59% | 574630 9.41% 99.99% | 158 0.00% 100.00% | 247 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6109475 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4700521 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.045023 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.596216 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4673467 99.42% 99.42% | 451 0.01% 99.43% | 352 0.01% 99.44% | 567 0.01% 99.45% | 25509 0.54% 100.00% | 158 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 10 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4700521 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4698338 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.045583 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.599791 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4670953 99.42% 99.42% | 477 0.01% 99.43% | 336 0.01% 99.43% | 540 0.01% 99.45% | 25880 0.55% 100.00% | 139 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4698338 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 82703 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000121 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.015550 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 82698 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 82703 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 83197 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000192 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.019611 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 83189 99.99% 99.99% | 0 0.00% 99.99% | 8 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 83197 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 15017729 -system.ruby.LD.latency_hist::mean 4.875603 -system.ruby.LD.latency_hist::gmean 3.591894 -system.ruby.LD.latency_hist::stdev 9.357158 -system.ruby.LD.latency_hist | 15001612 99.89% 99.89% | 13925 0.09% 99.99% | 816 0.01% 99.99% | 883 0.01% 100.00% | 364 0.00% 100.00% | 107 0.00% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.latency_hist::total 15017729 +system.ruby.LD.latency_hist::samples 15027912 +system.ruby.LD.latency_hist::mean 4.869020 +system.ruby.LD.latency_hist::gmean 3.591147 +system.ruby.LD.latency_hist::stdev 9.231737 +system.ruby.LD.latency_hist | 15011958 99.89% 99.89% | 13851 0.09% 99.99% | 851 0.01% 99.99% | 792 0.01% 100.00% | 329 0.00% 100.00% | 121 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist::total 15027912 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13626729 +system.ruby.LD.hit_latency_hist::samples 13637263 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13626729 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13626729 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13637263 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13637263 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1391000 -system.ruby.LD.miss_latency_hist::mean 23.249676 -system.ruby.LD.miss_latency_hist::gmean 20.961439 -system.ruby.LD.miss_latency_hist::stdev 23.942041 -system.ruby.LD.miss_latency_hist | 1374883 98.84% 98.84% | 13925 1.00% 99.84% | 816 0.06% 99.90% | 883 0.06% 99.96% | 364 0.03% 99.99% | 107 0.01% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1391000 -system.ruby.ST.latency_hist::bucket_size 256 -system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 9551572 -system.ruby.ST.latency_hist::mean 5.175450 -system.ruby.ST.latency_hist::gmean 3.300315 -system.ruby.ST.latency_hist::stdev 17.651145 -system.ruby.ST.latency_hist | 9545751 99.94% 99.94% | 3768 0.04% 99.98% | 2002 0.02% 100.00% | 25 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 9551572 +system.ruby.LD.miss_latency_hist::samples 1390649 +system.ruby.LD.miss_latency_hist::mean 23.197386 +system.ruby.LD.miss_latency_hist::gmean 20.952196 +system.ruby.LD.miss_latency_hist::stdev 23.468925 +system.ruby.LD.miss_latency_hist | 1374695 98.85% 98.85% | 13851 1.00% 99.85% | 851 0.06% 99.91% | 792 0.06% 99.97% | 329 0.02% 99.99% | 121 0.01% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1390649 +system.ruby.ST.latency_hist::bucket_size 128 +system.ruby.ST.latency_hist::max_bucket 1279 +system.ruby.ST.latency_hist::samples 9558783 +system.ruby.ST.latency_hist::mean 5.170026 +system.ruby.ST.latency_hist::gmean 3.300098 +system.ruby.ST.latency_hist::stdev 17.579302 +system.ruby.ST.latency_hist | 9544781 99.85% 99.85% | 8164 0.09% 99.94% | 1330 0.01% 99.95% | 2504 0.03% 99.98% | 1628 0.02% 100.00% | 340 0.00% 100.00% | 7 0.00% 100.00% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.latency_hist::total 9558783 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9200825 +system.ruby.ST.hit_latency_hist::samples 9207752 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9200825 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9200825 -system.ruby.ST.miss_latency_hist::bucket_size 256 -system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 350747 -system.ruby.ST.miss_latency_hist::mean 62.242032 -system.ruby.ST.miss_latency_hist::gmean 40.314149 -system.ruby.ST.miss_latency_hist::stdev 71.440751 -system.ruby.ST.miss_latency_hist | 344926 98.34% 98.34% | 3768 1.07% 99.41% | 2002 0.57% 99.99% | 25 0.01% 99.99% | 25 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 350747 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9207752 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9207752 +system.ruby.ST.miss_latency_hist::bucket_size 128 +system.ruby.ST.miss_latency_hist::max_bucket 1279 +system.ruby.ST.miss_latency_hist::samples 351031 +system.ruby.ST.miss_latency_hist::mean 62.091086 +system.ruby.ST.miss_latency_hist::gmean 40.236579 +system.ruby.ST.miss_latency_hist::stdev 71.074662 +system.ruby.ST.miss_latency_hist | 337029 96.01% 96.01% | 8164 2.33% 98.34% | 1330 0.38% 98.72% | 2504 0.71% 99.43% | 1628 0.46% 99.89% | 340 0.10% 99.99% | 7 0.00% 99.99% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 351031 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 127093107 -system.ruby.IFETCH.latency_hist::mean 3.119052 -system.ruby.IFETCH.latency_hist::gmean 3.036517 -system.ruby.IFETCH.latency_hist::stdev 2.234317 -system.ruby.IFETCH.latency_hist | 127086452 99.99% 99.99% | 5646 0.00% 100.00% | 489 0.00% 100.00% | 322 0.00% 100.00% | 142 0.00% 100.00% | 52 0.00% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 127093107 +system.ruby.IFETCH.latency_hist::samples 126996315 +system.ruby.IFETCH.latency_hist::mean 3.119134 +system.ruby.IFETCH.latency_hist::gmean 3.036572 +system.ruby.IFETCH.latency_hist::stdev 2.233716 +system.ruby.IFETCH.latency_hist | 126989642 99.99% 99.99% | 5673 0.00% 100.00% | 484 0.00% 100.00% | 317 0.00% 100.00% | 137 0.00% 100.00% | 55 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126996315 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 126277646 +system.ruby.IFETCH.hit_latency_hist::samples 126180135 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126277646 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 126277646 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126180135 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 126180135 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 815461 -system.ruby.IFETCH.miss_latency_hist::mean 21.554760 -system.ruby.IFETCH.miss_latency_hist::gmean 19.772157 -system.ruby.IFETCH.miss_latency_hist::stdev 20.880175 -system.ruby.IFETCH.miss_latency_hist | 808806 99.18% 99.18% | 5646 0.69% 99.88% | 489 0.06% 99.94% | 322 0.04% 99.98% | 142 0.02% 99.99% | 52 0.01% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 815461 +system.ruby.IFETCH.miss_latency_hist::samples 816180 +system.ruby.IFETCH.miss_latency_hist::mean 21.537108 +system.ruby.IFETCH.miss_latency_hist::gmean 19.766480 +system.ruby.IFETCH.miss_latency_hist::stdev 20.855244 +system.ruby.IFETCH.miss_latency_hist | 809507 99.18% 99.18% | 5673 0.70% 99.88% | 484 0.06% 99.94% | 317 0.04% 99.98% | 137 0.02% 99.99% | 55 0.01% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 816180 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 493320 -system.ruby.RMW_Read.latency_hist::mean 6.020587 -system.ruby.RMW_Read.latency_hist::gmean 3.953175 -system.ruby.RMW_Read.latency_hist::stdev 10.251324 -system.ruby.RMW_Read.latency_hist | 493147 99.96% 99.96% | 127 0.03% 99.99% | 17 0.00% 99.99% | 15 0.00% 100.00% | 9 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 493320 +system.ruby.RMW_Read.latency_hist::samples 494272 +system.ruby.RMW_Read.latency_hist::mean 6.020764 +system.ruby.RMW_Read.latency_hist::gmean 3.952362 +system.ruby.RMW_Read.latency_hist::stdev 10.313773 +system.ruby.RMW_Read.latency_hist | 494092 99.96% 99.96% | 129 0.03% 99.99% | 18 0.00% 99.99% | 18 0.00% 100.00% | 11 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 494272 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 428060 +system.ruby.RMW_Read.hit_latency_hist::samples 428940 system.ruby.RMW_Read.hit_latency_hist::mean 3 system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428060 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 428060 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 428940 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 65260 -system.ruby.RMW_Read.miss_latency_hist::mean 25.833527 -system.ruby.RMW_Read.miss_latency_hist::gmean 24.149766 -system.ruby.RMW_Read.miss_latency_hist::stdev 18.493474 -system.ruby.RMW_Read.miss_latency_hist | 65087 99.73% 99.73% | 127 0.19% 99.93% | 17 0.03% 99.96% | 15 0.02% 99.98% | 9 0.01% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 65260 +system.ruby.RMW_Read.miss_latency_hist::samples 65332 +system.ruby.RMW_Read.miss_latency_hist::mean 25.853716 +system.ruby.RMW_Read.miss_latency_hist::gmean 24.153784 +system.ruby.RMW_Read.miss_latency_hist::stdev 18.748956 +system.ruby.RMW_Read.miss_latency_hist | 65152 99.72% 99.72% | 129 0.20% 99.92% | 18 0.03% 99.95% | 18 0.03% 99.98% | 11 0.02% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65332 system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.latency_hist::samples 339680 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.345204 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780937 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.076413 -system.ruby.Locked_RMW_Read.latency_hist | 339429 99.93% 99.93% | 234 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 339680 +system.ruby.Locked_RMW_Read.latency_hist::samples 339654 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.351331 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780101 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.370233 +system.ruby.Locked_RMW_Read.latency_hist | 339398 99.92% 99.92% | 231 0.07% 99.99% | 12 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339654 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300571 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300589 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300571 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 300571 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300589 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 300589 system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39109 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.369199 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.378025 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.121215 -system.ruby.Locked_RMW_Read.miss_latency_hist | 38858 99.36% 99.36% | 234 0.60% 99.96% | 11 0.03% 99.98% | 3 0.01% 99.99% | 1 0.00% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 39109 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39065 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.443850 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.382210 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.468459 +system.ruby.Locked_RMW_Read.miss_latency_hist | 38809 99.34% 99.34% | 231 0.59% 99.94% | 12 0.03% 99.97% | 6 0.02% 99.98% | 4 0.01% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 39065 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 339680 +system.ruby.Locked_RMW_Write.latency_hist::samples 339654 system.ruby.Locked_RMW_Write.latency_hist::mean 3 system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 339680 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339680 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 339680 -system.ruby.Directory_Controller.Fetch 177916 0.00% 0.00% -system.ruby.Directory_Controller.Data 97855 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 178363 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 143156 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339654 +system.ruby.Directory_Controller.Fetch 177212 0.00% 0.00% +system.ruby.Directory_Controller.Data 97371 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 177674 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 142679 0.00% 0.00% system.ruby.Directory_Controller.DMA_READ 809 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 15288 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 177916 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 447 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 45301 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 447 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 45301 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 96058 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 362 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1435 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 15288 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 177916 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 96058 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1435 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1435 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 15060 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 177212 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 462 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 45308 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 462 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 45308 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 95596 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 347 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1428 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 15060 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 177212 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 95596 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 347 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 347 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1428 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1428 0.00% 0.00% system.ruby.DMA_Controller.ReadRequest | 809 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.ReadRequest::total 809 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% @@ -1067,169 +1065,169 @@ system.ruby.DMA_Controller.BUSY_RD.Data | 809 100.00% 100.00% | system.ruby.DMA_Controller.BUSY_RD.Data::total 809 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 6268725 41.74% 41.74% | 8749004 58.26% 100.00% -system.ruby.L1Cache_Controller.Load::total 15017729 -system.ruby.L1Cache_Controller.Ifetch | 68906101 54.22% 54.22% | 58187012 45.78% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 127093113 -system.ruby.L1Cache_Controller.Store | 5364359 50.02% 50.02% | 5359893 49.98% 100.00% -system.ruby.L1Cache_Controller.Store::total 10724252 -system.ruby.L1Cache_Controller.Inv | 15938 47.70% 47.70% | 17476 52.30% 100.00% -system.ruby.L1Cache_Controller.Inv::total 33414 -system.ruby.L1Cache_Controller.L1_Replacement | 827888 31.76% 31.76% | 1778547 68.24% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2606435 -system.ruby.L1Cache_Controller.Fwd_GETX | 12260 51.09% 51.09% | 11738 48.91% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 23998 -system.ruby.L1Cache_Controller.Fwd_GETS | 14169 56.03% 56.03% | 11118 43.97% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 25287 +system.ruby.L1Cache_Controller.Load | 6279317 41.78% 41.78% | 8748595 58.22% 100.00% +system.ruby.L1Cache_Controller.Load::total 15027912 +system.ruby.L1Cache_Controller.Ifetch | 68812914 54.18% 54.18% | 58183407 45.82% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126996321 +system.ruby.L1Cache_Controller.Store | 5372446 50.06% 50.06% | 5359917 49.94% 100.00% +system.ruby.L1Cache_Controller.Store::total 10732363 +system.ruby.L1Cache_Controller.Inv | 16157 48.07% 48.07% | 17455 51.93% 100.00% +system.ruby.L1Cache_Controller.Inv::total 33612 +system.ruby.L1Cache_Controller.L1_Replacement | 828605 31.79% 31.79% | 1777971 68.21% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2606576 +system.ruby.L1Cache_Controller.Fwd_GETX | 12248 51.07% 51.07% | 11736 48.93% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 23984 +system.ruby.L1Cache_Controller.Fwd_GETS | 14251 55.67% 55.67% | 11346 44.33% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 25597 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% -system.ruby.L1Cache_Controller.Data::total 1855 -system.ruby.L1Cache_Controller.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1282695 -system.ruby.L1Cache_Controller.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 25291 -system.ruby.L1Cache_Controller.Data_all_Acks | 578454 43.51% 43.51% | 751132 56.49% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1329586 -system.ruby.L1Cache_Controller.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% -system.ruby.L1Cache_Controller.Ack::total 22150 -system.ruby.L1Cache_Controller.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 24005 -system.ruby.L1Cache_Controller.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1687383 -system.ruby.L1Cache_Controller.NP.Load | 280457 20.44% 20.44% | 1091772 79.56% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1372229 -system.ruby.L1Cache_Controller.NP.Ifetch | 323032 39.65% 39.65% | 491723 60.35% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 814755 -system.ruby.L1Cache_Controller.NP.Store | 225423 53.48% 53.48% | 196076 46.52% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 421499 -system.ruby.L1Cache_Controller.NP.Inv | 4849 53.95% 53.95% | 4139 46.05% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 8988 -system.ruby.L1Cache_Controller.I.Load | 8492 45.24% 45.24% | 10279 54.76% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 18771 -system.ruby.L1Cache_Controller.I.Ifetch | 112 15.86% 15.86% | 594 84.14% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 706 -system.ruby.L1Cache_Controller.I.Store | 5744 50.09% 50.09% | 5723 49.91% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11467 -system.ruby.L1Cache_Controller.I.L1_Replacement | 9001 51.76% 51.76% | 8389 48.24% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 17390 -system.ruby.L1Cache_Controller.S.Load | 552961 51.86% 51.86% | 513218 48.14% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1066179 -system.ruby.L1Cache_Controller.S.Ifetch | 68582952 54.31% 54.31% | 57694694 45.69% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 126277646 -system.ruby.L1Cache_Controller.S.Store | 12149 54.85% 54.85% | 10001 45.15% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 22150 -system.ruby.L1Cache_Controller.S.Inv | 10866 45.32% 45.32% | 13108 54.68% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 23974 -system.ruby.L1Cache_Controller.S.L1_Replacement | 349852 38.80% 38.80% | 551810 61.20% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 901662 -system.ruby.L1Cache_Controller.E.Load | 1151502 29.73% 29.73% | 2721068 70.27% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3872570 -system.ruby.L1Cache_Controller.E.Store | 80746 48.37% 48.37% | 86187 51.63% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166933 -system.ruby.L1Cache_Controller.E.Inv | 47 57.32% 57.32% | 35 42.68% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 82 -system.ruby.L1Cache_Controller.E.L1_Replacement | 170526 15.32% 15.32% | 942229 84.68% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1112755 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 332 72.81% 72.81% | 124 27.19% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 456 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 992 45.23% 45.23% | 1201 54.77% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2193 -system.ruby.L1Cache_Controller.M.Load | 4275313 49.21% 49.21% | 4412667 50.79% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8687980 -system.ruby.L1Cache_Controller.M.Store | 5040297 49.89% 49.89% | 5061906 50.11% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10102203 -system.ruby.L1Cache_Controller.M.Inv | 176 47.57% 47.57% | 194 52.43% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 370 -system.ruby.L1Cache_Controller.M.L1_Replacement | 298509 51.95% 51.95% | 276119 48.05% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 574628 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 11928 50.67% 50.67% | 11614 49.33% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23542 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13177 57.06% 57.06% | 9917 42.94% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23094 +system.ruby.L1Cache_Controller.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% +system.ruby.L1Cache_Controller.Data::total 1840 +system.ruby.L1Cache_Controller.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 25601 +system.ruby.L1Cache_Controller.Data_all_Acks | 579316 43.50% 43.50% | 752306 56.50% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1331622 +system.ruby.L1Cache_Controller.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% +system.ruby.L1Cache_Controller.Ack::total 22455 +system.ruby.L1Cache_Controller.Ack_all | 13043 53.69% 53.69% | 11252 46.31% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 24295 +system.ruby.L1Cache_Controller.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1685450 +system.ruby.L1Cache_Controller.NP.Load | 280382 20.44% 20.44% | 1091184 79.56% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1371566 +system.ruby.L1Cache_Controller.NP.Ifetch | 323814 39.71% 39.71% | 491732 60.29% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 815546 +system.ruby.L1Cache_Controller.NP.Store | 225433 53.48% 53.48% | 196079 46.52% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 421512 +system.ruby.L1Cache_Controller.NP.Inv | 4849 54.09% 54.09% | 4115 45.91% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 8964 +system.ruby.L1Cache_Controller.I.Load | 8724 45.72% 45.72% | 10359 54.28% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 19083 +system.ruby.L1Cache_Controller.I.Ifetch | 100 15.77% 15.77% | 534 84.23% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 634 +system.ruby.L1Cache_Controller.I.Store | 5739 50.07% 50.07% | 5722 49.93% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11461 +system.ruby.L1Cache_Controller.I.L1_Replacement | 8993 51.78% 51.78% | 8375 48.22% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17368 +system.ruby.L1Cache_Controller.S.Load | 555624 51.88% 51.88% | 515377 48.12% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1071001 +system.ruby.L1Cache_Controller.S.Ifetch | 68488995 54.28% 54.28% | 57691140 45.72% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 126180135 +system.ruby.L1Cache_Controller.S.Store | 12225 54.44% 54.44% | 10230 45.56% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 22455 +system.ruby.L1Cache_Controller.S.Inv | 11078 45.79% 45.79% | 13115 54.21% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 24193 +system.ruby.L1Cache_Controller.S.L1_Replacement | 350718 38.81% 38.81% | 553040 61.19% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 903758 +system.ruby.L1Cache_Controller.E.Load | 1152084 29.74% 29.74% | 2722150 70.26% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3874234 +system.ruby.L1Cache_Controller.E.Store | 80726 48.37% 48.37% | 86165 51.63% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166891 +system.ruby.L1Cache_Controller.E.Inv | 52 59.77% 59.77% | 35 40.23% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 87 +system.ruby.L1Cache_Controller.E.L1_Replacement | 170402 15.34% 15.34% | 940436 84.66% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1110838 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 330 72.53% 72.53% | 125 27.47% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 455 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 996 45.17% 45.17% | 1209 54.83% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2205 +system.ruby.L1Cache_Controller.M.Load | 4282503 49.27% 49.27% | 4409525 50.73% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8692028 +system.ruby.L1Cache_Controller.M.Store | 5048323 49.93% 49.93% | 5061721 50.07% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10110044 +system.ruby.L1Cache_Controller.M.Inv | 178 48.37% 48.37% | 190 51.63% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 368 +system.ruby.L1Cache_Controller.M.L1_Replacement | 298492 51.95% 51.95% | 276120 48.05% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 574612 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11918 50.65% 50.65% | 11611 49.35% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23529 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13255 56.66% 56.66% | 10137 43.34% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23392 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1282695 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25291 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348115 38.75% 38.75% | 550360 61.25% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 898475 -system.ruby.L1Cache_Controller.IM.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1855 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230339 53.43% 53.43% | 200772 46.57% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431111 -system.ruby.L1Cache_Controller.SM.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 22150 -system.ruby.L1Cache_Controller.SM.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 24005 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25601 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348962 38.75% 38.75% | 551527 61.25% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 900489 +system.ruby.L1Cache_Controller.IM.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1840 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230354 53.43% 53.43% | 200779 46.57% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431133 +system.ruby.L1Cache_Controller.SM.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 22455 +system.ruby.L1Cache_Controller.SM.Ack_all | 13043 53.69% 53.69% | 11252 46.31% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 24295 system.ruby.L1Cache_Controller.M_I.Ifetch | 5 83.33% 83.33% | 1 16.67% 100.00% system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1687383 -system.ruby.L2Cache_Controller.L1_GET_INSTR 815461 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1391156 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 432966 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 22150 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1687383 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 95998 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 15348 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 177916 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 113143 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 23468 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2193 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1505 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7534 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 25291 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1737811 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 3594 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16427 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 34220 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 127269 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799004 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 83018 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1958 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22150 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 257 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7192 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1685450 +system.ruby.L2Cache_Controller.L1_GET_INSTR 816180 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1390821 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 432975 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 22455 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95536 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 15120 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 177212 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 112431 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23764 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2205 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1487 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7462 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 25601 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1736167 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 3550 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16316 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 33914 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 126982 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799834 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 84313 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1944 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22455 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 252 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7120 0.00% 0.00% system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1248475 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 279741 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 95619 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8056 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 1564 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1246825 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 280063 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 95163 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 7896 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1542 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 25287 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 23998 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1687383 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 122 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 100 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 25597 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 23984 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 121 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 104 0.00% 0.00% system.ruby.L2Cache_Controller.MT.MEM_Inv 230 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 113143 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 1564 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 310 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 42 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 112431 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1542 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 308 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 43 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.MEM_Inv 230 0.00% 0.00% system.ruby.L2Cache_Controller.MCT_I.WB_Data 60 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 40 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1245 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 7192 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 260 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 260 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 44 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1232 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 7120 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 255 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 255 0.00% 0.00% system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 34220 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 16427 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 127269 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 115 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24108 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 41 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1713703 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23085 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2191 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 15 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 13 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25276 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 33914 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 16316 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 126982 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 122 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24399 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 50 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1711768 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23385 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2205 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 11 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 11 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 25590 0.00% 0.00% ---------- End Simulation Statistics ---------- |