diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 3249 |
1 files changed, 1628 insertions, 1621 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 4fb206696..d9f455151 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.141985 # Number of seconds simulated -sim_ticks 5141984685500 # Number of ticks simulated -final_tick 5141984685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.140310 # Number of seconds simulated +sim_ticks 5140310078000 # Number of ticks simulated +final_tick 5140310078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264541 # Simulator instruction rate (inst/s) -host_op_rate 525842 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5597553756 # Simulator tick rate (ticks/s) -host_mem_usage 1010248 # Number of bytes of host memory used -host_seconds 918.61 # Real time elapsed on the host -sim_insts 243010444 # Number of instructions simulated -sim_ops 483045307 # Number of ops (including micro ops) simulated +host_inst_rate 269101 # Simulator instruction rate (inst/s) +host_op_rate 534933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5691143534 # Simulator tick rate (ticks/s) +host_mem_usage 1043812 # Number of bytes of host memory used +host_seconds 903.21 # Real time elapsed on the host +sim_insts 243055556 # Number of instructions simulated +sim_ops 483158347 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 439936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4996672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 212288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2043456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 288960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3313664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 444224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5333440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 157504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1822656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 355648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3199424 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11325056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 439936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 212288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 288960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 941184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9131200 # Number of bytes written to this memory -system.physmem.bytes_written::total 9131200 # Number of bytes written to this memory +system.physmem.bytes_read::total 11343552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 444224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 157504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 355648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 957376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9153408 # Number of bytes written to this memory +system.physmem.bytes_written::total 9153408 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6874 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3317 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 31929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4515 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 51776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 83335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2461 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 28479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 49991 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176954 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142675 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142675 # Number of write requests responded to by this memory +system.physmem.num_reads::total 177243 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143022 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143022 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 85558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 971740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 397406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 56196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 644433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2202468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 85558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 56196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 183039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1775812 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1775812 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1775812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 86420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1037572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 30641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 354581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 69188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 622418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2206784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 86420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 30641 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 69188 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 186249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1780711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1780711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1780711 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 85558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 971740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 397406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 56196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 644433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3978280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 91559 # Number of read requests accepted -system.physmem.writeReqs 81706 # Number of write requests accepted -system.physmem.readBursts 91559 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 81706 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5853184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 5229184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5859776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5229184 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 86420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1037572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 30641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 354581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 69188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 622418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3987495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 86962 # Number of read requests accepted +system.physmem.writeReqs 83127 # Number of write requests accepted +system.physmem.readBursts 86962 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83127 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5558208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 5320128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5565568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5320128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 24142 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5703 # Per bank write bursts -system.physmem.perBankRdBursts::1 4852 # Per bank write bursts -system.physmem.perBankRdBursts::2 5373 # Per bank write bursts -system.physmem.perBankRdBursts::3 5511 # Per bank write bursts -system.physmem.perBankRdBursts::4 5930 # Per bank write bursts -system.physmem.perBankRdBursts::5 4999 # Per bank write bursts -system.physmem.perBankRdBursts::6 5647 # Per bank write bursts -system.physmem.perBankRdBursts::7 5865 # Per bank write bursts -system.physmem.perBankRdBursts::8 5509 # Per bank write bursts -system.physmem.perBankRdBursts::9 5229 # Per bank write bursts -system.physmem.perBankRdBursts::10 5185 # Per bank write bursts -system.physmem.perBankRdBursts::11 5201 # Per bank write bursts -system.physmem.perBankRdBursts::12 6216 # Per bank write bursts -system.physmem.perBankRdBursts::13 6911 # Per bank write bursts -system.physmem.perBankRdBursts::14 6949 # Per bank write bursts -system.physmem.perBankRdBursts::15 6376 # Per bank write bursts -system.physmem.perBankWrBursts::0 5797 # Per bank write bursts -system.physmem.perBankWrBursts::1 4843 # Per bank write bursts -system.physmem.perBankWrBursts::2 5036 # Per bank write bursts -system.physmem.perBankWrBursts::3 5163 # Per bank write bursts -system.physmem.perBankWrBursts::4 5363 # Per bank write bursts -system.physmem.perBankWrBursts::5 4815 # Per bank write bursts -system.physmem.perBankWrBursts::6 4988 # Per bank write bursts -system.physmem.perBankWrBursts::7 5321 # Per bank write bursts -system.physmem.perBankWrBursts::8 4852 # Per bank write bursts -system.physmem.perBankWrBursts::9 4657 # Per bank write bursts -system.physmem.perBankWrBursts::10 4410 # Per bank write bursts -system.physmem.perBankWrBursts::11 4367 # Per bank write bursts -system.physmem.perBankWrBursts::12 5498 # Per bank write bursts -system.physmem.perBankWrBursts::13 5314 # Per bank write bursts -system.physmem.perBankWrBursts::14 5778 # Per bank write bursts -system.physmem.perBankWrBursts::15 5504 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 33935 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5197 # Per bank write bursts +system.physmem.perBankRdBursts::1 4660 # Per bank write bursts +system.physmem.perBankRdBursts::2 5410 # Per bank write bursts +system.physmem.perBankRdBursts::3 5303 # Per bank write bursts +system.physmem.perBankRdBursts::4 5131 # Per bank write bursts +system.physmem.perBankRdBursts::5 4781 # Per bank write bursts +system.physmem.perBankRdBursts::6 5593 # Per bank write bursts +system.physmem.perBankRdBursts::7 5451 # Per bank write bursts +system.physmem.perBankRdBursts::8 5257 # Per bank write bursts +system.physmem.perBankRdBursts::9 4895 # Per bank write bursts +system.physmem.perBankRdBursts::10 5205 # Per bank write bursts +system.physmem.perBankRdBursts::11 5208 # Per bank write bursts +system.physmem.perBankRdBursts::12 5485 # Per bank write bursts +system.physmem.perBankRdBursts::13 6574 # Per bank write bursts +system.physmem.perBankRdBursts::14 6603 # Per bank write bursts +system.physmem.perBankRdBursts::15 6094 # Per bank write bursts +system.physmem.perBankWrBursts::0 5588 # Per bank write bursts +system.physmem.perBankWrBursts::1 5124 # Per bank write bursts +system.physmem.perBankWrBursts::2 5267 # Per bank write bursts +system.physmem.perBankWrBursts::3 4836 # Per bank write bursts +system.physmem.perBankWrBursts::4 5431 # Per bank write bursts +system.physmem.perBankWrBursts::5 5206 # Per bank write bursts +system.physmem.perBankWrBursts::6 5103 # Per bank write bursts +system.physmem.perBankWrBursts::7 5105 # Per bank write bursts +system.physmem.perBankWrBursts::8 5093 # Per bank write bursts +system.physmem.perBankWrBursts::9 5184 # Per bank write bursts +system.physmem.perBankWrBursts::10 5317 # Per bank write bursts +system.physmem.perBankWrBursts::11 5091 # Per bank write bursts +system.physmem.perBankWrBursts::12 4613 # Per bank write bursts +system.physmem.perBankWrBursts::13 5363 # Per bank write bursts +system.physmem.perBankWrBursts::14 5354 # Per bank write bursts +system.physmem.perBankWrBursts::15 5452 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 5140984417000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 5136428746000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 91559 # Read request sizes (log2) +system.physmem.readPktSize::6 86962 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 81706 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 86389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83127 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 81204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -161,1114 +161,1119 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6655 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 276.476998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.125046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 300.303961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15966 39.83% 39.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9813 24.48% 64.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4306 10.74% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2350 5.86% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1723 4.30% 85.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1131 2.82% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 740 1.85% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 595 1.48% 91.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3460 8.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40084 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.316984 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 232.117398 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4096 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39704 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 273.985896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.719261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.548634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16089 40.52% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9815 24.72% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4115 10.36% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2259 5.69% 81.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1546 3.89% 85.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1077 2.71% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 717 1.81% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 581 1.46% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3505 8.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39704 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4014 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.636024 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 232.585773 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4011 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4098 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4098 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.938019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.673577 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.950142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 68 1.66% 1.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 4 0.10% 1.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 3 0.07% 1.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 4 0.10% 1.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3475 84.80% 86.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 74 1.81% 88.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.68% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 103 2.51% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 14 0.34% 92.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 88 2.15% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 45 1.10% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.12% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.20% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.20% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.05% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.10% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 126 3.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 13 0.32% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.05% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.37% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4098 # Writes before turning the bus around for reads -system.physmem.totQLat 1118460500 # Total ticks spent queuing -system.physmem.totMemAccLat 2833260500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 457280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12229.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4014 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4014 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.709268 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.149216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.865339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 66 1.64% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 4 0.10% 1.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.12% 1.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3286 81.86% 83.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 102 2.54% 86.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.77% 87.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 110 2.74% 89.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 16 0.40% 90.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 107 2.67% 92.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 56 1.40% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.07% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.30% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.50% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.10% 95.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 148 3.69% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.10% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 15 0.37% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.07% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.25% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4014 # Writes before turning the bus around for reads +system.physmem.totQLat 1058164225 # Total ticks spent queuing +system.physmem.totMemAccLat 2686545475 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 434235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12184.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30979.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30934.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.08 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.03 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.88 # Average write queue length when enqueuing -system.physmem.readRowHits 73104 # Number of row buffer hits during reads -system.physmem.writeRowHits 59973 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.40 # Row buffer hit rate for writes -system.physmem.avgGap 29671222.79 # Average gap between requests -system.physmem.pageHitRate 76.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 146323800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 79666125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 342256200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 267792480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96409908585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2240143266750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2587784324100 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.897651 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3686083069500 # Time in different power states -system.physmem_0.memoryStateTime::REF 128013860000 # Time in different power states +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 6.40 # Average write queue length when enqueuing +system.physmem.readRowHits 68775 # Number of row buffer hits during reads +system.physmem.writeRowHits 61495 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.98 # Row buffer hit rate for writes +system.physmem.avgGap 30198476.95 # Average gap between requests +system.physmem.pageHitRate 76.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 145461960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 79191750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 323902800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 269956800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96312598470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2240118682500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2587633207560 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.890236 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3686035921978 # Time in different power states +system.physmem_0.memoryStateTime::REF 128007880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 19995411750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19846503022 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 156711240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 371092800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 261662400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96741256995 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2232099467250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2580110601720 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.145421 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3685614437250 # Time in different power states -system.physmem_1.memoryStateTime::REF 128013860000 # Time in different power states +system.physmem_1.actEnergy 154700280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 84191250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 353503800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 268706160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96598721655 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2233305647250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2581148883675 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.102542 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3685636098978 # Time in different power states +system.physmem_1.memoryStateTime::REF 128007880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 20427995000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20213469772 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1069587616 # number of cpu cycles simulated +system.cpu0.numCycles 1072285216 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72296493 # Number of instructions committed -system.cpu0.committedOps 147472982 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 135372886 # Number of integer alu accesses +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu0.committedInsts 71949475 # Number of instructions committed +system.cpu0.committedOps 146629560 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134558001 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 990052 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14329607 # number of instructions that are conditional controls -system.cpu0.num_int_insts 135372886 # number of integer instructions +system.cpu0.num_func_calls 963710 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14252688 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134558001 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 248231827 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116398223 # number of times the integer registers were written +system.cpu0.num_int_register_reads 246915369 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115616478 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84256506 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56232303 # number of times the CC registers were written -system.cpu0.num_mem_refs 13832544 # number of memory refs -system.cpu0.num_load_insts 10299641 # Number of load instructions -system.cpu0.num_store_insts 3532903 # Number of store instructions -system.cpu0.num_idle_cycles 1014098909.517961 # Number of idle cycles -system.cpu0.num_busy_cycles 55488706.482039 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051879 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948121 # Percentage of idle cycles -system.cpu0.Branches 15685270 # Number of branches fetched -system.cpu0.op_class::No_OpClass 94460 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 133436032 90.48% 90.55% # Class of executed instruction -system.cpu0.op_class::IntMult 61341 0.04% 90.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 50787 0.03% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::MemRead 10297804 6.98% 97.60% # Class of executed instruction -system.cpu0.op_class::MemWrite 3532903 2.40% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83804950 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55920141 # number of times the CC registers were written +system.cpu0.num_mem_refs 13826864 # number of memory refs +system.cpu0.num_load_insts 10217566 # Number of load instructions +system.cpu0.num_store_insts 3609298 # Number of store instructions +system.cpu0.num_idle_cycles 1017808473.109560 # Number of idle cycles +system.cpu0.num_busy_cycles 54476742.890440 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050804 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949196 # Percentage of idle cycles +system.cpu0.Branches 15573120 # Number of branches fetched +system.cpu0.op_class::No_OpClass 93860 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132602493 90.43% 90.50% # Class of executed instruction +system.cpu0.op_class::IntMult 58992 0.04% 90.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 49730 0.03% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::MemRead 10215736 6.97% 97.54% # Class of executed instruction +system.cpu0.op_class::MemWrite 3609298 2.46% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 147473327 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1636478 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999449 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19597198 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1636990 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.971483 # Average number of references to valid blocks. +system.cpu0.op_class::total 146630109 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1637599 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999082 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19598772 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1638111 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.964252 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.606115 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 212.665668 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 114.727666 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360559 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.415363 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.224077 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.195837 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 211.604771 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 116.198475 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359757 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.413291 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.226950 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999998 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 241 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88196545 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88196545 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5063587 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2515932 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3866751 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11446270 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3403152 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1746042 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2940280 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8089474 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 21659 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10037 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 27859 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59555 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8466739 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4261974 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6807031 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19535744 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8488398 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4272011 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6834890 # number of overall hits -system.cpu0.dcache.overall_hits::total 19595299 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 370405 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 158702 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 782991 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1312098 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 124734 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 62333 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 138967 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 326034 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153415 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61804 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 191235 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406454 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 495139 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 221035 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 921958 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1638132 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 648554 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 282839 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1113193 # number of overall misses -system.cpu0.dcache.overall_misses::total 2044586 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2348294000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12545085500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14893379500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4136391991 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6933238397 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11069630388 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 6484685991 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 19478323897 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25963009888 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 6484685991 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 19478323897 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25963009888 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5433992 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2674634 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4649742 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12758368 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3527886 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1808375 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3079247 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8415508 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 175074 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 71841 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 219094 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466009 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8961878 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4483009 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7728989 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21173876 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9136952 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4554850 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7948083 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21639885 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.068164 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059336 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.168395 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.102842 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.035357 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034469 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.045130 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038742 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.876287 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.860289 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.872845 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.872202 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055249 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.049305 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.119286 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.077366 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070981 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.062096 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.140058 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.094482 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14796.877166 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16022.004723 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11350.813354 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 66359.584666 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 49891.257615 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 33952.380390 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 29337.824286 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21127.127154 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15849.156166 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22927.128122 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17497.706055 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12698.419087 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 213021 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 88194499 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88194499 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4977444 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2398985 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4079357 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11455786 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3466929 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1632241 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2982365 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8081535 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 21705 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9720 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 28159 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 59584 # 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number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8408176 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 179145 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 68443 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 218464 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 466052 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8953123 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4239829 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7980090 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21173042 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9132268 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4308272 # 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miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.857984 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.871105 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.872152 # miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.056824 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.049201 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115082 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.077255 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072949 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.062049 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135228 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.094375 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14654.361060 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16189.128450 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11427.191997 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 66580.830690 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 49284.446103 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31348.634727 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28389.287283 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20990.242910 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15405.352072 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22153.065901 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17387.243489 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12339.140939 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 206703 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 22215 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 22011 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.589061 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.390895 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1547054 # number of writebacks -system.cpu0.dcache.writebacks::total 1547054 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033523 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.034243 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019733 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.860275 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.857294 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.535678 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048909 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067435 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034971 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061706 # 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average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163230.829407 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183188.649425 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211831.864905 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 193783.994206 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165427.585585 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162033.525890 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163659.674907 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1548077 # number of writebacks +system.cpu0.dcache.writebacks::total 1548077 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 70 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 363716 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 363786 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1660 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 33557 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 35217 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1730 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 397273 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 399003 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1730 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 397273 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 399003 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 153356 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 421425 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 574781 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 53517 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99670 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 153187 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58722 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186896 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 245618 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 206873 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 521095 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 727968 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 265595 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 707991 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 973586 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 176326 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 193522 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 369848 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3494 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2876 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 6370 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 179820 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 196398 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 376218 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2092039500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 6051222000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8143261500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3446784995 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5707170401 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9153955396 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1012070500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2960619500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3972690000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 5538824495 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11758392401 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17297216896 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6550894995 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 14719011901 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21269906896 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30675451000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32998765500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63674216500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 673827500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 612020000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1285847500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31349278500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33610785500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64960064000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060083 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086633 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045028 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031715 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031991 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018219 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.857969 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.855500 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.527018 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048793 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065299 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034382 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061648 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086356 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.044992 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13641.719268 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14358.953550 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14167.589917 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64405.422483 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57260.664202 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59756.737817 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17234.946017 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15840.999807 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.262473 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26774.032837 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22564.776866 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23760.957756 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24664.978614 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20789.829109 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21846.972837 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173970.095165 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170516.868883 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172163.203532 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192852.747567 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212802.503477 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201859.890110 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174336.995329 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171136.088453 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172666.018107 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 856629 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.743625 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 130224655 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 857141 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 151.929093 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149031497500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 143.311880 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 129.505351 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 237.926394 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.279906 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.252940 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.464700 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997546 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 862079 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.743965 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129387157 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 862591 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 149.998269 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149036221500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.474513 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 126.887139 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 237.382314 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286083 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.247826 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.463637 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997547 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131961129 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131961129 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 88027171 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39361631 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2835853 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 130224655 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 88027171 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39361631 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2835853 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 130224655 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 88027171 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39361631 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2835853 # 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number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2702410000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5371996473 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8074406473 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2702410000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5371996473 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8074406473 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2702410000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5371996473 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8074406473 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 88358040 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39538574 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3207365 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 131103979 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 88358040 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39538574 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3207365 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 131103979 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 88358040 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39538574 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3207365 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 131103979 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003745 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004475 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115831 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006707 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003745 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004475 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115831 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006707 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003745 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004475 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115831 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006707 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15272.771457 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14459.819529 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9182.515743 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15272.771457 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14459.819529 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9182.515743 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15272.771457 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14459.819529 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9182.515743 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 11595 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 131136403 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 131136403 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 87656734 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38708215 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3022208 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129387157 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87656734 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38708215 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3022208 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129387157 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87656734 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38708215 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3022208 # number of overall hits +system.cpu0.icache.overall_hits::total 129387157 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 322605 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 163640 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 400399 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 886644 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 322605 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 163640 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 400399 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 886644 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 322605 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 163640 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 400399 # number of overall misses +system.cpu0.icache.overall_misses::total 886644 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2424218000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5939623464 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8363841464 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2424218000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5939623464 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8363841464 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2424218000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5939623464 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8363841464 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 87979339 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38871855 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3422607 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130273801 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 87979339 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38871855 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3422607 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130273801 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 87979339 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38871855 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3422607 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130273801 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003667 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004210 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116987 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006806 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003667 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004210 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116987 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006806 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003667 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004210 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116987 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006806 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14814.336348 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14834.261484 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9433.145055 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14814.336348 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14834.261484 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9433.145055 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14814.336348 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14834.261484 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9433.145055 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 13267 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 455 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 575 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.483516 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.073043 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22174 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 22174 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 22174 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 22174 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 22174 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 22174 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 176943 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 349338 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 526281 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 176943 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 349338 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 526281 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 176943 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 349338 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 526281 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2525467000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4769426473 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7294893473 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2525467000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4769426473 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7294893473 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2525467000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4769426473 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7294893473 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004014 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004014 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004014 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13861.213825 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13861.213825 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13861.213825 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 862079 # number of writebacks +system.cpu0.icache.writebacks::total 862079 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24042 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24042 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24042 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24042 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24042 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24042 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 163640 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376357 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 539997 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 163640 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 376357 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 539997 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 163640 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 376357 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 539997 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2260578000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5251926966 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7512504966 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2260578000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5251926966 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7512504966 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2260578000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5251926966 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7512504966 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004145 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004145 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004145 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13912.123523 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13912.123523 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13912.123523 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608369012 # number of cpu cycles simulated +system.cpu1.numCycles 2606017772 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35935781 # Number of instructions committed -system.cpu1.committedOps 69853480 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64823976 # Number of integer alu accesses +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.committedInsts 35434797 # Number of instructions committed +system.cpu1.committedOps 68967057 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63950611 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 488968 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6599189 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64823976 # number of integer instructions +system.cpu1.num_func_calls 471158 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6540301 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63950611 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120030856 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55861909 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118144126 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55187106 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36569866 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27235503 # number of times the CC registers were written -system.cpu1.num_mem_refs 4739526 # number of memory refs -system.cpu1.num_load_insts 2929606 # Number of load instructions -system.cpu1.num_store_insts 1809920 # Number of store instructions -system.cpu1.num_idle_cycles 2476291441.144386 # Number of idle cycles -system.cpu1.num_busy_cycles 132077570.855614 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050636 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949364 # Percentage of idle cycles -system.cpu1.Branches 7267259 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35769 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 65023245 93.08% 93.14% # Class of executed instruction -system.cpu1.op_class::IntMult 31643 0.05% 93.18% # Class of executed instruction -system.cpu1.op_class::IntDiv 24977 0.04% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::MemRead 2928241 4.19% 97.41% # Class of executed instruction -system.cpu1.op_class::MemWrite 1809920 2.59% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36132535 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26987071 # number of times the CC registers were written +system.cpu1.num_mem_refs 4484181 # number of memory refs +system.cpu1.num_load_insts 2795215 # Number of load instructions +system.cpu1.num_store_insts 1688966 # Number of store instructions +system.cpu1.num_idle_cycles 2475079667.780020 # Number of idle cycles +system.cpu1.num_busy_cycles 130938104.219980 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050245 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949755 # Percentage of idle cycles +system.cpu1.Branches 7181908 # Number of branches fetched +system.cpu1.op_class::No_OpClass 31577 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64398957 93.38% 93.42% # Class of executed instruction +system.cpu1.op_class::IntMult 30119 0.04% 93.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 23752 0.03% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::MemRead 2793855 4.05% 97.55% # Class of executed instruction +system.cpu1.op_class::MemWrite 1688966 2.45% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69853795 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28595724 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28595724 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 274281 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 25954960 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25419524 # Number of BTB hits +system.cpu1.op_class::total 68967226 # Class of executed instruction +system.cpu2.branchPred.lookups 28923329 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28923329 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 299282 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26177543 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25594622 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.937057 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 541766 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 58217 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155590039 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.773202 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 576797 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63162 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157005453 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9827756 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141445049 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28595724 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 25961290 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 144324316 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 577708 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 89529 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 4628 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9926 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 52140 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 25 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1381 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3207378 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 141789 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2491 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154597903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.800587 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.004500 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10540975 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142872413 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28923329 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26171419 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 144748563 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 631577 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 103277 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10569 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7821 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 68344 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 26 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1893 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3422619 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 155063 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2960 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 155796605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.805087 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.007326 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 100285595 64.87% 64.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 850088 0.55% 65.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23359910 15.11% 80.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 558025 0.36% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 768716 0.50% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 809103 0.52% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 512827 0.33% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 703407 0.45% 82.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 26750232 17.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 100986274 64.82% 64.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 876971 0.56% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23450168 15.05% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 581136 0.37% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 798057 0.51% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 839354 0.54% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 536255 0.34% 82.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 727896 0.47% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27000494 17.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154597903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.183789 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.909088 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8590820 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95748375 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 20322096 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4023271 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 289506 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 275783905 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 289506 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10203934 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 77122652 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4692669 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 22463307 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14202064 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 274713209 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 193941 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5398657 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 70031 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 7189088 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 328421156 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 598952608 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 367856783 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 202 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 317944423 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10476733 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 154897 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 156262 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19984245 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6287198 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3639298 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 400920 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 367403 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 273029174 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 403661 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 271361789 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 92310 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7713990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11716947 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 58327 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154597903 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.755275 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.385225 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 155796605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184219 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.909984 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9166270 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95860787 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22254534 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3994693 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 316440 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278480395 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 316440 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10781716 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77380942 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5123914 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24366684 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13623085 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277321096 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 194260 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5340054 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 70865 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 6669514 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331396172 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605049332 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371619608 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 206 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320040545 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11355627 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 162880 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 164114 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19801512 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6563978 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3714528 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 447098 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 397095 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275506715 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 407720 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273559358 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 95175 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8352705 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12694060 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 62726 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155796605 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.755875 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.385543 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 93164208 60.26% 60.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5135729 3.32% 63.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3649233 2.36% 65.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3187928 2.06% 68.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 23055647 14.91% 82.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2154571 1.39% 84.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23598215 15.26% 99.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 439899 0.28% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 212473 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 93882329 60.26% 60.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5118192 3.29% 63.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3721128 2.39% 65.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3254343 2.09% 68.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 23198440 14.89% 82.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2207021 1.42% 84.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23723391 15.23% 99.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 467418 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 224343 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154597903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155796605 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1212353 81.77% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 211907 14.29% 96.06% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 58391 3.94% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1207560 81.79% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 207213 14.03% 95.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 61669 4.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 71762 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 261142020 96.23% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 52428 0.02% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48121 0.02% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 75 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6661415 2.45% 98.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3385968 1.25% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 77609 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263069409 96.17% 96.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56423 0.02% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50250 0.02% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 74 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6863260 2.51% 98.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3442333 1.26% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 271361789 # Type of FU issued -system.cpu2.iq.rate 1.744082 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1482651 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.005464 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 698896144 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 281150786 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 269884047 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 272772537 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 141 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 697485 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 273559358 # Type of FU issued +system.cpu2.iq.rate 1.742356 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1476442 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.005397 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 704486629 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284271419 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272061524 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 309 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 274958042 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 149 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 723498 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1044107 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 5365 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4726 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 557112 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1134318 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5680 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5091 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 595155 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 749552 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 25864 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 712054 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 23601 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 289506 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 69224885 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 4893125 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 273432835 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 29776 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6287198 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3639298 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 235948 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 164149 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4411192 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4726 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 153905 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164065 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 317970 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 270855594 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6536848 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 455372 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 316440 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 69933639 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4486006 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275914435 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 35023 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6563978 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3714528 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 243237 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 162474 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4012628 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5091 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 167077 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 180895 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 347972 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273011944 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6727791 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 497508 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9843230 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27477788 # Number of branches executed -system.cpu2.iew.exec_stores 3306382 # Number of stores executed -system.cpu2.iew.exec_rate 1.740829 # Inst execution rate -system.cpu2.iew.wb_sent 270693369 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 269884157 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 210625616 # num instructions producing a value -system.cpu2.iew.wb_consumers 345602988 # num instructions consuming a value +system.cpu2.iew.exec_refs 10089541 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27708179 # Number of branches executed +system.cpu2.iew.exec_stores 3361750 # Number of stores executed +system.cpu2.iew.exec_rate 1.738869 # Inst execution rate +system.cpu2.iew.wb_sent 272840114 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272061642 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212265363 # num instructions producing a value +system.cpu2.iew.wb_consumers 348191102 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.734585 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609444 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.732817 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609623 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7711989 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 345334 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 277097 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 153447715 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.731657 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.637088 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8350016 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 344994 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 302940 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 154548999 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.731242 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.636335 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 96780970 63.07% 63.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4222028 2.75% 65.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1231000 0.80% 66.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24221852 15.79% 82.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 924771 0.60% 83.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 693299 0.45% 83.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 425605 0.28% 83.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 22935468 14.95% 98.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2012722 1.31% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 97452573 63.06% 63.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4255618 2.75% 65.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1276058 0.83% 66.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24388972 15.78% 82.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 952831 0.62% 83.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 707614 0.46% 83.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 433779 0.28% 83.77% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23017420 14.89% 98.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2064134 1.34% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 153447715 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 134778170 # Number of instructions committed -system.cpu2.commit.committedOps 265718845 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 154548999 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135671284 # Number of instructions committed +system.cpu2.commit.committedOps 267561730 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8325277 # Number of memory references committed -system.cpu2.commit.loads 5243091 # Number of loads committed -system.cpu2.commit.membars 153740 # Number of memory barriers committed -system.cpu2.commit.branches 27132938 # Number of branches committed +system.cpu2.commit.refs 8549033 # Number of memory references committed +system.cpu2.commit.loads 5429660 # Number of loads committed +system.cpu2.commit.membars 149565 # Number of memory barriers committed +system.cpu2.commit.branches 27339879 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 242753564 # Number of committed integer instructions. -system.cpu2.commit.function_calls 416792 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 41984 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 257254606 96.81% 96.83% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 50787 0.02% 96.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 46205 0.02% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5243061 1.97% 98.84% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3082186 1.16% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244517945 # Number of committed integer instructions. +system.cpu2.commit.function_calls 438137 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 46306 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 258863559 96.75% 96.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 54521 0.02% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48345 0.02% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5429610 2.03% 98.83% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3119373 1.17% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 265718845 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2012722 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 424836983 # The number of ROB reads -system.cpu2.rob.rob_writes 548017282 # The number of ROB writes -system.cpu2.timesIdled 100227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 992136 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4909996040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 134778170 # Number of Instructions Simulated -system.cpu2.committedOps 265718845 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.154416 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.154416 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.866239 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.866239 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 360832495 # number of integer regfile reads -system.cpu2.int_regfile_writes 216221900 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73134 # number of floating regfile reads -system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 137826475 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106107258 # number of cc regfile writes -system.cpu2.misc_regfile_reads 87959882 # number of misc regfile reads -system.cpu2.misc_regfile_writes 137617 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3552161 # Transaction distribution -system.iobus.trans_dist::ReadResp 3552161 # Transaction distribution -system.iobus.trans_dist::WriteReq 57740 # Transaction distribution -system.iobus.trans_dist::WriteResp 57740 # Transaction distribution -system.iobus.trans_dist::MessageReq 1667 # Transaction distribution -system.iobus.trans_dist::MessageResp 1667 # Transaction distribution +system.cpu2.commit.op_class_0::total 267561730 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2064134 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 428366748 # The number of ROB reads +system.cpu2.rob.rob_writes 553077080 # The number of ROB writes +system.cpu2.timesIdled 112413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1208848 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4910585835 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135671284 # Number of Instructions Simulated +system.cpu2.committedOps 267561730 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.157249 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.157249 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.864118 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.864118 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363754203 # number of integer regfile reads +system.cpu2.int_regfile_writes 218036965 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73086 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 138800226 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106739606 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88774953 # number of misc regfile reads +system.cpu2.misc_regfile_writes 143862 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3545348 # Transaction distribution +system.iobus.trans_dist::ReadResp 3545348 # Transaction distribution +system.iobus.trans_dist::WriteReq 57726 # Transaction distribution +system.iobus.trans_dist::WriteResp 57726 # Transaction distribution +system.iobus.trans_dist::MessageReq 1644 # Transaction distribution +system.iobus.trans_dist::MessageResp 1644 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066648 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7124546 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7223136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7110880 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7209436 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540117 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533324 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13934 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3568475 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6602951 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2194728 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3561720 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6596152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2378920 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3095000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5419500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 748000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 921000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 140118000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 199977500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 340000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 507000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8907000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11026500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 119418499 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 144387981 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 1052000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 295238000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 283491000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 23500000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 31080000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 920000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 979000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47573 # number of replacements -system.iocache.tags.tagsinuse 0.105025 # Cycle average of tags in use +system.iocache.tags.replacements 47579 # number of replacements +system.iocache.tags.tagsinuse 0.099877 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000694858009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.105025 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006564 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006564 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000697713509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.099877 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006242 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006242 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428652 # Number of tag accesses -system.iocache.tags.data_accesses 428652 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses -system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.tags.tag_accesses 428706 # Number of tag accesses +system.iocache.tags.data_accesses 428706 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses +system.iocache.ReadReq_misses::total 914 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses -system.iocache.demand_misses::total 908 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses -system.iocache.overall_misses::total 908 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 17834920 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 17834920 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3008484579 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 3008484579 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 17834920 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 17834920 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 17834920 # number of overall miss cycles -system.iocache.overall_miss_latency::total 17834920 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses +system.iocache.demand_misses::total 914 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses +system.iocache.overall_misses::total 914 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126880276 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 126880276 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3631346705 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3631346705 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 126880276 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 126880276 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 126880276 # number of overall miss cycles +system.iocache.overall_miss_latency::total 126880276 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1277,323 +1282,327 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 19641.982379 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 64393.933626 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 64393.933626 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 19641.982379 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 19641.982379 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 138818.682713 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77725.742830 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 77725.742830 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 138818.682713 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 138818.682713 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 745 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 69 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.797101 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 150 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 23200 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 23200 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 150 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 150 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 150 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 150 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10334920 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1848484579 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1848484579 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10334920 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10334920 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.165198 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.496575 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.496575 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.165198 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.165198 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68899.466667 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79676.059440 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79676.059440 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 756 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 756 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 27936 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 27936 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 756 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 756 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 756 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 756 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 89080276 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 2234546705 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2234546705 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 89080276 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 89080276 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.827133 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.597945 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.597945 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.827133 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.827133 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117831.052910 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79988.069337 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79988.069337 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 117831.052910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 117831.052910 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104099 # number of replacements -system.l2c.tags.tagsinuse 64798.751400 # Cycle average of tags in use -system.l2c.tags.total_refs 4622477 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168145 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.491017 # Average number of references to valid blocks. +system.l2c.tags.replacements 104604 # number of replacements +system.l2c.tags.tagsinuse 64807.192442 # Cycle average of tags in use +system.l2c.tags.total_refs 4639119 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168682 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.502158 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50975.916354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134600 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1575.171206 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4997.364493 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 516.989893 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1851.248692 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 5.076348 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 959.125226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3917.724589 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.777831 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51005.596123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.135096 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1646.370611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4933.032602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 515.170721 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1886.198863 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.247587 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 884.114832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3927.326006 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.778284 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.024035 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076254 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.028248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000077 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.014635 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.059780 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988750 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64046 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3569 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7409 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52933 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977264 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 41263442 # Number of tag accesses -system.l2c.tags.data_accesses 41263442 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 19237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10440 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 11603 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6238 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 52514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 10913 # number of ReadReq hits -system.l2c.ReadReq_hits::total 110945 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.025122 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075272 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007861 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.028781 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000141 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60263672500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000262 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829670 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.822884 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.408213 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.452781 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.378810 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.212834 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.009295 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021742 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.020912 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012854 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.071045 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.071045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033243 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 130338.709677 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70649.006623 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70774.285714 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70746.301775 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116170.600414 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119572.361059 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118240.532391 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124448.179097 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121442.420299 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 127706.092767 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126039.611101 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117015.785265 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121631.123891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 120369.010153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117015.785265 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121631.123891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 120369.010153 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161470.092329 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 158016.775870 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159663.153512 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181352.604465 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 201296.418637 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 190357.064364 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161856.420309 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158650.551431 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 160182.852761 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5081876 # Transaction distribution -system.membus.trans_dist::ReadResp 5130307 # Transaction distribution -system.membus.trans_dist::WriteReq 13937 # Transaction distribution -system.membus.trans_dist::WriteResp 13937 # Transaction distribution -system.membus.trans_dist::Writeback 142675 # Transaction distribution -system.membus.trans_dist::CleanEvict 8457 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1667 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1667 # Transaction distribution -system.membus.trans_dist::ReadExReq 129637 # Transaction distribution -system.membus.trans_dist::ReadExResp 129637 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 48432 # Transaction distribution -system.membus.trans_dist::MessageReq 1667 # Transaction distribution -system.membus.trans_dist::MessageResp 1667 # Transaction distribution -system.membus.trans_dist::BadAddressError 1 # Transaction distribution +system.membus.trans_dist::ReadReq 5063565 # Transaction distribution +system.membus.trans_dist::ReadResp 5112222 # Transaction distribution +system.membus.trans_dist::WriteReq 13898 # Transaction distribution +system.membus.trans_dist::WriteResp 13898 # Transaction distribution +system.membus.trans_dist::WritebackDirty 143022 # Transaction distribution +system.membus.trans_dist::CleanEvict 8552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1672 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1672 # Transaction distribution +system.membus.trans_dist::ReadExReq 129713 # Transaction distribution +system.membus.trans_dist::ReadExResp 129713 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48657 # Transaction distribution +system.membus.trans_dist::MessageReq 1644 # Transaction distribution +system.membus.trans_dist::MessageResp 1644 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3067080 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 461494 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10653122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142139 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142139 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10798595 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568475 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6134157 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17466624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27169256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3035200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3035200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30211124 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 409 # Total snoops (count) -system.membus.snoop_fanout::samples 5475610 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000304 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017446 # Request fanout histogram +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 462447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10617373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10762648 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6088089 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17501760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27151569 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3025152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30183297 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 664 # Total snoops (count) +system.membus.snoop_fanout::samples 5457993 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000301 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017353 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5473943 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1667 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5456349 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1644 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5475610 # Request fanout histogram -system.membus.reqLayer0.occupancy 227177500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5457993 # Request fanout histogram +system.membus.reqLayer0.occupancy 219248500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 301308000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 286800000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1840000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2377080 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 538434425 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 547350354 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 920000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1398080 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1326481306 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1208209380 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 41176558 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 52355698 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1815,60 +1822,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.snoop_filter.tot_requests 5040257 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2546109 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 319 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1148 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1148 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5045321 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2544604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1171 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1171 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 5235870 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7440960 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13939 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13939 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1628762 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 950991 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1645 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1645 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 289206 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 289206 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 857150 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1347950 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 920 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 23200 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2570707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15105454 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 66396 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 204903 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17947460 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54857344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213491432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 241048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 697376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 269287200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 238040 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10439686 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.005090 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.071166 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5213952 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7425084 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13900 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13900 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1631207 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 861736 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 94941 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1656 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1656 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289822 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289822 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 862602 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1349057 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 979 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 27936 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586927 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15072185 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 70382 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 205946 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17935440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110356800 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213581265 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 259408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 748104 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 324945577 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 226314 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8918759 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.005043 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.070832 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 10386543 99.49% 99.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 53143 0.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8873785 99.50% 99.50% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 44974 0.50% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10439686 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2709674498 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8918759 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3217757998 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 251420 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 405376 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 789952436 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 810539408 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1874874404 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1832719254 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23291487 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24003478 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 94859175 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 87328075 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |