diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 3257 |
1 files changed, 1645 insertions, 1612 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index df59304a0..e92014927 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,152 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.142345 # Number of seconds simulated -sim_ticks 5142345332000 # Number of ticks simulated -final_tick 5142345332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.145152 # Number of seconds simulated +sim_ticks 5145151650500 # Number of ticks simulated +final_tick 5145151650500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 328643 # Simulator instruction rate (inst/s) -host_op_rate 653294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6944434004 # Simulator tick rate (ticks/s) -host_mem_usage 993680 # Number of bytes of host memory used -host_seconds 740.50 # Real time elapsed on the host -sim_insts 243359937 # Number of instructions simulated -sim_ops 483763631 # Number of ops (including micro ops) simulated +host_inst_rate 272385 # Simulator instruction rate (inst/s) +host_op_rate 541465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5759353840 # Simulator tick rate (ticks/s) +host_mem_usage 1031560 # Number of bytes of host memory used +host_seconds 893.36 # Real time elapsed on the host +sim_insts 243336751 # Number of instructions simulated +sim_ops 483720414 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5043712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 148160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2254656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 338432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3039936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 460480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5461312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 120640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2033024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 372928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2832128 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11319616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 148160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 338432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 950464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9139904 # Number of bytes written to this memory -system.physmem.bytes_written::total 9139904 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7248 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2315 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5288 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 47499 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11311232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 460480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 120640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 372928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 954048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9134592 # Number of bytes written to this memory +system.physmem.bytes_written::total 9134592 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 85333 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1885 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 31766 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 32 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5827 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 44252 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176869 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142811 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142811 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 90206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 980819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 28812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 438449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 65813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 591157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2201256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 90206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 28812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 65813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 184831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1777380 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1777380 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1777380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 90206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 980819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 28812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 438449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 65813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 591157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3978636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 90808 # Number of read requests accepted -system.physmem.writeReqs 80864 # Number of write requests accepted -system.physmem.readBursts 90808 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 80864 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5799936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11776 # Total number of bytes read from write queue -system.physmem.bytesWritten 5173504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5811712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5175296 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 184 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 176738 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142728 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142728 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 89498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1061448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 23447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 395134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 72481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 550446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2198425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 89498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 23447 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 72481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 185427 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1775379 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1775379 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1775379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 89498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1061448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 23447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 395134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 72481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 550446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3973804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 84206 # Number of read requests accepted +system.physmem.writeReqs 79488 # Number of write requests accepted +system.physmem.readBursts 84206 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 79488 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5382080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 5087168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5389184 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5087232 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 28946 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5471 # Per bank write bursts -system.physmem.perBankRdBursts::1 4964 # Per bank write bursts -system.physmem.perBankRdBursts::2 5622 # Per bank write bursts -system.physmem.perBankRdBursts::3 5619 # Per bank write bursts -system.physmem.perBankRdBursts::4 5375 # Per bank write bursts -system.physmem.perBankRdBursts::5 4811 # Per bank write bursts -system.physmem.perBankRdBursts::6 5429 # Per bank write bursts -system.physmem.perBankRdBursts::7 5659 # Per bank write bursts -system.physmem.perBankRdBursts::8 5571 # Per bank write bursts -system.physmem.perBankRdBursts::9 5234 # Per bank write bursts -system.physmem.perBankRdBursts::10 5583 # Per bank write bursts -system.physmem.perBankRdBursts::11 5583 # Per bank write bursts -system.physmem.perBankRdBursts::12 6015 # Per bank write bursts -system.physmem.perBankRdBursts::13 6427 # Per bank write bursts -system.physmem.perBankRdBursts::14 6843 # Per bank write bursts -system.physmem.perBankRdBursts::15 6418 # Per bank write bursts -system.physmem.perBankWrBursts::0 5328 # Per bank write bursts -system.physmem.perBankWrBursts::1 5179 # Per bank write bursts -system.physmem.perBankWrBursts::2 4756 # Per bank write bursts -system.physmem.perBankWrBursts::3 4771 # Per bank write bursts -system.physmem.perBankWrBursts::4 5274 # Per bank write bursts -system.physmem.perBankWrBursts::5 4797 # Per bank write bursts -system.physmem.perBankWrBursts::6 4981 # Per bank write bursts -system.physmem.perBankWrBursts::7 4962 # Per bank write bursts -system.physmem.perBankWrBursts::8 4826 # Per bank write bursts -system.physmem.perBankWrBursts::9 4673 # Per bank write bursts -system.physmem.perBankWrBursts::10 4967 # Per bank write bursts -system.physmem.perBankWrBursts::11 4883 # Per bank write bursts -system.physmem.perBankWrBursts::12 5134 # Per bank write bursts -system.physmem.perBankWrBursts::13 5204 # Per bank write bursts -system.physmem.perBankWrBursts::14 5383 # Per bank write bursts -system.physmem.perBankWrBursts::15 5718 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5096 # Per bank write bursts +system.physmem.perBankRdBursts::1 4624 # Per bank write bursts +system.physmem.perBankRdBursts::2 5310 # Per bank write bursts +system.physmem.perBankRdBursts::3 5338 # Per bank write bursts +system.physmem.perBankRdBursts::4 5132 # Per bank write bursts +system.physmem.perBankRdBursts::5 4140 # Per bank write bursts +system.physmem.perBankRdBursts::6 4924 # Per bank write bursts +system.physmem.perBankRdBursts::7 5068 # Per bank write bursts +system.physmem.perBankRdBursts::8 5142 # Per bank write bursts +system.physmem.perBankRdBursts::9 4820 # Per bank write bursts +system.physmem.perBankRdBursts::10 5253 # Per bank write bursts +system.physmem.perBankRdBursts::11 5392 # Per bank write bursts +system.physmem.perBankRdBursts::12 5342 # Per bank write bursts +system.physmem.perBankRdBursts::13 6011 # Per bank write bursts +system.physmem.perBankRdBursts::14 6494 # Per bank write bursts +system.physmem.perBankRdBursts::15 6009 # Per bank write bursts +system.physmem.perBankWrBursts::0 5355 # Per bank write bursts +system.physmem.perBankWrBursts::1 5372 # Per bank write bursts +system.physmem.perBankWrBursts::2 5018 # Per bank write bursts +system.physmem.perBankWrBursts::3 4968 # Per bank write bursts +system.physmem.perBankWrBursts::4 5041 # Per bank write bursts +system.physmem.perBankWrBursts::5 4268 # Per bank write bursts +system.physmem.perBankWrBursts::6 4490 # Per bank write bursts +system.physmem.perBankWrBursts::7 4780 # Per bank write bursts +system.physmem.perBankWrBursts::8 5008 # Per bank write bursts +system.physmem.perBankWrBursts::9 4638 # Per bank write bursts +system.physmem.perBankWrBursts::10 4962 # Per bank write bursts +system.physmem.perBankWrBursts::11 5159 # Per bank write bursts +system.physmem.perBankWrBursts::12 4729 # Per bank write bursts +system.physmem.perBankWrBursts::13 5005 # Per bank write bursts +system.physmem.perBankWrBursts::14 5381 # Per bank write bursts +system.physmem.perBankWrBursts::15 5313 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 5141345197000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 5144151504000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 90808 # Read request sizes (log2) +system.physmem.readPktSize::6 84206 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 80864 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 79488 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -161,1038 +165,1041 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4423 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 273.144621 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.560811 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 297.725081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16113 40.11% 40.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9912 24.67% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4303 10.71% 75.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2413 6.01% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1642 4.09% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1065 2.65% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 735 1.83% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 648 1.61% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3343 8.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40174 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4096 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.121094 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 231.669266 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4094 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4096 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.735352 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.630791 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.122766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 68 1.66% 1.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 3 0.07% 1.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.12% 1.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3465 84.59% 86.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 91 2.22% 88.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.78% 89.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 114 2.78% 92.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 13 0.32% 92.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 74 1.81% 94.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 48 1.17% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.07% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.32% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.24% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.17% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.05% 96.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 111 2.71% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.10% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.05% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 16 0.39% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.07% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.15% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4096 # Writes before turning the bus around for reads -system.physmem.totQLat 1084591495 # Total ticks spent queuing -system.physmem.totMemAccLat 2783791495 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 453120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11968.04 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4576 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 271.729236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.741988 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 299.469956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15728 40.82% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9476 24.60% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4018 10.43% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2235 5.80% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1484 3.85% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1040 2.70% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 621 1.61% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 586 1.52% 91.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3340 8.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38528 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.323865 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 241.560167 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3765 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-14847 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3767 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3767 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.100876 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.013157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 16.139837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 73 1.94% 1.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 5 0.13% 2.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.05% 2.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 10 0.27% 2.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3150 83.62% 86.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 90 2.39% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 37 0.98% 89.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 29 0.77% 90.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 11 0.29% 90.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.40% 90.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 49 1.30% 92.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.13% 92.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 97 2.57% 94.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.13% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.13% 95.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.16% 95.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 56 1.49% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.05% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.11% 96.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.69% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 71 1.88% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.24% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.11% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3767 # Writes before turning the bus around for reads +system.physmem.totQLat 976693078 # Total ticks spent queuing +system.physmem.totMemAccLat 2553474328 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 420475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11614.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30718.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30364.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.79 # Average write queue length when enqueuing -system.physmem.readRowHits 72353 # Number of row buffer hits during reads -system.physmem.writeRowHits 58932 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.88 # Row buffer hit rate for writes -system.physmem.avgGap 29948653.23 # Average gap between requests -system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 144214560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 78573000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 335010000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 259511040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250484108160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96378538635 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2237986517250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2585666472645 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.978665 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3687486057488 # Time in different power states -system.physmem_0.memoryStateTime::REF 128059360000 # Time in different power states +system.physmem.avgWrQLen 6.49 # Average write queue length when enqueuing +system.physmem.readRowHits 66583 # Number of row buffer hits during reads +system.physmem.writeRowHits 58470 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.56 # Row buffer hit rate for writes +system.physmem.avgGap 31425412.68 # Average gap between requests +system.physmem.pageHitRate 76.45 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 137463480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 74835750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 309129600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254612160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250601076960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 95881334760 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2241313470000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2588571922710 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.897936 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3690036314984 # Time in different power states +system.physmem_0.memoryStateTime::REF 128119160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 19884905262 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19076389516 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 159500880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 86876625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 371841600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 264306240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250484108160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 97163933940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2232534954750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2581065522195 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.160201 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3686335779224 # Time in different power states -system.physmem_1.memoryStateTime::REF 128059360000 # Time in different power states +system.physmem_1.actEnergy 153808200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 83729250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 346803600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 260463600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250601076960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96592845240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2234121702750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2582160429600 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.130643 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3689011276980 # Time in different power states +system.physmem_1.memoryStateTime::REF 128119160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21009267026 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20078331770 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1088115959 # number of cpu cycles simulated +system.cpu0.numCycles 1088692410 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.committedInsts 71651877 # Number of instructions committed -system.cpu0.committedOps 146177129 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134125177 # Number of integer alu accesses +system.cpu0.committedInsts 72035509 # Number of instructions committed +system.cpu0.committedOps 146805199 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134737053 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 958449 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14231951 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134125177 # number of integer instructions +system.cpu0.num_func_calls 969730 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14267962 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134737053 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 245781224 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115362346 # number of times the integer registers were written +system.cpu0.num_int_register_reads 247210570 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115779061 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83627387 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55829285 # number of times the CC registers were written -system.cpu0.num_mem_refs 13623500 # number of memory refs -system.cpu0.num_load_insts 10168797 # Number of load instructions -system.cpu0.num_store_insts 3454703 # Number of store instructions -system.cpu0.num_idle_cycles 1031530406.657702 # Number of idle cycles -system.cpu0.num_busy_cycles 56585552.342298 # Number of busy cycles -system.cpu0.not_idle_fraction 0.052003 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.947997 # Percentage of idle cycles -system.cpu0.Branches 15545637 # Number of branches fetched -system.cpu0.op_class::No_OpClass 91075 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132356346 90.54% 90.61% # Class of executed instruction -system.cpu0.op_class::IntMult 58823 0.04% 90.65% # Class of executed instruction -system.cpu0.op_class::IntDiv 49650 0.03% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::MemRead 10166974 6.96% 97.64% # Class of executed instruction -system.cpu0.op_class::MemWrite 3454703 2.36% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83908421 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55985088 # number of times the CC registers were written +system.cpu0.num_mem_refs 13846193 # number of memory refs +system.cpu0.num_load_insts 10242461 # Number of load instructions +system.cpu0.num_store_insts 3603732 # Number of store instructions +system.cpu0.num_idle_cycles 1032281888.672235 # Number of idle cycles +system.cpu0.num_busy_cycles 56410521.327765 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051815 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948185 # Percentage of idle cycles +system.cpu0.Branches 15596726 # Number of branches fetched +system.cpu0.op_class::No_OpClass 94997 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132756064 90.43% 90.49% # Class of executed instruction +system.cpu0.op_class::IntMult 60391 0.04% 90.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 49910 0.03% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::MemRead 10240627 6.98% 97.55% # Class of executed instruction +system.cpu0.op_class::MemWrite 3603732 2.45% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146177571 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1639042 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999458 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19611882 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1639554 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.961718 # Average number of references to valid blocks. +system.cpu0.op_class::total 146805721 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1638200 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999475 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19659628 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1638712 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.997000 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 186.987910 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 208.755532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 116.256017 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.365211 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.407726 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.227063 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 187.218245 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 208.811458 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 115.969772 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.365661 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.407835 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.226503 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 215 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88233009 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88233009 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4935475 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2488884 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4043023 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11467382 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3326286 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1767826 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2988998 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8083110 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 21538 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9785 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 28212 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59535 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8261761 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4256710 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7032021 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19550492 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8283299 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4266495 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7060233 # number of overall hits -system.cpu0.dcache.overall_hits::total 19610027 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 366824 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 158843 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 779794 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1305461 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 124701 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 64481 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 137348 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 326530 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 154680 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59779 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 191883 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406342 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 491525 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 223324 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 917142 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1631991 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 646205 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 283103 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1109025 # number of overall misses -system.cpu0.dcache.overall_misses::total 2038333 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2324834000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12051133500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14375967500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4618815996 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6391491377 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11010307373 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 6943649996 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 18442624877 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25386274873 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 6943649996 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 18442624877 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25386274873 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5302299 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2647727 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4822817 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12772843 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3450987 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1832307 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3126346 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8409640 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 176218 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 69564 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 220095 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 465877 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8753286 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4480034 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7949163 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21182483 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8929504 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4549598 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8169258 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21648360 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.069182 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059992 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.161688 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.102206 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036135 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035191 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.043932 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038828 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.877776 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.859338 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.871819 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.872209 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.056153 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.049849 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115376 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.077044 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072367 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.062226 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135756 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.094156 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14636.049432 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15454.252662 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11012.176924 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 71630.650827 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46535.015996 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 33719.129553 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31092.269510 # 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miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.101065 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037294 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035867 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.042352 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.038780 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.878163 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.860410 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.871198 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.872160 # miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.056079 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.049813 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115419 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.076367 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072067 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.062779 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135830 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.093466 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14677.354760 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14308.788023 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10274.225766 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63929.575132 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48279.860893 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31558.777696 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 29033.558950 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 19124.733870 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14560.112687 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22668.765804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15811.908537 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11640.775535 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 181528 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 22224 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 21282 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.428186 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.529649 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1549010 # number of writebacks -system.cpu0.dcache.writebacks::total 1549010 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 70 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 358190 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 358260 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1746 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1351424500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31278342000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33745348000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65023690000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059966 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087419 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045438 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034238 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.033163 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019789 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.859324 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.856344 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.532877 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.049443 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.066080 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.035255 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061827 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087372 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.045964 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13624.045020 # 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average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24140.923273 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26922.310374 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20269.198481 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22149.941031 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173931.934171 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170384.488619 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172073.252169 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 194145.675266 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 206174.536501 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200300.059286 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174303.096162 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171010.586381 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172578.713669 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1548224 # number of writebacks +system.cpu0.dcache.writebacks::total 1548224 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 71 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 347686 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 347757 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1725 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 33527 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 35252 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1796 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 381213 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 383009 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1796 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 381213 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 383009 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 159234 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 418129 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 577363 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 63813 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92973 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 156786 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 63129 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 183547 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 246676 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 223047 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 511102 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 734149 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 286176 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 694649 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 980825 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 176076 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 193760 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 369836 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3149 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3340 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 6489 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 179225 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 197100 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 376325 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2175898000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5751483000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7927381000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3945399495 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5264356903 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9209756398 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1086717000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2791741000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3878458000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6121297495 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11015839903 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17137137398 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7208014495 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 13807580903 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21015595398 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30625317500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33009151000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63634468500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 615059500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 691101000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1306160500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31240377000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33700252000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64940629000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059272 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088133 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045089 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034923 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031128 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018634 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.860396 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.855326 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.529416 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.049415 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.066110 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034599 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.062387 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087424 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045231 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13664.782647 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13755.283656 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13730.323904 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61827.519393 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 56622.426973 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 58740.936040 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17214.228009 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15209.951675 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15722.883458 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27443.980394 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21553.114453 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23342.860098 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25187.347978 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19877.061513 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21426.447529 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173932.378632 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170361.018786 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172061.315015 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 195318.990156 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 206916.467066 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201288.411157 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174308.143395 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170980.476915 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172565.280011 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 863213 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.772348 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129563028 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 863725 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 150.004953 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149035233500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 148.852314 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 120.504208 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 241.415826 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.290727 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.235360 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.471515 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997602 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 861781 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.773422 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 130020592 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 862293 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 150.784701 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149035238500 # 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Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131315867 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131315867 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 87303659 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39282323 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2977046 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129563028 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87303659 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39282323 # 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number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 889099 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 304214 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 169918 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 414967 # number of overall misses -system.cpu0.icache.overall_misses::total 889099 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2488615500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6088929474 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8577544974 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2488615500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 6088929474 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8577544974 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2488615500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 6088929474 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8577544974 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87607873 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39452241 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3392013 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130452127 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87607873 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39452241 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3392013 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130452127 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87607873 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39452241 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3392013 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130452127 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003472 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004307 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122337 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006816 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003472 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004307 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122337 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006816 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003472 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004307 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122337 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006816 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14645.979237 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14673.286006 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9647.457678 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14645.979237 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14673.286006 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9647.457678 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14645.979237 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14673.286006 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9647.457678 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 13598 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 573 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.731239 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 131769548 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 131769548 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 87783032 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 39282832 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2954728 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 130020592 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87783032 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 39282832 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2954728 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 130020592 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87783032 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 39282832 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2954728 # number of overall hits +system.cpu0.icache.overall_hits::total 130020592 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 317380 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 167997 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 401278 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 886655 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 317380 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 167997 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 401278 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 886655 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 317380 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 167997 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 401278 # number of overall misses +system.cpu0.icache.overall_misses::total 886655 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2412041500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5992630472 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8404671972 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2412041500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5992630472 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8404671972 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2412041500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5992630472 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8404671972 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 88100412 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39450829 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3356006 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130907247 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 88100412 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39450829 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3356006 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130907247 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 88100412 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39450829 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3356006 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130907247 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003602 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004258 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.119570 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006773 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003602 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004258 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.119570 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006773 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003602 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004258 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.119570 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006773 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14357.646267 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14933.862489 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9479.078077 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14357.646267 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14933.862489 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9479.078077 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14357.646267 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14933.862489 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9479.078077 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 12794 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 161 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 565 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.644248 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 80.500000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 863213 # number of writebacks -system.cpu0.icache.writebacks::total 863213 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25359 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 25359 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 25359 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 25359 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 25359 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 25359 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 169918 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 389608 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 559526 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 169918 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 389608 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 559526 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 169918 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 389608 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 559526 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2318697500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5380005477 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7698702977 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2318697500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5380005477 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7698702977 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2318697500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5380005477 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7698702977 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004307 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114860 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004289 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004307 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114860 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004289 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004307 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114860 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004289 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13645.979237 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13808.765418 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13759.330178 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13645.979237 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13808.765418 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13759.330178 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13645.979237 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13808.765418 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13759.330178 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 861781 # number of writebacks +system.cpu0.icache.writebacks::total 861781 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24354 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24354 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24354 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24354 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24354 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24354 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 167997 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376924 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 544921 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 167997 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 376924 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 544921 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 167997 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 376924 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 544921 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2244044500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5288988973 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7533033473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2244044500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5288988973 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7533033473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2244044500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5288988973 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7533033473 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004258 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.112313 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004163 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004258 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.112313 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004163 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004258 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.112313 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004163 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.646267 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14031.977197 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13824.083625 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.646267 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 14031.977197 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13824.083625 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.646267 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 14031.977197 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13824.083625 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608019031 # number of cpu cycles simulated +system.cpu1.numCycles 2608700985 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 35872545 # Number of instructions committed -system.cpu1.committedOps 69699402 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64677814 # Number of integer alu accesses +system.cpu1.committedInsts 35853190 # Number of instructions committed +system.cpu1.committedOps 69637325 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64624192 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 478121 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6602854 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64677814 # number of integer instructions +system.cpu1.num_func_calls 480821 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6584072 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64624192 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119785728 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55703367 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119734930 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55665261 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36592003 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27221835 # number of times the CC registers were written -system.cpu1.num_mem_refs 4725252 # number of memory refs -system.cpu1.num_load_insts 2891470 # Number of load instructions -system.cpu1.num_store_insts 1833782 # Number of store instructions -system.cpu1.num_idle_cycles 2475574417.457654 # Number of idle cycles -system.cpu1.num_busy_cycles 132444613.542345 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050784 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949216 # Percentage of idle cycles -system.cpu1.Branches 7256649 # Number of branches fetched -system.cpu1.op_class::No_OpClass 36799 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64882747 93.09% 93.14% # Class of executed instruction -system.cpu1.op_class::IntMult 30615 0.04% 93.19% # Class of executed instruction -system.cpu1.op_class::IntDiv 25662 0.04% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::MemRead 2890134 4.15% 97.37% # Class of executed instruction -system.cpu1.op_class::MemWrite 1833782 2.63% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36441615 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27163948 # number of times the CC registers were written +system.cpu1.num_mem_refs 4762653 # number of memory refs +system.cpu1.num_load_insts 2934148 # Number of load instructions +system.cpu1.num_store_insts 1828505 # Number of store instructions +system.cpu1.num_idle_cycles 2477829433.289960 # Number of idle cycles +system.cpu1.num_busy_cycles 130871551.710040 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050167 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949833 # Percentage of idle cycles +system.cpu1.Branches 7242423 # Number of branches fetched +system.cpu1.op_class::No_OpClass 33618 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64788264 93.04% 93.08% # Class of executed instruction +system.cpu1.op_class::IntMult 30568 0.04% 93.13% # Class of executed instruction +system.cpu1.op_class::IntDiv 23981 0.03% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::MemRead 2932794 4.21% 97.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 1828505 2.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69699739 # Class of executed instruction -system.cpu2.branchPred.lookups 28904699 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28904699 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 301799 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26182960 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25618019 # Number of BTB hits +system.cpu1.op_class::total 69637730 # Class of executed instruction +system.cpu2.branchPred.lookups 28889322 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28889322 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 295969 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26161863 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25623496 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.842333 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 577766 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 65377 # Number of incorrect RAS predictions. -system.cpu2.numCycles 157028917 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.942169 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 568311 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63642 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155802495 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10756065 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142934226 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28904699 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26195785 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 144559167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 634442 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 102497 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 11445 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9293 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 61170 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 12 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1572 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3392030 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 159049 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2822 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 155817791 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.805701 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.007704 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10515897 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142640150 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28889322 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26191807 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 143559452 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 620364 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 87827 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9842 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 11126 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 54390 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 17 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1387 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3356023 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 154184 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2703 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154549468 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.817375 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.013614 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 100969926 64.80% 64.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 864181 0.55% 65.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23515186 15.09% 80.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 574321 0.37% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 784323 0.50% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 832797 0.53% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 526849 0.34% 82.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 721182 0.46% 82.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27029026 17.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 99785668 64.57% 64.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 851405 0.55% 65.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23501964 15.21% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 570178 0.37% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 787471 0.51% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 829399 0.54% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 530756 0.34% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 713885 0.46% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 26978742 17.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155817791 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.184072 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.910241 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9372643 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95636804 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 20963245 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4000269 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 317872 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278646605 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 317872 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10991831 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 77276692 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5181011 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 23079329 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13444163 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277492076 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 194116 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5314185 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 68849 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 6513408 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 331462631 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605120715 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371802312 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 234 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320362920 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11099709 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 163935 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 165202 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19836823 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6505105 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3734190 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 446981 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 391369 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275686580 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 411981 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273842853 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 94839 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8211456 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12322633 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 64605 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155817791 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.757456 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.386043 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154549468 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185423 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.915519 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9161947 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 94660451 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22362416 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3983614 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 310834 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278186393 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 310834 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10773754 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76930615 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4967111 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24468455 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13028558 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277047338 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 190678 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5336222 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 56223 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 6096944 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331227284 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 604004541 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 370955338 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 211 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 319831441 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11395843 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 155918 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 157041 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19693984 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6408841 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3580904 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 429275 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 378401 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275247067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 403961 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273265487 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 91844 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8373138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12782922 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 62096 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154549468 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.768143 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.389638 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 93841974 60.23% 60.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5140662 3.30% 63.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3701702 2.38% 65.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3241767 2.08% 67.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 23231728 14.91% 82.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2206356 1.42% 84.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23779364 15.26% 99.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 455294 0.29% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 218944 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 92779587 60.03% 60.03% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5028830 3.25% 63.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3690380 2.39% 65.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3236781 2.09% 67.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 23211705 15.02% 82.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2188888 1.42% 84.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23752986 15.37% 99.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 446110 0.29% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 214201 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155817791 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154549468 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1209883 81.76% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 208644 14.10% 95.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 61248 4.14% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1203384 82.42% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 197980 13.56% 95.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 58776 4.03% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 74059 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 263387979 96.18% 96.21% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56208 0.02% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48343 0.02% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 104 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6817856 2.49% 98.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3458304 1.26% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 71495 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263081199 96.27% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54839 0.02% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49922 0.02% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 90 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6697042 2.45% 98.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3310900 1.21% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273842853 # Type of FU issued -system.cpu2.iq.rate 1.743901 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1479775 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.005404 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 705077754 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284314372 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272343231 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 356 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 332 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275248392 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 717023 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 273265487 # Type of FU issued +system.cpu2.iq.rate 1.753922 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1460140 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.005343 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 702632101 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284028018 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 271786365 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 325 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 130 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 274653974 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 158 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 690819 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1119882 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 5658 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5248 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 603569 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1132838 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5529 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4669 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 589748 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 712184 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 25029 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 711826 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 19138 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 317872 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 69999671 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 4334406 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 276098561 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 36227 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6505105 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3734190 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 245180 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 161697 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3862519 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5248 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 168896 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 180792 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 349688 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273296807 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6682967 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 496833 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 310834 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 69908252 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4108684 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275651028 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 34465 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6408841 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3580904 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 237862 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 162562 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3635003 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4669 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 168040 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 174694 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 342734 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 272728091 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6566445 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 490893 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10058933 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27720177 # Number of branches executed -system.cpu2.iew.exec_stores 3375966 # Number of stores executed -system.cpu2.iew.exec_rate 1.740423 # Inst execution rate -system.cpu2.iew.wb_sent 273120714 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272343375 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212424693 # num instructions producing a value -system.cpu2.iew.wb_consumers 348436865 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.734352 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609650 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 8207919 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 347376 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 304652 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 154587808 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.732912 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.636931 # Number of insts commited each cycle +system.cpu2.iew.exec_refs 9797112 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27676327 # Number of branches executed +system.cpu2.iew.exec_stores 3230667 # Number of stores executed +system.cpu2.iew.exec_rate 1.750473 # Inst execution rate +system.cpu2.iew.wb_sent 272561668 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 271786495 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212223501 # num instructions producing a value +system.cpu2.iew.wb_consumers 348135650 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.744430 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609600 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 8370841 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 341865 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 298631 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153304959 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.743439 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.641523 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 97422616 63.02% 63.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4263028 2.76% 65.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1258481 0.81% 66.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24441508 15.81% 82.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 948995 0.61% 83.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 702646 0.45% 83.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 422583 0.27% 83.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23085730 14.93% 98.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2042221 1.32% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 96327195 62.83% 62.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4172265 2.72% 65.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1243558 0.81% 66.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24424351 15.93% 82.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 933210 0.61% 82.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 700271 0.46% 83.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 423861 0.28% 83.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23073889 15.05% 98.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2006359 1.31% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 154587808 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135835515 # Number of instructions committed -system.cpu2.commit.committedOps 267887100 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153304959 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135448052 # Number of instructions committed +system.cpu2.commit.committedOps 267277890 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8515843 # Number of memory references committed -system.cpu2.commit.loads 5385222 # Number of loads committed -system.cpu2.commit.membars 151391 # Number of memory barriers committed -system.cpu2.commit.branches 27354284 # Number of branches committed +system.cpu2.commit.refs 8267159 # Number of memory references committed +system.cpu2.commit.loads 5276003 # Number of loads committed +system.cpu2.commit.membars 150855 # Number of memory barriers committed +system.cpu2.commit.branches 27313126 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244770291 # Number of committed integer instructions. -system.cpu2.commit.function_calls 437535 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 44208 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 259226210 96.77% 96.78% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 54262 0.02% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 46624 0.02% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5385159 2.01% 98.83% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3130621 1.17% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244177571 # Number of committed integer instructions. +system.cpu2.commit.function_calls 431165 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 43823 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 258865945 96.85% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52891 0.02% 96.89% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48103 0.02% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5275956 1.97% 98.88% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2991156 1.12% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 267887100 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2042221 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 428611967 # The number of ROB reads -system.cpu2.rob.rob_writes 553425779 # The number of ROB writes -system.cpu2.timesIdled 117856 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1211126 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4911627157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135835515 # Number of Instructions Simulated -system.cpu2.committedOps 267887100 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.156023 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.156023 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.865035 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.865035 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364164831 # number of integer regfile reads -system.cpu2.int_regfile_writes 218212592 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73112 # number of floating regfile reads +system.cpu2.commit.op_class_0::total 267277890 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2006359 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 426921144 # The number of ROB reads +system.cpu2.rob.rob_writes 552547339 # The number of ROB writes +system.cpu2.timesIdled 113614 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1253027 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4915786083 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135448052 # Number of Instructions Simulated +system.cpu2.committedOps 267277890 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.150275 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.150275 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.869357 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.869357 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363036550 # number of integer regfile reads +system.cpu2.int_regfile_writes 217868300 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73154 # number of floating regfile reads system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138818129 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106823368 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88818544 # number of misc regfile reads -system.cpu2.misc_regfile_writes 142989 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3545369 # Transaction distribution -system.iobus.trans_dist::ReadResp 3545369 # Transaction distribution -system.iobus.trans_dist::WriteReq 57733 # Transaction distribution -system.iobus.trans_dist::WriteResp 57733 # Transaction distribution -system.iobus.trans_dist::MessageReq 1667 # Transaction distribution -system.iobus.trans_dist::MessageResp 1667 # Transaction distribution +system.cpu2.cc_regfile_reads 138663599 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106715601 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88486209 # number of misc regfile reads +system.cpu2.misc_regfile_writes 136274 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3545384 # Transaction distribution +system.iobus.trans_dist::ReadResp 3545384 # Transaction distribution +system.iobus.trans_dist::WriteReq 57740 # Transaction distribution +system.iobus.trans_dist::WriteResp 57740 # Transaction distribution +system.iobus.trans_dist::MessageReq 1683 # Transaction distribution +system.iobus.trans_dist::MessageResp 1683 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066646 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1182 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27866 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27896 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7110938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7209538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7110986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3366 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3366 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7209614 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533323 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2364 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13933 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13948 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3561710 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6596226 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2386632 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3561695 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6732 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6732 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6596259 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2351548 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 41000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 6479000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5836500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 921000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 921500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) @@ -1202,68 +1209,68 @@ system.iobus.reqLayer7.occupancy 21000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 199976000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 478500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 454000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 170000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11054500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10925000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 117264991 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 135494828 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1060500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 284201000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 283574000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 25798000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 29242000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 987000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 969000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47578 # number of replacements -system.iocache.tags.tagsinuse 0.106179 # Cycle average of tags in use +system.iocache.tags.replacements 47576 # number of replacements +system.iocache.tags.tagsinuse 0.114834 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47594 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 5000689447509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.106179 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006636 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006636 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.114834 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007177 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007177 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428697 # Number of tag accesses -system.iocache.tags.data_accesses 428697 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses -system.iocache.ReadReq_misses::total 913 # number of ReadReq misses +system.iocache.tags.tag_accesses 428679 # Number of tag accesses +system.iocache.tags.data_accesses 428679 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 913 # number of demand (read+write) misses -system.iocache.demand_misses::total 913 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 913 # number of overall misses -system.iocache.overall_misses::total 913 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126475754 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 126475754 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2945894237 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2945894237 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 126475754 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 126475754 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 126475754 # number of overall miss cycles -system.iocache.overall_miss_latency::total 126475754 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 911 # number of demand (read+write) misses +system.iocache.demand_misses::total 911 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 911 # number of overall misses +system.iocache.overall_misses::total 911 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130436776 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130436776 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3277643052 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3277643052 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 130436776 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 130436776 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 130436776 # number of overall miss cycles +system.iocache.overall_miss_latency::total 130436776 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 913 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 913 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 913 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 913 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 911 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 911 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 911 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 911 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1272,327 +1279,341 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138527.660460 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 138527.660460 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 63054.243086 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 63054.243086 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138527.660460 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 138527.660460 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138527.660460 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 138527.660460 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 657 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143179.776070 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 143179.776070 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70155.031079 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 70155.031079 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 143179.776070 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 143179.776070 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 143179.776070 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 143179.776070 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 254 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 59 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.135593 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.043478 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 755 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 755 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 22656 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 22656 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 755 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 755 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 755 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 755 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88725754 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88725754 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1813094237 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1813094237 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88725754 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 88725754 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88725754 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 88725754 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.826944 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.826944 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.484932 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.484932 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.826944 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.826944 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.826944 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.826944 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117517.554967 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80027.111450 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80027.111450 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117517.554967 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117517.554967 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 757 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 757 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 26096 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 26096 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 757 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 757 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 757 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 757 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92586776 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92586776 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1971782289 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1971782289 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 92586776 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 92586776 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 92586776 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 92586776 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.830955 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.830955 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.558562 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.558562 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.830955 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.830955 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.830955 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.830955 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 122307.498018 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 122307.498018 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75558.794030 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75558.794030 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 122307.498018 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 122307.498018 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 122307.498018 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 122307.498018 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104233 # number of replacements -system.l2c.tags.tagsinuse 64807.184468 # Cycle average of tags in use -system.l2c.tags.total_refs 4648895 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.601512 # Average number of references to valid blocks. +system.l2c.tags.replacements 104171 # number of replacements +system.l2c.tags.tagsinuse 64805.453766 # Cycle average of tags in use +system.l2c.tags.total_refs 4641601 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168365 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.568681 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50959.111320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.136263 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1606.978228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4944.954504 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 496.939087 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1891.921055 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.257150 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 951.270746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3946.616114 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.777574 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50961.018177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131592 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1604.778639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4964.722322 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 496.770357 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1893.527022 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.992586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.004519 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 948.195899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3929.312654 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.777603 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.024521 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075454 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007583 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.028868 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.014515 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.060221 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988879 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64196 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 668 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3069 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5065 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55320 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979553 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 41479817 # Number of tag accesses -system.l2c.tags.data_accesses 41479817 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 19668 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10402 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 11752 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6500 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 59100 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 12594 # number of ReadReq hits -system.l2c.ReadReq_hits::total 120016 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.024487 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075756 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007580 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.028893 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000107 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.014468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.059957 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.988853 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64194 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 76 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3073 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6656 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54343 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979523 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1231508000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 29003212500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31239791000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60243003500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000593 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000083 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.796729 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.839161 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.425364 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.428290 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.375181 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.213812 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011220 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.015459 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.008944 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021789 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.016437 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.010920 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011220 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.111962 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015459 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.064279 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.032235 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.111962 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015459 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.064279 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.032235 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 139718.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 137000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 139636.363636 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67978.005865 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68098.611111 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68039.942939 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116754.770149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119097.797610 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118069.914193 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120466.843501 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 125488.074138 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124260.763485 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122832.817337 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124750.430074 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124119.859034 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120466.843501 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117675.225831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 139718.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 137000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 125488.074138 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 120350.461702 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119700.925903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120466.843501 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117675.225831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 139718.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 137000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 125488.074138 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 120350.461702 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119700.925903 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161432.375792 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157860.902663 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159561.252826 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183818.831375 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 195407.934132 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189783.942056 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161825.707909 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158497.163876 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 160082.384907 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5063475 # Transaction distribution -system.membus.trans_dist::ReadResp 5112044 # Transaction distribution -system.membus.trans_dist::WriteReq 13928 # Transaction distribution -system.membus.trans_dist::WriteResp 13928 # Transaction distribution -system.membus.trans_dist::WritebackDirty 142811 # Transaction distribution -system.membus.trans_dist::CleanEvict 8387 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1702 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1702 # Transaction distribution -system.membus.trans_dist::ReadExReq 129429 # Transaction distribution -system.membus.trans_dist::ReadExResp 129429 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 48569 # Transaction distribution -system.membus.trans_dist::MessageReq 1667 # Transaction distribution -system.membus.trans_dist::MessageResp 1667 # Transaction distribution +system.membus.trans_dist::ReadReq 5063492 # Transaction distribution +system.membus.trans_dist::ReadResp 5112114 # Transaction distribution +system.membus.trans_dist::WriteReq 13953 # Transaction distribution +system.membus.trans_dist::WriteResp 13953 # Transaction distribution +system.membus.trans_dist::WritebackDirty 142728 # Transaction distribution +system.membus.trans_dist::CleanEvict 8956 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1657 # Transaction distribution +system.membus.trans_dist::UpgradeResp 756 # Transaction distribution +system.membus.trans_dist::ReadExReq 129246 # Transaction distribution +system.membus.trans_dist::ReadExResp 129246 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48622 # Transaction distribution +system.membus.trans_dist::MessageReq 1683 # Transaction distribution +system.membus.trans_dist::MessageResp 1683 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110938 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3043868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 461232 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10616038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10761354 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561710 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6087733 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17454144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27103587 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3025152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30135407 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 824 # Total snoops (count) -system.membus.snoop_fanout::samples 5457240 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000305 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017475 # Request fanout histogram +system.membus.trans_dist::InvalidateResp 20624 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3043904 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 460036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10614926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 116428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 116428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10734720 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6732 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6732 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561695 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6087805 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17447936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27097436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3024896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3024896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30129064 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 713 # Total snoops (count) +system.membus.snoop_fanout::samples 5457064 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000308 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017559 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5455573 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1667 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5455381 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1683 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5457240 # Request fanout histogram -system.membus.reqLayer0.occupancy 220305500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5457064 # Request fanout histogram +system.membus.reqLayer0.occupancy 219508500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 286836500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 286793500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2385368 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2349452 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 534782231 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 523492338 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1398368 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1380452 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1230215238 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1192096252 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 43264654 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 3875571 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1812,60 +1845,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.snoop_filter.tot_requests 5045999 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2542699 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 716 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1209 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1209 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5037396 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2536385 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 720 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1161 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1161 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 5211020 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7425092 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13930 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13930 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1629876 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 862717 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 95523 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1686 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1686 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 289480 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 289480 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 863740 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1350844 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 987 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 22656 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2590172 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15076396 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 68863 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 204307 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17939738 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110491648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213734051 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 254408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 750576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 325230683 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 223463 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8879878 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.004588 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.067577 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5204527 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7416348 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13955 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13955 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1627719 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 861781 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 95177 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1648 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1648 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289427 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289427 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 862301 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1350048 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 969 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 26096 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586381 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15074051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 68680 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 194868 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17923980 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110341120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213628444 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 723128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 324949652 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 219979 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8897461 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.004125 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.064090 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 8839140 99.54% 99.54% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 40738 0.46% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8860763 99.59% 99.59% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 36698 0.41% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8879878 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3300004999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8897461 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3238433000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 437354 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 410366 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 839896281 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 817982794 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1865125250 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1843572784 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24363482 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 22804980 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 87735122 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 80183573 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |