diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 2956 |
1 files changed, 1476 insertions, 1480 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index e884e1c2d..2b6efde37 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137942 # Number of seconds simulated -sim_ticks 5137941673500 # Number of ticks simulated -final_tick 5137941673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137456 # Number of seconds simulated +sim_ticks 5137456264000 # Number of ticks simulated +final_tick 5137456264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248874 # Simulator instruction rate (inst/s) -host_op_rate 494699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5246911955 # Simulator tick rate (ticks/s) -host_mem_usage 994832 # Number of bytes of host memory used -host_seconds 979.23 # Real time elapsed on the host -sim_insts 243705182 # Number of instructions simulated -sim_ops 484425104 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2466368 # Number of bytes read from this memory +host_inst_rate 176189 # Simulator instruction rate (inst/s) +host_op_rate 350219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3709429360 # Simulator tick rate (ticks/s) +host_mem_usage 1030148 # Number of bytes of host memory used +host_seconds 1384.97 # Real time elapsed on the host +sim_insts 244016231 # Number of instructions simulated +sim_ops 485043652 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2422400 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 426944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5894144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1789248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 385728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2633280 # Number of bytes read from this memory -system.physmem.bytes_read::total 13744640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 426944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 385728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 959872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9091584 # Number of bytes written to this memory -system.physmem.bytes_written::total 9091584 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38537 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 383808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5693376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 137536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1729152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 448384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2947264 # Number of bytes read from this memory +system.physmem.bytes_read::total 13764480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 383808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 137536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 448384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9086592 # Number of bytes written to this memory +system.physmem.bytes_written::total 9086592 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37850 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6671 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 92096 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 27957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6027 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41145 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214760 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142056 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142056 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 480030 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 5997 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 88959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 27018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 46051 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141978 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141978 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 471517 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 83096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1147180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 28650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 348242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 75074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 512517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2675126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 83096 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 28650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 75074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 186820 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1769499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1769499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1769499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 480030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1108209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 336577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 87277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 573682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2679240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 87277 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1768695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1768695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1768695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 471517 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 83096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1147180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 28650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 75074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 512517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4444625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 100936 # Number of read requests accepted -system.physmem.writeReqs 78380 # Number of write requests accepted -system.physmem.readBursts 100936 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 78380 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6458816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue -system.physmem.bytesWritten 5015040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6459904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5016320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 74708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1108209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 336577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 87277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 573682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4447935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 102292 # Number of read requests accepted +system.physmem.writeReqs 78374 # Number of write requests accepted +system.physmem.readBursts 102292 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 78374 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6544384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2304 # Total number of bytes read from write queue +system.physmem.bytesWritten 5015936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6546688 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5015936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 699 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5898 # Per bank write bursts -system.physmem.perBankRdBursts::1 6403 # Per bank write bursts -system.physmem.perBankRdBursts::2 6411 # Per bank write bursts -system.physmem.perBankRdBursts::3 6523 # Per bank write bursts -system.physmem.perBankRdBursts::4 6306 # Per bank write bursts -system.physmem.perBankRdBursts::5 6840 # Per bank write bursts -system.physmem.perBankRdBursts::6 6199 # Per bank write bursts -system.physmem.perBankRdBursts::7 6896 # Per bank write bursts -system.physmem.perBankRdBursts::8 5528 # Per bank write bursts -system.physmem.perBankRdBursts::9 5898 # Per bank write bursts -system.physmem.perBankRdBursts::10 6128 # Per bank write bursts -system.physmem.perBankRdBursts::11 6570 # Per bank write bursts -system.physmem.perBankRdBursts::12 6317 # Per bank write bursts -system.physmem.perBankRdBursts::13 6334 # Per bank write bursts -system.physmem.perBankRdBursts::14 6542 # Per bank write bursts -system.physmem.perBankRdBursts::15 6126 # Per bank write bursts -system.physmem.perBankWrBursts::0 4721 # Per bank write bursts -system.physmem.perBankWrBursts::1 4902 # Per bank write bursts -system.physmem.perBankWrBursts::2 4923 # Per bank write bursts -system.physmem.perBankWrBursts::3 5159 # Per bank write bursts -system.physmem.perBankWrBursts::4 5192 # Per bank write bursts -system.physmem.perBankWrBursts::5 5457 # Per bank write bursts -system.physmem.perBankWrBursts::6 4843 # Per bank write bursts -system.physmem.perBankWrBursts::7 5797 # Per bank write bursts -system.physmem.perBankWrBursts::8 4085 # Per bank write bursts -system.physmem.perBankWrBursts::9 4367 # Per bank write bursts -system.physmem.perBankWrBursts::10 4807 # Per bank write bursts -system.physmem.perBankWrBursts::11 4903 # Per bank write bursts -system.physmem.perBankWrBursts::12 4884 # Per bank write bursts -system.physmem.perBankWrBursts::13 4699 # Per bank write bursts -system.physmem.perBankWrBursts::14 5116 # Per bank write bursts -system.physmem.perBankWrBursts::15 4505 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 862 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6805 # Per bank write bursts +system.physmem.perBankRdBursts::1 7244 # Per bank write bursts +system.physmem.perBankRdBursts::2 6375 # Per bank write bursts +system.physmem.perBankRdBursts::3 6857 # Per bank write bursts +system.physmem.perBankRdBursts::4 6927 # Per bank write bursts +system.physmem.perBankRdBursts::5 6780 # Per bank write bursts +system.physmem.perBankRdBursts::6 5925 # Per bank write bursts +system.physmem.perBankRdBursts::7 6310 # Per bank write bursts +system.physmem.perBankRdBursts::8 5868 # Per bank write bursts +system.physmem.perBankRdBursts::9 5795 # Per bank write bursts +system.physmem.perBankRdBursts::10 5783 # Per bank write bursts +system.physmem.perBankRdBursts::11 6231 # Per bank write bursts +system.physmem.perBankRdBursts::12 6160 # Per bank write bursts +system.physmem.perBankRdBursts::13 6316 # Per bank write bursts +system.physmem.perBankRdBursts::14 6211 # Per bank write bursts +system.physmem.perBankRdBursts::15 6669 # Per bank write bursts +system.physmem.perBankWrBursts::0 5462 # Per bank write bursts +system.physmem.perBankWrBursts::1 5811 # Per bank write bursts +system.physmem.perBankWrBursts::2 4880 # Per bank write bursts +system.physmem.perBankWrBursts::3 5445 # Per bank write bursts +system.physmem.perBankWrBursts::4 5542 # Per bank write bursts +system.physmem.perBankWrBursts::5 5461 # Per bank write bursts +system.physmem.perBankWrBursts::6 4520 # Per bank write bursts +system.physmem.perBankWrBursts::7 4685 # Per bank write bursts +system.physmem.perBankWrBursts::8 4152 # Per bank write bursts +system.physmem.perBankWrBursts::9 4422 # Per bank write bursts +system.physmem.perBankWrBursts::10 4208 # Per bank write bursts +system.physmem.perBankWrBursts::11 4507 # Per bank write bursts +system.physmem.perBankWrBursts::12 4889 # Per bank write bursts +system.physmem.perBankWrBursts::13 4664 # Per bank write bursts +system.physmem.perBankWrBursts::14 4834 # Per bank write bursts +system.physmem.perBankWrBursts::15 4892 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 5136941479000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5136272146500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 100936 # Read request sizes (log2) +system.physmem.readPktSize::6 102292 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 78380 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 75816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 78374 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -163,226 +163,227 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.217991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.094116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1121.662575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16547 46.47% 46.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5535 15.54% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3551 9.97% 71.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2213 6.22% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1334 3.75% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1101 3.09% 85.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 807 2.27% 87.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 584 1.64% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 515 1.45% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 517 1.45% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 309 0.87% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 309 0.87% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 205 0.58% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 200 0.56% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 177 0.50% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 272 0.76% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 139 0.39% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 84 0.24% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 95 0.27% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 94 0.26% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 81 0.23% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 178 0.50% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 83 0.23% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 58 0.16% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 45 0.13% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 38 0.11% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 29 0.08% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 19 0.05% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 15 0.04% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 14 0.04% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 11 0.03% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 8 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 6 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 8 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 5 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 8 0.02% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 3 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 5 0.01% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 6 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 6 0.02% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 4 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 3 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 3 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 20 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 2 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 2 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 2 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 2 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 3 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 2 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 2 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 3 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 12 0.03% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 6 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 10 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 3 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 5 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 9 0.03% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 8 0.02% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 29 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35607 # Bytes accessed per row activation -system.physmem.totQLat 2741683498 # Total ticks spent queuing -system.physmem.totMemAccLat 4643457248 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 504595000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1397178750 # Total ticks spent accessing banks -system.physmem.avgQLat 27167.17 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13844.56 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 37207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.623700 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.064630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1005.971949 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16908 45.44% 45.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5765 15.49% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3845 10.33% 71.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2398 6.45% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1477 3.97% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1206 3.24% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 882 2.37% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 634 1.70% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 564 1.52% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 479 1.29% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 331 0.89% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 285 0.77% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 209 0.56% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 204 0.55% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 197 0.53% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 303 0.81% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 153 0.41% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 117 0.31% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 75 0.20% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 61 0.16% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 106 0.28% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 199 0.53% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 97 0.26% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.23% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 45 0.12% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 43 0.12% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 26 0.07% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 28 0.08% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 16 0.04% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 12 0.03% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 10 0.03% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 17 0.05% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 7 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 10 0.03% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 3 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 7 0.02% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 9 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 4 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 6 0.02% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 13 0.03% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 4 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 4 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 7 0.02% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 24 0.06% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 10 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 25 0.07% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 2 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 23 0.06% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 5 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 2 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 2 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 4 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.02% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 3 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 11 0.03% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 14 0.04% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 22 0.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37207 # Bytes accessed per row activation +system.physmem.totQLat 2596442750 # Total ticks spent queuing +system.physmem.totMemAccLat 4566061500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 511280000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1458338750 # Total ticks spent accessing banks +system.physmem.avgQLat 25391.59 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14261.64 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46011.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44653.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -390,322 +391,318 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.11 # Average write queue length when enqueuing -system.physmem.readRowHits 85240 # Number of row buffer hits during reads -system.physmem.writeRowHits 58432 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes -system.physmem.avgGap 28647423.98 # Average gap between requests -system.physmem.pageHitRate 80.13 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6427951 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 423177 # Transaction distribution -system.membus.trans_dist::ReadResp 423176 # Transaction distribution -system.membus.trans_dist::WriteReq 6474 # Transaction distribution -system.membus.trans_dist::WriteResp 6474 # Transaction distribution -system.membus.trans_dist::Writeback 78380 # Transaction distribution -system.membus.trans_dist::UpgradeReq 714 # Transaction distribution -system.membus.trans_dist::UpgradeResp 714 # Transaction distribution -system.membus.trans_dist::ReadExReq 80216 # Transaction distribution -system.membus.trans_dist::ReadExResp 80216 # Transaction distribution -system.membus.trans_dist::MessageReq 892 # Transaction distribution -system.membus.trans_dist::MessageResp 892 # Transaction distribution -system.membus.trans_dist::BadAddressError 1 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 310648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497624 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 207711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1015985 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 78748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 78748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1096517 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159467 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995245 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8228608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9383320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 3247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12634504 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32719620 # Total data (bytes) -system.membus.snoop_data_through_bus 306816 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 163512000 # Layer occupancy (ticks) +system.physmem.readRowHits 86197 # Number of row buffer hits during reads +system.physmem.writeRowHits 57226 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes +system.physmem.avgGap 28429655.53 # Average gap between requests +system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.13 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6440814 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 424797 # Transaction distribution +system.membus.trans_dist::ReadResp 424797 # Transaction distribution +system.membus.trans_dist::WriteReq 7056 # Transaction distribution +system.membus.trans_dist::WriteResp 7056 # Transaction distribution +system.membus.trans_dist::Writeback 78374 # Transaction distribution +system.membus.trans_dist::UpgradeReq 877 # Transaction distribution +system.membus.trans_dist::UpgradeResp 877 # Transaction distribution +system.membus.trans_dist::ReadExReq 80570 # Transaction distribution +system.membus.trans_dist::ReadExResp 80570 # Transaction distribution +system.membus.trans_dist::MessageReq 957 # Transaction distribution +system.membus.trans_dist::MessageResp 957 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 221000 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1030868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 68894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1101676 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160435 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995417 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8741760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9897612 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2820864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2820864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12722304 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32756791 # Total data (bytes) +system.membus.snoop_data_through_bus 332608 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 164980499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315210000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315323500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1784000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1914000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 830204748 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 859913497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 892000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1595294481 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1658568572 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 252511249 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 223775499 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 103855 # number of replacements -system.l2c.tags.tagsinuse 64822.347448 # Cycle average of tags in use -system.l2c.tags.total_refs 3646219 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167877 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.719586 # Average number of references to valid blocks. +system.l2c.tags.replacements 103968 # number of replacements +system.l2c.tags.tagsinuse 64819.095791 # Cycle average of tags in use +system.l2c.tags.total_refs 3669692 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168243 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.811855 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51292.264352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121895 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1278.615227 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4499.945934 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 292.458405 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1505.357985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.212632 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1370.507166 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4576.860668 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.782658 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51211.809516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121912 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1304.363790 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4492.907273 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 251.742289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1518.622796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.780510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.958868 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1352.233300 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4674.555536 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.781430 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019510 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068664 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004463 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020912 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.069837 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989111 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 19693 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10326 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 346717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 513928 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10907 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 155624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 223811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 47020 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 9087 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 331652 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 566093 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2240790 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.019903 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.068556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003841 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000180 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.020633 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.071328 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989061 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21716 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11486 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 326601 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 505560 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10498 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5651 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 148959 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223967 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 55385 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 11312 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 366888 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 576803 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2264826 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1542501 # number of Writeback hits -system.l2c.Writeback_hits::total 1542501 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 58 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 254 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 70841 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 36082 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 59675 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166598 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 19693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10328 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 346717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 584769 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10907 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5932 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 155624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 259893 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 47020 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 9087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 331652 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 625768 # number of demand (read+write) hits -system.l2c.demand_hits::total 2407390 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19693 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10328 # number of overall hits -system.l2c.overall_hits::cpu0.inst 346717 # number of overall hits -system.l2c.overall_hits::cpu0.data 584769 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10907 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5932 # number of overall hits -system.l2c.overall_hits::cpu1.inst 155624 # number of overall hits -system.l2c.overall_hits::cpu1.data 259893 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 47020 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 9087 # number of overall hits -system.l2c.overall_hits::cpu2.inst 331652 # number of overall hits -system.l2c.overall_hits::cpu2.data 625768 # number of overall hits -system.l2c.overall_hits::total 2407390 # number of overall hits +system.l2c.Writeback_hits::writebacks 1544272 # number of Writeback hits +system.l2c.Writeback_hits::total 1544272 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 123 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 38 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 95 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 256 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65648 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 35064 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 65209 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 165921 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21716 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 11488 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 326601 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 571208 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10498 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5651 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 148959 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 259031 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 55385 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 11312 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 366888 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 642012 # number of demand (read+write) hits +system.l2c.demand_hits::total 2430749 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 21716 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 11488 # number of overall hits +system.l2c.overall_hits::cpu0.inst 326601 # number of overall hits +system.l2c.overall_hits::cpu0.data 571208 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10498 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5651 # number of overall hits +system.l2c.overall_hits::cpu1.inst 148959 # number of overall hits +system.l2c.overall_hits::cpu1.data 259031 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 55385 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 11312 # number of overall hits +system.l2c.overall_hits::cpu2.inst 366888 # number of overall hits +system.l2c.overall_hits::cpu2.data 642012 # number of overall hits +system.l2c.overall_hits::total 2430749 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6671 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 16268 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2301 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4539 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 22 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 6029 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 11901 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47736 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 761 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 281 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 269 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1311 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76320 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 23649 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 29451 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 129420 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 5997 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 15878 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2150 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4005 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 34 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 7008 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 12968 # number of ReadReq misses +system.l2c.ReadReq_misses::total 48046 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 707 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 185 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 493 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1385 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 73415 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 23238 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 33467 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130120 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6671 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 92588 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2301 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 28188 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 22 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 6029 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 41352 # number of demand (read+write) misses -system.l2c.demand_misses::total 177156 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5997 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 89293 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 27243 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 34 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 7008 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 46435 # number of demand (read+write) misses +system.l2c.demand_misses::total 178166 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6671 # number of overall misses -system.l2c.overall_misses::cpu0.data 92588 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2301 # number of overall misses -system.l2c.overall_misses::cpu1.data 28188 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 22 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu2.inst 6029 # number of overall misses -system.l2c.overall_misses::cpu2.data 41352 # number of overall misses -system.l2c.overall_misses::total 177156 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 178484750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 352246744 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2002250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 488673998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 943243246 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1964725488 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 3587383 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 3136875 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 6724258 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1676320610 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2179701143 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 3856021753 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 178484750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2028567354 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 2002250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 488673998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3122944389 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 5820747241 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 178484750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2028567354 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 2002250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 488673998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3122944389 # number of overall miss cycles -system.l2c.overall_miss_latency::total 5820747241 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 19693 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10330 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 353388 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 530196 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10907 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 157925 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 228350 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 47042 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 9088 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 337681 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 577994 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2288526 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 5997 # number of overall misses +system.l2c.overall_misses::cpu0.data 89293 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2150 # number of overall misses +system.l2c.overall_misses::cpu1.data 27243 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 34 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu2.inst 7008 # number of overall misses +system.l2c.overall_misses::cpu2.data 46435 # number of overall misses +system.l2c.overall_misses::total 178166 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 161561250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 314335492 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2727499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 170750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 583607489 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1035968985 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2098371465 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 3143902 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 6170749 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9314651 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1653854893 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2482673598 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 4136528491 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 161561250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1968190385 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 2727499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 170750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 583607489 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3518642583 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6234899956 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 161561250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1968190385 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 2727499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 170750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 583607489 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3518642583 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6234899956 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 21716 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 11490 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 332598 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 521438 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10498 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 151109 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 227972 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 55419 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 11314 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 373896 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 589771 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2312872 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1542501 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1542501 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 900 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 339 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1565 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 147161 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 59731 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 89126 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296018 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 19693 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10332 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 353388 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 677357 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10907 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5932 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 157925 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 288081 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 47042 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 9088 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 337681 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 667120 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2584546 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 19693 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10332 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 353388 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 677357 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10907 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5932 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 157925 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 288081 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 47042 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 9088 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 337681 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 667120 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2584546 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000387 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018877 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.030683 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014570 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.019877 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000110 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.017854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.020590 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020859 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.845556 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828909 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.825153 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.837700 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.518616 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.395925 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.330442 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.437203 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000387 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018877 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.136690 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014570 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.097847 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000110 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.017854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.061986 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.068544 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000387 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018877 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.136690 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014570 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.097847 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000110 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.017854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.061986 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.068544 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77568.339852 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77604.482045 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 81053.905789 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 79257.478027 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 41158.150830 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12766.487544 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11661.245353 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5129.106026 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70883.361241 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74011.108044 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 29794.635705 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 77568.339852 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71965.636228 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 81053.905789 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 75520.999927 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 32856.619256 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 77568.339852 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71965.636228 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 81053.905789 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 75520.999927 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 32856.619256 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1544272 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1544272 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 830 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 223 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 588 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1641 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 139063 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 58302 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 98676 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296041 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 21716 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 11492 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 332598 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 660501 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10498 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5651 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 151109 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 286274 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 55419 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 11314 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 373896 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 688447 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2608915 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 21716 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 11492 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 332598 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 660501 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10498 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5651 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 151109 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 286274 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 55419 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 11314 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 373896 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 688447 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2608915 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000348 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018031 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.030450 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014228 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017568 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000614 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000177 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.018743 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.021988 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020773 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.851807 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829596 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.838435 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.843998 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.527926 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.398580 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.339160 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.439534 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000348 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018031 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.135190 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014228 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.095164 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000614 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000177 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.018743 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.067449 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.068291 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000348 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018031 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.135190 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014228 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.095164 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000614 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000177 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.018743 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.067449 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.068291 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75144.767442 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78485.765793 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 80220.558824 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 85375 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 83277.324344 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 79886.565777 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 43674.217729 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16994.064865 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12516.732252 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6725.379783 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71170.276831 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74182.735172 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 31790.105218 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75144.767442 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 72245.728628 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 80220.558824 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 85375 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 83277.324344 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75775.655928 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 34994.892157 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75144.767442 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 72245.728628 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 80220.558824 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 85375 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 83277.324344 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75775.655928 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 34994.892157 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -714,131 +711,131 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95389 # number of writebacks -system.l2c.writebacks::total 95389 # number of writebacks +system.l2c.writebacks::writebacks 95311 # number of writebacks +system.l2c.writebacks::total 95311 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.inst 2301 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4539 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 22 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 6027 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 11901 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 24791 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 281 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 269 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 550 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 23649 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 29451 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 53100 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2301 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 28188 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 22 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 6027 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 41352 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 77891 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2301 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 28188 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 22 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 6027 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 41352 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 77891 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 149580250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 295478756 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 413107752 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 794213750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1654174258 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3410269 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 2847765 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 6258034 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1378867890 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1809513813 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 3188381703 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 149580250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1674346646 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 413107752 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2603727563 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4842555961 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 149580250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1674346646 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 413107752 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2603727563 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4842555961 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28165267500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30426261500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58591529000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 495358500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 671313500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1166672000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28660626000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31097575000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59758201000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019877 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.020590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.010833 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828909 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.825153 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.351438 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.395925 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.330442 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.179381 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.030137 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.030137 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65097.765147 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66735.043274 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 66724.789561 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12136.188612 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10586.486989 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11378.243636 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58305.547380 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61441.506672 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60044.853164 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu1.inst 2150 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4005 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 34 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 7006 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 12968 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 26165 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 185 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 493 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 678 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 23238 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 33467 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 56705 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2150 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 27243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 34 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 7006 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 46435 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 82870 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2150 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 27243 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 34 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 7006 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 46435 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 82870 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 134244250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 264246008 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2308001 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 145750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 495740261 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 873454007 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1770138277 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2450173 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 5190488 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 7640661 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1355864107 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2052275856 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3408139963 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 134244250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1620110115 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2308001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 145750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 495740261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2925729863 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5178278240 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 134244250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1620110115 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2308001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 145750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 495740261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2925729863 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5178278240 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28143642000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30477969500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58621611500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 483707000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 766316000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1250023000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28627349000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31244285500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59871634500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014228 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017568 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000614 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000177 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.018738 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021988 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.011313 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829596 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.838435 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.413163 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.398580 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.339160 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.191544 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014228 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.095164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000614 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000177 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.018738 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.067449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.031764 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014228 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.095164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000614 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000177 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.018738 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.067449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.031764 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62439.186047 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65979.028215 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 72875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 70759.386383 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67354.565623 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 67652.905676 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 13244.178378 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10528.373225 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11269.411504 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58346.850288 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61322.372964 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60102.988502 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62439.186047 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59468.858606 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 72875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70759.386383 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63006.996081 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62486.765295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62439.186047 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59468.858606 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 72875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70759.386383 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63006.996081 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62486.765295 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -849,39 +846,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.094274 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.092731 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000200819009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094274 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005892 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5000213887009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092731 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005796 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005796 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129801048 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129801048 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6845673540 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6845673540 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6975474588 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6975474588 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6975474588 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6975474588 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135882017 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 135882017 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5955673280 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5955673280 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6091555297 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6091555297 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6091555297 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6091555297 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -890,56 +887,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142638.514286 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142638.514286 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 146525.546661 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 146525.546661 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 146451.282553 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 146451.282553 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 105453 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 149485.167217 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 149485.167217 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 127475.883562 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 127475.883562 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127895.930987 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127895.930987 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 91729 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6453 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5124 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.341702 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 17.901835 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 724 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 27280 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 27280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 28004 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 28004 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 28004 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 28004 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92126548 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 92126548 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 5426189542 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5426189542 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5518316090 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5518316090 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.795604 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.795604 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.583904 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.583904 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.587949 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.587949 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127246.613260 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127246.613260 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 198907.241276 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 198907.241276 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 754 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 754 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24064 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 24064 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 24818 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 24818 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 24818 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 24818 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96648017 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96648017 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4703544282 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4703544282 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4800192299 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4800192299 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.829483 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.829483 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.515068 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.515068 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.521069 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.521069 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 128180.393899 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128180.393899 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195459.785655 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 195459.785655 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -953,459 +950,458 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52188015 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1787129 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1786595 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6474 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6474 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 905502 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 665 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 665 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 176137 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 148862 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 991248 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3625702 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34347 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 125379 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4776676 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31718784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120252184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 463592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152554720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268001344 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 137632 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5049278590 # Layer occupancy (ticks) +system.toL2Bus.throughput 52370833 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1836862 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1836332 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 7056 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 7056 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 922959 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 811 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 811 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 181042 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 156978 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1050040 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3684115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 38115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 140219 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4912489 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 33600320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 122621708 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 135720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 527336 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 156885084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268925359 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 127504 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5157428290 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 882000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1008000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2232669307 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2365130940 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4714355905 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4803653283 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19343965 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 21171206 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 67521559 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 74417261 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1276093 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 150466 # Transaction distribution -system.iobus.trans_dist::ReadResp 150466 # Transaction distribution -system.iobus.trans_dist::WriteReq 32862 # Transaction distribution -system.iobus.trans_dist::WriteResp 32862 # Transaction distribution -system.iobus.trans_dist::MessageReq 892 # Transaction distribution -system.iobus.trans_dist::MessageResp 892 # Transaction distribution +system.iobus.throughput 1276721 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 150736 # Transaction distribution +system.iobus.trans_dist::ReadResp 150736 # Transaction distribution +system.iobus.trans_dist::WriteReq 30161 # Transaction distribution +system.iobus.trans_dist::WriteResp 30161 # Transaction distribution +system.iobus.trans_dist::MessageReq 957 # Transaction distribution +system.iobus.trans_dist::MessageResp 957 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4556 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 500 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 580 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15082 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 310648 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 56008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 56008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1784 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1784 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 368440 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 312158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49636 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49636 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 363708 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3380 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 17 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143595 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1000 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1160 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7541 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 159467 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1782176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1782176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1945211 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6556491 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2113460 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 160435 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1576592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1576592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1740855 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6559098 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2255722 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3772000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4948000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143596000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143539000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 394000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 458000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11170000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11248000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 248070339 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 218954798 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 305066000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306061000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 32957751 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 29747501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 892000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 957000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1184263733 # number of cpu cycles simulated +system.cpu0.numCycles 1152461068 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72124506 # Number of instructions committed -system.cpu0.committedOps 146682326 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134713165 # Number of integer alu accesses +system.cpu0.committedInsts 71542662 # Number of instructions committed +system.cpu0.committedOps 145644721 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 133686522 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 981373 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14229217 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134713165 # number of integer instructions +system.cpu0.num_func_calls 963574 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14130614 # number of instructions that are conditional controls +system.cpu0.num_int_insts 133686522 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 247622256 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115606613 # number of times the integer registers were written +system.cpu0.num_int_register_reads 245609809 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114802156 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83816060 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55907358 # number of times the CC registers were written -system.cpu0.num_mem_refs 14049102 # number of memory refs -system.cpu0.num_load_insts 10253492 # Number of load instructions -system.cpu0.num_store_insts 3795610 # Number of store instructions -system.cpu0.num_idle_cycles 1123870108.492543 # Number of idle cycles -system.cpu0.num_busy_cycles 60393624.507457 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050997 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949003 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 83145706 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55494396 # number of times the CC registers were written +system.cpu0.num_mem_refs 13834339 # number of memory refs +system.cpu0.num_load_insts 10142209 # Number of load instructions +system.cpu0.num_store_insts 3692130 # Number of store instructions +system.cpu0.num_idle_cycles 1095316733.110107 # Number of idle cycles +system.cpu0.num_busy_cycles 57144334.889893 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049585 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950415 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 848510 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.789516 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129618382 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 849022 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 152.667872 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147463418500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 302.993641 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 130.368033 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 77.427843 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.591784 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.254625 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.151226 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997636 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 87771297 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39145197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2701888 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129618382 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87771297 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39145197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2701888 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129618382 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87771297 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39145197 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2701888 # number of overall hits -system.cpu0.icache.overall_hits::total 129618382 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 353389 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 157925 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 356099 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 867413 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 353389 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 157925 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 356099 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 867413 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 353389 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 157925 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 356099 # number of overall misses -system.cpu0.icache.overall_misses::total 867413 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2216316250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5093590204 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7309906454 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2216316250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5093590204 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7309906454 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2216316250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5093590204 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7309906454 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 88124686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39303122 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3057987 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130485795 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 88124686 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39303122 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3057987 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130485795 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 88124686 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39303122 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3057987 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130485795 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004010 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004018 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116449 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006648 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004010 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004018 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116449 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006648 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004010 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004018 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116449 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006648 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14033.979737 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14303.859893 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8427.250288 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8427.250288 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8427.250288 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4049 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 857108 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.816977 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128607019 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 857620 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 149.958046 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147466681500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 303.791229 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 134.865519 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 72.160229 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.593342 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.263409 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.140938 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997689 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 87032678 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38704601 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2869740 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 128607019 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87032678 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38704601 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2869740 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 128607019 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87032678 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38704601 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2869740 # number of overall hits +system.cpu0.icache.overall_hits::total 128607019 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 332599 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 151109 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 394689 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 878397 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 332599 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 151109 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 394689 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 878397 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 332599 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 151109 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 394689 # number of overall misses +system.cpu0.icache.overall_misses::total 878397 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2111983250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5690259841 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7802243091 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2111983250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5690259841 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7802243091 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2111983250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5690259841 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7802243091 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 87365277 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38855710 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3264429 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 129485416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 87365277 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38855710 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3264429 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 129485416 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 87365277 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38855710 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3264429 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 129485416 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003807 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003889 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120906 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006784 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003807 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003889 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120906 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006784 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003807 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003889 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120906 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006784 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13976.555003 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14417.072280 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8882.365367 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13976.555003 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14417.072280 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8882.365367 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13976.555003 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14417.072280 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8882.365367 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6122 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 236 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 230 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.156780 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.617391 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 18382 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 18382 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 18382 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 18382 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 18382 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 18382 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 157925 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 337717 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 495642 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 157925 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 337717 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 495642 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 157925 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 337717 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 495642 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1899637750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4221033432 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6120671182 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1899637750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4221033432 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6120671182 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1899637750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4221033432 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6120671182 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003798 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.003798 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.003798 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12348.976039 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 20763 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 20763 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 20763 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 20763 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 20763 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 20763 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 151109 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 373926 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 525035 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 151109 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 373926 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 525035 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 151109 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 373926 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 525035 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1808966750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4711215798 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6520182548 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1808966750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4711215798 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6520182548 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1808966750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4711215798 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6520182548 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003889 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114546 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004055 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003889 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114546 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004055 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003889 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114546 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004055 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11971.270738 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12599.326599 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12418.567425 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11971.270738 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12599.326599 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12418.567425 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11971.270738 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12599.326599 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12418.567425 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1632030 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997838 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19577218 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1632542 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.991862 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1634697 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999455 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19613816 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1635209 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.994684 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 205.523243 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 299.707974 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.766620 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.401413 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.585367 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013216 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5112635 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2556554 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3831407 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11500596 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3643791 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1689050 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2742153 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8074994 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8756426 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4245604 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6573560 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19575590 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8756426 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4245604 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6573560 # number of overall hits -system.cpu0.dcache.overall_hits::total 19575590 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 530196 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 228350 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 940486 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1699032 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 148061 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 60070 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 106578 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 314709 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 678257 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 288420 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1047064 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2013741 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 678257 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 288420 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1047064 # number of overall misses -system.cpu0.dcache.overall_misses::total 2013741 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3284093256 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15033857981 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 18317951237 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2239487659 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3281341546 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5520829205 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5523580915 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 18315199527 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 23838780442 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5523580915 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 18315199527 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 23838780442 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5642831 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2784904 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4771893 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13199628 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3791852 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1749120 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2848731 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8389703 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9434683 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4534024 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7620624 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21589331 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9434683 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4534024 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7620624 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21589331 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093959 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.081996 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.197089 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128718 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.039047 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034343 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.037412 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037511 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071890 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.063612 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137399 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.093275 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071890 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063612 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137399 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093275 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14381.840403 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15985.201248 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10781.404492 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37281.299467 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30788.169660 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17542.647986 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 11838.056851 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11838.056851 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 171453 # number of cycles access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 200.851253 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 304.204078 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.944124 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.392288 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.594149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013563 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5007486 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2456211 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4066814 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11530511 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3548930 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1627224 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2905330 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8081484 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8556416 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4083435 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6972144 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19611995 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8556416 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4083435 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6972144 # number of overall hits +system.cpu0.dcache.overall_hits::total 19611995 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 521438 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 227972 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 965445 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1714855 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 139893 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 58525 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 116582 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 315000 # number of WriteReq misses +system.cpu0.dcache.demand_misses::cpu0.data 661331 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 286497 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1082027 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2029855 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 661331 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 286497 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1082027 # number of overall misses +system.cpu0.dcache.overall_misses::total 2029855 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3246346508 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15541427611 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18787774119 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2199408780 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3682017546 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5881426326 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 5445755288 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 19223445157 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24669200445 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 5445755288 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 19223445157 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24669200445 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5528924 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2684183 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 5032259 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13245366 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3688823 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1685749 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3021912 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8396484 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9217747 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4369932 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 8054171 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21641850 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9217747 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4369932 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8054171 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21641850 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.094311 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.084932 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.191851 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.129468 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037923 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034718 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.038579 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037516 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071745 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065561 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.134344 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.093793 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071745 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065561 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.134344 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.093793 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14240.110663 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16097.683049 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10955.896632 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37580.671166 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31583.070680 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18671.194686 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19008.070898 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17766.141840 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12153.183575 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19008.070898 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17766.141840 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12153.183575 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 177963 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11788 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11847 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.544706 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.021778 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1542501 # number of writebacks -system.cpu0.dcache.writebacks::total 1542501 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 362466 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362466 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17153 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 17153 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 379619 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 379619 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 379619 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 379619 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 228350 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 578020 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 806370 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60070 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89425 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 149495 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 288420 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 667445 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 955865 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 288420 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 667445 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 955865 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2826173744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8314744809 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11140918553 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2108252341 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2905747700 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5014000041 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4934426085 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11220492509 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16154918594 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4934426085 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11220492509 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16154918594 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30636255000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33190282000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63826537000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 532271000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 712236000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1244507000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31168526000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33902518000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65071044000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081996 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121130 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061090 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031391 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017819 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.044275 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044275 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.499864 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14384.873895 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13816.137199 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35096.592992 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32493.684093 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33539.583538 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1544272 # number of writebacks +system.cpu0.dcache.writebacks::total 1544272 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 375629 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 375629 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17363 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17363 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 392992 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 392992 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 392992 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 392992 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 227972 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 589816 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 817788 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 58525 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99219 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 157744 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 286497 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 689035 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 975532 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 286497 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 689035 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 975532 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2789367492 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8524003053 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11313370545 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2071430220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3281431451 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5352861671 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4860797712 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11805434504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16666232216 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4860797712 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11805434504 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16666232216 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30612926500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33246502500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63859429000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 519657500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 815190500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1334848000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31132584000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34061693000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65194277000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.084932 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.117207 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061741 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034718 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032833 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018787 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.045076 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045076 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12235.570561 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14451.969857 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13834.111707 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35393.937975 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33072.611607 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33933.852768 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1416,306 +1412,306 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606010326 # number of cpu cycles simulated +system.cpu1.numCycles 2606011326 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35502902 # Number of instructions committed -system.cpu1.committedOps 69019443 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64128875 # Number of integer alu accesses +system.cpu1.committedInsts 35164948 # Number of instructions committed +system.cpu1.committedOps 68413270 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63529188 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 466888 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6511590 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64128875 # number of integer instructions +system.cpu1.num_func_calls 457891 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6471423 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63529188 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 118555351 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55341107 # number of times the integer registers were written +system.cpu1.num_int_register_reads 117257194 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54850904 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36337345 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27074895 # number of times the CC registers were written -system.cpu1.num_mem_refs 4724906 # number of memory refs -system.cpu1.num_load_insts 2973846 # Number of load instructions -system.cpu1.num_store_insts 1751060 # Number of store instructions -system.cpu1.num_idle_cycles 2477242501.972853 # Number of idle cycles -system.cpu1.num_busy_cycles 128767824.027147 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049412 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950588 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 36014934 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26882843 # number of times the CC registers were written +system.cpu1.num_mem_refs 4560424 # number of memory refs +system.cpu1.num_load_insts 2872895 # Number of load instructions +system.cpu1.num_store_insts 1687529 # Number of store instructions +system.cpu1.num_idle_cycles 2475874291.383945 # Number of idle cycles +system.cpu1.num_busy_cycles 130137034.616055 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049937 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950063 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28668505 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28668505 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 293936 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26313496 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25716329 # Number of BTB hits +system.cpu2.branchPred.lookups 29049356 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29049356 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 330189 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26516680 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25920061 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.730568 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 531231 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 59742 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154176343 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.750024 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 553809 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 66194 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157465018 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9183670 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141279801 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28668505 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26247560 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54165747 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1372429 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 60595 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24017130 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 2633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7414 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 19025 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3057990 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 134510 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1720 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 88520588 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.147296 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.411069 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10014190 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 143120520 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29049356 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26473870 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54776048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1540394 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 78659 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 25463388 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 3574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6100 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 25165 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 454 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3264432 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 152504 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2125 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 91560833 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.080398 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.405930 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 34483261 38.96% 38.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 569039 0.64% 39.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23712203 26.79% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 303942 0.34% 66.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 596203 0.67% 67.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 791828 0.89% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 321684 0.36% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 518300 0.59% 69.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27224128 30.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 36927513 40.33% 40.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 611138 0.67% 41.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23812381 26.01% 67.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 328703 0.36% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 619714 0.68% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 832275 0.91% 68.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 355282 0.39% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 540716 0.59% 69.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27533111 30.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 88520588 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185946 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.916352 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10629848 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 22917593 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 30946726 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1286674 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1067388 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 277843876 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 5 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1067388 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11607450 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13707721 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4125990 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 31086433 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5253313 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 276918591 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6816 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2458805 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2129053 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 330941436 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 602250525 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 370032440 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321416172 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9525262 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 139074 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 139963 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11350220 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6069912 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3334552 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 325084 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 284462 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275324678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 401766 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273874447 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 58026 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6719880 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10332541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 51920 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 88520588 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.093907 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.392477 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 91560833 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184481 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.908904 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 11521398 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 24357574 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 32837645 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1316376 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1196608 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 281192085 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 11 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1196608 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12539536 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14626708 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4503596 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 32964525 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5398696 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280154725 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 7234 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2491982 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2219031 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 334708153 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 610319016 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 374834819 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 324049688 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10658465 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 153621 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 154561 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11685330 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6409686 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3556417 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 350066 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 288206 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 278401976 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 420214 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 276663998 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 65469 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7519016 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11586940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 57670 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 91560833 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.021641 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.405034 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 25429283 28.73% 28.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6033030 6.82% 35.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3870306 4.37% 39.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2690716 3.04% 42.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25010151 28.25% 71.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1323131 1.49% 72.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23827077 26.92% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 285216 0.32% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 51678 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 27548029 30.09% 30.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6302445 6.88% 36.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 4040687 4.41% 41.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2809709 3.07% 44.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25166051 27.49% 71.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1389542 1.52% 73.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23947180 26.15% 99.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 301462 0.33% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 55728 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 88520588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 91560833 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 120453 33.21% 33.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 124 0.03% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 190037 52.39% 85.63% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 52134 14.37% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 136321 35.17% 35.17% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 124 0.03% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 194124 50.09% 85.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 56993 14.71% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 69880 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264196051 96.47% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 53857 0.02% 96.51% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 45427 0.02% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6378380 2.33% 98.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3130852 1.14% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 81905 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 266468718 96.31% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56660 0.02% 96.37% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48242 0.02% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6674536 2.41% 98.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3333937 1.21% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273874447 # Type of FU issued -system.cpu2.iq.rate 1.776371 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 362748 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001325 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 636728050 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 282449613 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272560977 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 75 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 276663998 # Type of FU issued +system.cpu2.iq.rate 1.756987 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387562 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 645385259 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 286345237 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 275267423 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 106 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274167280 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 35 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 638144 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 276969613 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 42 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 657734 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 933920 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 7005 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3826 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 481474 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1052819 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4672 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 529632 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656274 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10618 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656268 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10631 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9024497 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 812904 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275726444 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 67814 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6069912 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3334552 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 224273 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 631637 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3885 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3826 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 167894 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164610 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 332504 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273407129 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6276348 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 467317 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1196608 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9811775 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 820688 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 278822190 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 75669 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6409704 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3556417 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 239796 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 634227 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4101 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4672 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 184871 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 190702 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 375573 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 276137017 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6556879 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 526981 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9343774 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27815177 # Number of branches executed -system.cpu2.iew.exec_stores 3067426 # Number of stores executed -system.cpu2.iew.exec_rate 1.773340 # Inst execution rate -system.cpu2.iew.wb_sent 273265355 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272560999 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212629872 # num instructions producing a value -system.cpu2.iew.wb_consumers 347702126 # num instructions consuming a value +system.cpu2.iew.exec_refs 9821909 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28090459 # Number of branches executed +system.cpu2.iew.exec_stores 3265030 # Number of stores executed +system.cpu2.iew.exec_rate 1.753640 # Inst execution rate +system.cpu2.iew.wb_sent 275979435 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 275267445 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 214496489 # num instructions producing a value +system.cpu2.iew.wb_consumers 350700107 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.767852 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611529 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.748118 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611624 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7002811 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 349846 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 295934 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 87453200 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.072767 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.870996 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7834345 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 362544 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 332977 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 90364225 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 2.998816 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.871519 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30168588 34.50% 34.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4310788 4.93% 39.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1198483 1.37% 40.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24616834 28.15% 68.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 847666 0.97% 69.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 576601 0.66% 70.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 339942 0.39% 70.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23302626 26.65% 97.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2091672 2.39% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 32381210 35.83% 35.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4545159 5.03% 40.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1281676 1.42% 42.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24783522 27.43% 69.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 890698 0.99% 70.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 597656 0.66% 71.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 358639 0.40% 71.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23381642 25.87% 97.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2144023 2.37% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 87453200 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136077774 # Number of instructions committed -system.cpu2.commit.committedOps 268723335 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 90364225 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137308621 # Number of instructions committed +system.cpu2.commit.committedOps 270985661 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7989069 # Number of memory references committed -system.cpu2.commit.loads 5135991 # Number of loads committed -system.cpu2.commit.membars 163538 # Number of memory barriers committed -system.cpu2.commit.branches 27499066 # Number of branches committed +system.cpu2.commit.refs 8383670 # Number of memory references committed +system.cpu2.commit.loads 5356885 # Number of loads committed +system.cpu2.commit.membars 165489 # Number of memory barriers committed +system.cpu2.commit.branches 27738642 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245318960 # Number of committed integer instructions. -system.cpu2.commit.function_calls 428759 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2091672 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 247503684 # Number of committed integer instructions. +system.cpu2.commit.function_calls 442390 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2144023 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 361063162 # The number of ROB reads -system.cpu2.rob.rob_writes 552523197 # The number of ROB writes -system.cpu2.timesIdled 466136 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65655755 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4909695924 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136077774 # Number of Instructions Simulated -system.cpu2.committedOps 268723335 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136077774 # Number of Instructions Simulated -system.cpu2.cpi 1.133002 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.133002 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882611 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882611 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 363659019 # number of integer regfile reads -system.cpu2.int_regfile_writes 218348978 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads +system.cpu2.rob.rob_reads 367011505 # The number of ROB reads +system.cpu2.rob.rob_writes 558841004 # The number of ROB writes +system.cpu2.timesIdled 481956 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65904185 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4905068069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137308621 # Number of Instructions Simulated +system.cpu2.committedOps 270985661 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 137308621 # Number of Instructions Simulated +system.cpu2.cpi 1.146796 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.146796 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.871994 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.871994 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 367544012 # number of integer regfile reads +system.cpu2.int_regfile_writes 220503659 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72990 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138971726 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107072573 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88484504 # number of misc regfile reads -system.cpu2.misc_regfile_writes 124462 # number of misc regfile writes +system.cpu2.cc_regfile_reads 140406201 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108013944 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89640596 # number of misc regfile reads +system.cpu2.misc_regfile_writes 136839 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |