diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 3082 |
1 files changed, 1549 insertions, 1533 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 9fd6d97ff..e53b3f285 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,150 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133872 # Number of seconds simulated -sim_ticks 5133872107500 # Number of ticks simulated -final_tick 5133872107500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137752 # Number of seconds simulated +sim_ticks 5137751757500 # Number of ticks simulated +final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 332026 # Simulator instruction rate (inst/s) -host_op_rate 659988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6979227984 # Simulator tick rate (ticks/s) -host_mem_usage 973372 # Number of bytes of host memory used -host_seconds 735.59 # Real time elapsed on the host -sim_insts 244235751 # Number of instructions simulated -sim_ops 485482573 # Number of ops (including micro ops) simulated +host_inst_rate 205879 # Simulator instruction rate (inst/s) +host_op_rate 409313 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4343855741 # Simulator tick rate (ticks/s) +host_mem_usage 976756 # Number of bytes of host memory used +host_seconds 1182.76 # Real time elapsed on the host +sim_insts 243506025 # Number of instructions simulated +sim_ops 484120527 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5572928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 164928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1639680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 412864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3220800 # Number of bytes read from this memory -system.physmem.bytes_read::total 11438848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 164928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 412864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 974528 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6205312 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 475328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5564736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 130048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2113344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 362880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2752000 # Number of bytes read from this memory +system.physmem.bytes_read::total 11429696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 475328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 130048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 362880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6180416 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9195392 # Number of bytes written to this memory +system.physmem.bytes_written::total 9170496 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 87077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 25620 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 50325 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178732 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96958 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7427 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 86949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 43000 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178589 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96569 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143678 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 77278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1085521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 319385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 80420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 627363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2228113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 77278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 80420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 189823 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1208700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 582422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1791122 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1208700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 587945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 77278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1085521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 319385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 80420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 627363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4019235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 85451 # Number of read requests accepted -system.physmem.writeReqs 85019 # Number of write requests accepted -system.physmem.readBursts 85451 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 85019 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5457024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11840 # Total number of bytes read from write queue -system.physmem.bytesWritten 5440128 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5468864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5441216 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 143289 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 92517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1083107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 25312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 411336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 70630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 535643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2224649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 92517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 25312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 70630 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1202942 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 581982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1784924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1202942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 587501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 92517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1083107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 25312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 411336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 70630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 535643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4009573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 84209 # Number of read requests accepted +system.physmem.writeReqs 74716 # Number of write requests accepted +system.physmem.readBursts 84209 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 74716 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5376960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12416 # Total number of bytes read from write queue +system.physmem.bytesWritten 4781824 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5389376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4781824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 868 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5096 # Per bank write bursts -system.physmem.perBankRdBursts::1 5035 # Per bank write bursts -system.physmem.perBankRdBursts::2 5503 # Per bank write bursts -system.physmem.perBankRdBursts::3 5713 # Per bank write bursts -system.physmem.perBankRdBursts::4 5011 # Per bank write bursts -system.physmem.perBankRdBursts::5 4756 # Per bank write bursts -system.physmem.perBankRdBursts::6 4921 # Per bank write bursts -system.physmem.perBankRdBursts::7 5413 # Per bank write bursts -system.physmem.perBankRdBursts::8 5128 # Per bank write bursts -system.physmem.perBankRdBursts::9 4999 # Per bank write bursts -system.physmem.perBankRdBursts::10 4701 # Per bank write bursts -system.physmem.perBankRdBursts::11 5348 # Per bank write bursts -system.physmem.perBankRdBursts::12 5396 # Per bank write bursts -system.physmem.perBankRdBursts::13 6167 # Per bank write bursts -system.physmem.perBankRdBursts::14 6376 # Per bank write bursts -system.physmem.perBankRdBursts::15 5703 # Per bank write bursts -system.physmem.perBankWrBursts::0 5743 # Per bank write bursts -system.physmem.perBankWrBursts::1 5870 # Per bank write bursts -system.physmem.perBankWrBursts::2 5006 # Per bank write bursts -system.physmem.perBankWrBursts::3 5323 # Per bank write bursts -system.physmem.perBankWrBursts::4 4689 # Per bank write bursts -system.physmem.perBankWrBursts::5 4481 # Per bank write bursts -system.physmem.perBankWrBursts::6 5327 # Per bank write bursts -system.physmem.perBankWrBursts::7 5300 # Per bank write bursts -system.physmem.perBankWrBursts::8 5281 # Per bank write bursts -system.physmem.perBankWrBursts::9 5131 # Per bank write bursts -system.physmem.perBankWrBursts::10 5421 # Per bank write bursts -system.physmem.perBankWrBursts::11 5658 # Per bank write bursts -system.physmem.perBankWrBursts::12 5171 # Per bank write bursts -system.physmem.perBankWrBursts::13 5597 # Per bank write bursts -system.physmem.perBankWrBursts::14 5966 # Per bank write bursts -system.physmem.perBankWrBursts::15 5038 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 805 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5309 # Per bank write bursts +system.physmem.perBankRdBursts::1 4164 # Per bank write bursts +system.physmem.perBankRdBursts::2 4421 # Per bank write bursts +system.physmem.perBankRdBursts::3 5747 # Per bank write bursts +system.physmem.perBankRdBursts::4 5625 # Per bank write bursts +system.physmem.perBankRdBursts::5 4848 # Per bank write bursts +system.physmem.perBankRdBursts::6 4889 # Per bank write bursts +system.physmem.perBankRdBursts::7 4803 # Per bank write bursts +system.physmem.perBankRdBursts::8 5153 # Per bank write bursts +system.physmem.perBankRdBursts::9 5288 # Per bank write bursts +system.physmem.perBankRdBursts::10 4847 # Per bank write bursts +system.physmem.perBankRdBursts::11 5280 # Per bank write bursts +system.physmem.perBankRdBursts::12 5573 # Per bank write bursts +system.physmem.perBankRdBursts::13 6540 # Per bank write bursts +system.physmem.perBankRdBursts::14 6055 # Per bank write bursts +system.physmem.perBankRdBursts::15 5473 # Per bank write bursts +system.physmem.perBankWrBursts::0 4689 # Per bank write bursts +system.physmem.perBankWrBursts::1 3818 # Per bank write bursts +system.physmem.perBankWrBursts::2 3922 # Per bank write bursts +system.physmem.perBankWrBursts::3 4862 # Per bank write bursts +system.physmem.perBankWrBursts::4 4936 # Per bank write bursts +system.physmem.perBankWrBursts::5 4229 # Per bank write bursts +system.physmem.perBankWrBursts::6 4848 # Per bank write bursts +system.physmem.perBankWrBursts::7 4482 # Per bank write bursts +system.physmem.perBankWrBursts::8 4577 # Per bank write bursts +system.physmem.perBankWrBursts::9 4853 # Per bank write bursts +system.physmem.perBankWrBursts::10 4451 # Per bank write bursts +system.physmem.perBankWrBursts::11 4689 # Per bank write bursts +system.physmem.perBankWrBursts::12 4903 # Per bank write bursts +system.physmem.perBankWrBursts::13 5464 # Per bank write bursts +system.physmem.perBankWrBursts::14 5149 # Per bank write bursts +system.physmem.perBankWrBursts::15 4844 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5132871981000 # Total gap between requests +system.physmem.totGap 5136577016500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 85451 # Read request sizes (log2) +system.physmem.readPktSize::6 84209 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 85019 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 78990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 74716 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see @@ -164,487 +168,497 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 115 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 272.686252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.690614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.316153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16345 40.90% 40.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9834 24.61% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4112 10.29% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2230 5.58% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1552 3.88% 85.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1069 2.68% 87.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 711 1.78% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 597 1.49% 91.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3512 8.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39962 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4105 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.770767 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 117.592245 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 4095 99.76% 99.76% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 7 0.17% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4105 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.706943 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.214534 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.616872 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 63 1.53% 1.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.17% 1.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 4 0.10% 1.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3359 81.83% 83.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 49 1.19% 84.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.63% 85.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 173 4.21% 89.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 182 4.43% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 7 0.17% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 12 0.29% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.19% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.24% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.05% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 157 3.82% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.24% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 7 0.17% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.05% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.12% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.19% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4105 # Writes before turning the bus around for reads -system.physmem.totQLat 1041221500 # Total ticks spent queuing -system.physmem.totMemAccLat 2639959000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 426330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12211.45 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 37237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.814244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.615678 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.614315 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15278 41.03% 41.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9118 24.49% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3769 10.12% 75.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2135 5.73% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1492 4.01% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 936 2.51% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 657 1.76% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 562 1.51% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3290 8.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37237 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3726 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.548309 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 194.901220 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3723 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-6143 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3726 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3726 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.052603 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.849959 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.299765 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 61 1.64% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.24% 1.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.03% 1.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.11% 2.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3105 83.33% 85.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 37 0.99% 86.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.64% 86.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 154 4.13% 91.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 145 3.89% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 6 0.16% 95.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 11 0.30% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.05% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.38% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.11% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.03% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 119 3.19% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.13% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.03% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.03% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.16% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.11% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.24% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3726 # Writes before turning the bus around for reads +system.physmem.totQLat 920887750 # Total ticks spent queuing +system.physmem.totMemAccLat 2496169000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 420075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10960.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30961.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.06 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29710.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.94 # Average write queue length when enqueuing -system.physmem.readRowHits 67077 # Number of row buffer hits during reads -system.physmem.writeRowHits 63228 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes -system.physmem.avgGap 30110118.97 # Average gap between requests -system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4938526642750 # Time in different power states -system.physmem.memoryStateTime::REF 171431260000 # Time in different power states +system.physmem.avgWrQLen 12.74 # Average write queue length when enqueuing +system.physmem.readRowHits 66918 # Number of row buffer hits during reads +system.physmem.writeRowHits 54576 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes +system.physmem.avgGap 32320761.47 # Average gap between requests +system.physmem.pageHitRate 76.54 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4942660463000 # Time in different power states +system.physmem.memoryStateTime::REF 171560740000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23914099250 # Time in different power states +system.physmem.memoryStateTime::ACT 23528333250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 145575360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 156537360 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 79431000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 85412250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 323294400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 341772600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 270468720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 280344240 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 335319544560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 335319544560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 122941148535 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 123404461065 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 2972480080500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2972073666000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3431559543075 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3431661738075 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.415487 # Core power per rank (mW) -system.physmem.averagePower::1 668.435393 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 5056260 # Transaction distribution -system.membus.trans_dist::ReadResp 5056258 # Transaction distribution -system.membus.trans_dist::WriteReq 13754 # Transaction distribution -system.membus.trans_dist::WriteResp 13754 # Transaction distribution -system.membus.trans_dist::Writeback 96958 # Transaction distribution +system.physmem.actEnergy::0 135618840 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 145892880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 73998375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 79604250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 310486800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 344830200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 231893280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 252266400 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 335572807440 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 335572807440 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 122729524065 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 123386936985 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 2974992236250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 2974415558250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 3434046565050 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 3434197896405 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.395092 # Core power per rank (mW) +system.physmem.averagePower::1 668.424547 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 5119571 # Transaction distribution +system.membus.trans_dist::ReadResp 5119569 # Transaction distribution +system.membus.trans_dist::WriteReq 13900 # Transaction distribution +system.membus.trans_dist::WriteResp 13900 # Transaction distribution +system.membus.trans_dist::Writeback 96569 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1654 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1654 # Transaction distribution -system.membus.trans_dist::ReadExReq 129924 # Transaction distribution -system.membus.trans_dist::ReadExResp 129924 # Transaction distribution -system.membus.trans_dist::MessageReq 1664 # Transaction distribution -system.membus.trans_dist::MessageResp 1664 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1658 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1658 # Transaction distribution +system.membus.trans_dist::ReadExReq 130179 # Transaction distribution +system.membus.trans_dist::ReadExResp 130179 # Transaction distribution +system.membus.trans_dist::MessageReq 1687 # Transaction distribution +system.membus.trans_dist::MessageResp 1687 # Transaction distribution system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7028524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3012958 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456844 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456177 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10498330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10596613 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3520458 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6025913 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17615808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27162179 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3029056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30197891 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 297 # Total snoops (count) -system.membus.snoop_fanout::samples 324529 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::total 10625377 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10723708 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079977 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17581760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27232497 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3029312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30268557 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 291 # Total snoops (count) +system.membus.snoop_fanout::samples 323999 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 324529 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 323999 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 324529 # Request fanout histogram -system.membus.reqLayer0.occupancy 165183000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 323999 # Request fanout histogram +system.membus.reqLayer0.occupancy 162958500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315920500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 314938500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1960000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2254000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 897247500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 804193000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 980000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1127000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1679098885 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1664243698 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 35042997 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 28678745 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 105529 # number of replacements -system.l2c.tags.tagsinuse 64826.632454 # Cycle average of tags in use -system.l2c.tags.total_refs 3692969 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169653 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.767779 # Average number of references to valid blocks. +system.l2c.tags.replacements 104648 # number of replacements +system.l2c.tags.tagsinuse 64825.327064 # Cycle average of tags in use +system.l2c.tags.total_refs 3691316 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168821 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.865266 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50921.041202 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134275 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1022.158767 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3887.538850 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 285.540185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1563.161522 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 13.370475 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1774.545144 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5359.142034 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.776993 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51329.060133 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131449 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1735.761730 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4946.132925 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 379.214744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1982.386911 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.162749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 878.696468 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3562.776774 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.783219 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.015597 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.059319 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004357 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023852 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000204 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.027077 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.081774 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989176 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 541 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7391 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52860 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.978455 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33891981 # Number of tag accesses -system.l2c.tags.data_accesses 33891981 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 19672 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10574 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 322011 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 496358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 11305 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6290 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 162787 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 241655 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 55032 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13181 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 370296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 572247 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2281408 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.026486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.005786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.030249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.013408 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.054364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989156 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3770 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7642 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52446 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979202 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33857298 # Number of tag accesses +system.l2c.tags.data_accesses 33857298 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 21885 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11413 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 321088 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 497388 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12632 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6595 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 160077 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 224317 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 53710 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 12539 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 370609 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 592462 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2284715 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1548978 # number of Writeback hits -system.l2c.Writeback_hits::total 1548978 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 124 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 90 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 261 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 66428 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 37696 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 62332 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166456 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 19672 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10576 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 322011 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 562786 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 11305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6290 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 162787 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 279351 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 55032 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13181 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 370296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 634579 # number of demand (read+write) hits -system.l2c.demand_hits::total 2447866 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19672 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10576 # number of overall hits -system.l2c.overall_hits::cpu0.inst 322011 # number of overall hits -system.l2c.overall_hits::cpu0.data 562786 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 11305 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6290 # number of overall hits -system.l2c.overall_hits::cpu1.inst 162787 # number of overall hits -system.l2c.overall_hits::cpu1.data 279351 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 55032 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13181 # number of overall hits -system.l2c.overall_hits::cpu2.inst 370296 # number of overall hits -system.l2c.overall_hits::cpu2.data 634579 # number of overall hits -system.l2c.overall_hits::total 2447866 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6199 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 12693 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2577 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4439 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 35 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 6453 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 15968 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48369 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 700 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 296 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 406 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1402 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 74470 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21268 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 34438 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130176 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6199 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 87163 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2577 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 25707 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 35 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28535023500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30878906000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59413929500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020984 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017388 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.009876 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836120 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.811839 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.381010 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.447705 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.342576 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.208964 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.061719 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -776,54 +796,54 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47571 # number of replacements -system.iocache.tags.tagsinuse 0.081570 # Cycle average of tags in use +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.092434 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000192639009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081570 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005098 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005098 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092434 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005777 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005777 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428634 # Number of tag accesses -system.iocache.tags.data_accesses 428634 # Number of data accesses +system.iocache.tags.tag_accesses 428616 # Number of tag accesses +system.iocache.tags.data_accesses 428616 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses -system.iocache.ReadReq_misses::total 906 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 906 # number of demand (read+write) misses -system.iocache.demand_misses::total 906 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 906 # number of overall misses -system.iocache.overall_misses::total 906 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132202779 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 132202779 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 132202779 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 132202779 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 132202779 # number of overall miss cycles -system.iocache.overall_miss_latency::total 132202779 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses +system.iocache.demand_misses::total 904 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses +system.iocache.overall_misses::total 904 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131931527 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 131931527 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 131931527 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 131931527 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 131931527 # number of overall miss cycles +system.iocache.overall_miss_latency::total 131931527 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 906 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 906 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 906 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 906 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145919.182119 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145919.182119 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145919.182119 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145941.954646 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145941.954646 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145941.954646 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked @@ -832,38 +852,38 @@ system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 740 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 740 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28368 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 28368 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 740 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 740 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 740 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 740 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93698779 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1718205368 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1718205368 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 93698779 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 93698779 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.816777 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.607192 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.607192 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.816777 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.816777 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 126619.971622 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60568.435138 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60568.435138 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 22056 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 22056 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 734 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93740027 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1329860248 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1329860248 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 93740027 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.472089 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.472089 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60294.715633 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60294.715633 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -877,567 +897,563 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7367165 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7366643 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13756 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13756 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1548978 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 28368 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1663 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1663 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296632 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296632 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7431790 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7431262 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1547592 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22056 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291447 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291447 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740682 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14873990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 71302 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 198555 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16884529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55700736 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213654403 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 264160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 728920 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270348219 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 69633 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4254339 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011195 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105211 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14997138 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72735 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 201275 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17005004 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55482624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213567857 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 271280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 749120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270070881 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 66934 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4248687 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011209 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105278 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4206713 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47626 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4201063 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4254339 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5229007845 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4248687 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5247340592 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 990000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2442789502 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2425844552 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4872933864 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4872344858 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24776404 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24091410 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 82986153 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 80681637 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 3504325 # Transaction distribution -system.iobus.trans_dist::ReadResp 3504325 # Transaction distribution -system.iobus.trans_dist::WriteReq 57563 # Transaction distribution -system.iobus.trans_dist::WriteResp 39211 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 18352 # Transaction distribution -system.iobus.trans_dist::MessageReq 1664 # Transaction distribution -system.iobus.trans_dist::MessageResp 1664 # Transaction distribution +system.iobus.trans_dist::ReadReq 3554542 # Transaction distribution +system.iobus.trans_dist::ReadResp 3554542 # Transaction distribution +system.iobus.trans_dist::WriteReq 57685 # Transaction distribution +system.iobus.trans_dist::WriteResp 33021 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 24664 # Transaction distribution +system.iobus.trans_dist::MessageReq 1687 # Transaction distribution +system.iobus.trans_dist::MessageResp 1687 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 6984892 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27782 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7028524 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7127104 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7129206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7227828 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3492446 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13891 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3520458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6554906 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2324808 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3570760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6605284 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2693792 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4502000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4846000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143632000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 361000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 333000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11636000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10264000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 256433144 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 199614020 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 306163000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 303080000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33668003 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 27344255 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 980000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1127000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1069607129 # number of cpu cycles simulated +system.cpu0.numCycles 818767223 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70538619 # Number of instructions committed -system.cpu0.committedOps 143755687 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 131850662 # Number of integer alu accesses +system.cpu0.committedInsts 72040073 # Number of instructions committed +system.cpu0.committedOps 146798683 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134677148 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 928819 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13976393 # number of instructions that are conditional controls -system.cpu0.num_int_insts 131850662 # number of integer instructions +system.cpu0.num_func_calls 957492 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14259376 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134677148 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 241989475 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113259644 # number of times the integer registers were written +system.cpu0.num_int_register_reads 247199145 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115729599 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82136389 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 54810829 # number of times the CC registers were written -system.cpu0.num_mem_refs 13501731 # number of memory refs -system.cpu0.num_load_insts 9912408 # Number of load instructions -system.cpu0.num_store_insts 3589323 # Number of store instructions -system.cpu0.num_idle_cycles 1016224343.330366 # Number of idle cycles -system.cpu0.num_busy_cycles 53382785.669634 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049909 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950091 # Percentage of idle cycles -system.cpu0.Branches 15238819 # Number of branches fetched -system.cpu0.op_class::No_OpClass 94852 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 130054750 90.47% 90.53% # Class of executed instruction -system.cpu0.op_class::IntMult 56051 0.04% 90.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 48845 0.03% 90.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.61% # Class of executed instruction -system.cpu0.op_class::MemRead 9912408 6.90% 97.50% # Class of executed instruction -system.cpu0.op_class::MemWrite 3589323 2.50% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83822967 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55940767 # number of times the CC registers were written +system.cpu0.num_mem_refs 13836630 # number of memory refs +system.cpu0.num_load_insts 10218166 # Number of load instructions +system.cpu0.num_store_insts 3618464 # Number of store instructions +system.cpu0.num_idle_cycles 776544159.837226 # Number of idle cycles +system.cpu0.num_busy_cycles 42223063.162775 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051569 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948431 # Percentage of idle cycles +system.cpu0.Branches 15573109 # Number of branches fetched +system.cpu0.op_class::No_OpClass 95028 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132757091 90.43% 90.50% # Class of executed instruction +system.cpu0.op_class::IntMult 59427 0.04% 90.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 51115 0.03% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::MemRead 10218166 6.96% 97.54% # Class of executed instruction +system.cpu0.op_class::MemWrite 3618464 2.46% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143756229 # Class of executed instruction +system.cpu0.op_class::total 146799291 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 869835 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.810026 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 128546541 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 870347 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 147.695736 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147420125000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.953257 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.567270 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.289498 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.246002 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.268686 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.482987 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997676 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 866413 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.840210 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 130156159 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 866925 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 150.135432 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149014386250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 138.994027 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 266.522548 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 105.323634 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.271473 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.520552 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.205710 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997735 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 130310898 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 130310898 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 85798477 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39676062 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3072002 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 128546541 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 85798477 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39676062 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3072002 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 128546541 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 85798477 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39676062 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3072002 # number of overall hits -system.cpu0.icache.overall_hits::total 128546541 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 328211 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 165364 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 400424 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 893999 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 328211 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 165364 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 400424 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 893999 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 328211 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 165364 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 400424 # number of overall misses -system.cpu0.icache.overall_misses::total 893999 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2321256000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5686834829 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8008090829 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2321256000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5686834829 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8008090829 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2321256000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5686834829 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8008090829 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 86126688 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39841426 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3472426 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 129440540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 86126688 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39841426 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3472426 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 129440540 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 86126688 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39841426 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3472426 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 129440540 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003811 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004151 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115315 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006907 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003811 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004151 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115315 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006907 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003811 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004151 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115315 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006907 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14037.251155 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14202.032918 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8957.606025 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14037.251155 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14202.032918 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8957.606025 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14037.251155 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14202.032918 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8957.606025 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4468 # 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number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3932721854 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9086943348 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13019665202 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4927988354 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11857516609 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16785504963 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30674705000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33246369000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63921074000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534053500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 811227000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345280500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31208758500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34057596000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65266354500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.061209 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084010 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045295 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033572 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031937 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018640 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.862400 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.842514 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.545962 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050505 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.063972 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034738 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065711 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.084391 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.045740 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11810.286560 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14263.787110 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13540.083936 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32259.387031 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33496.144849 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33027.559834 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13258.729101 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15436.668492 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.396908 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17074.737561 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17958.421554 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17682.002602 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16136.757886 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17298.147148 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16940.202896 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1547592 # number of writebacks +system.cpu0.dcache.writebacks::total 1547592 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 59 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 355847 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 355906 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1633 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 30941 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 32574 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1692 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 386788 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 388480 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1692 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 386788 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 388480 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 164832 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 416190 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 581022 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 63496 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95574 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 159070 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64293 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186824 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 251117 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 228328 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 511764 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 740092 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 292621 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 698588 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 991209 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1964999750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5660700319 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7625700069 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2364352650 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3101755528 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5466108178 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 883443250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2757990753 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3641434003 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4329352400 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8762455847 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13091808247 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5212795650 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11520446600 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16733242250 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30452050000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32985877000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63437927000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 577982500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 687759500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1265742000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31030032500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33673636500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64703669000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059119 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.089108 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045278 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033849 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032789 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018926 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.858602 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.851553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.538331 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048955 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067467 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034849 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061749 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.089507 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045670 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.227371 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13601.240585 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13124.632233 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37236.245590 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32453.967899 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34362.910530 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13740.893254 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14762.507777 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14500.945786 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18961.110333 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17122.063777 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17689.433539 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17814.154316 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16491.045652 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16881.648825 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1448,376 +1464,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604021576 # number of cpu cycles simulated +system.cpu1.numCycles 2606022983 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35901808 # Number of instructions committed -system.cpu1.committedOps 69778761 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64893692 # Number of integer alu accesses +system.cpu1.committedInsts 35939339 # Number of instructions committed +system.cpu1.committedOps 69774923 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64844483 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 487874 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6598396 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64893692 # number of integer instructions +system.cpu1.num_func_calls 499287 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6580388 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64844483 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119938204 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55974127 # number of times the integer registers were written +system.cpu1.num_int_register_reads 120226227 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55826198 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36929560 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27415142 # number of times the CC registers were written -system.cpu1.num_mem_refs 4838216 # number of memory refs -system.cpu1.num_load_insts 3070311 # Number of load instructions -system.cpu1.num_store_insts 1767905 # Number of store instructions -system.cpu1.num_idle_cycles 2474835372.874957 # Number of idle cycles -system.cpu1.num_busy_cycles 129186203.125043 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049610 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950390 # Percentage of idle cycles -system.cpu1.Branches 7267731 # Number of branches fetched -system.cpu1.op_class::No_OpClass 34873 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64849393 92.94% 92.99% # Class of executed instruction -system.cpu1.op_class::IntMult 30804 0.04% 93.03% # Class of executed instruction -system.cpu1.op_class::IntDiv 25762 0.04% 93.07% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.07% # Class of executed instruction -system.cpu1.op_class::MemRead 3070311 4.40% 97.47% # Class of executed instruction -system.cpu1.op_class::MemWrite 1767905 2.53% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36586824 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27309791 # number of times the CC registers were written +system.cpu1.num_mem_refs 4927873 # number of memory refs +system.cpu1.num_load_insts 3050339 # Number of load instructions +system.cpu1.num_store_insts 1877534 # Number of store instructions +system.cpu1.num_idle_cycles 2477290986.248718 # Number of idle cycles +system.cpu1.num_busy_cycles 128731996.751282 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049398 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950602 # Percentage of idle cycles +system.cpu1.Branches 7259898 # Number of branches fetched +system.cpu1.op_class::No_OpClass 35461 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64754697 92.80% 92.86% # Class of executed instruction +system.cpu1.op_class::IntMult 31756 0.05% 92.90% # Class of executed instruction +system.cpu1.op_class::IntDiv 25505 0.04% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::MemRead 3050339 4.37% 97.31% # Class of executed instruction +system.cpu1.op_class::MemWrite 1877534 2.69% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69779048 # Class of executed instruction +system.cpu1.op_class::total 69775292 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29537500 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29537500 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 323734 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26929505 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26224950 # Number of BTB hits +system.cpu2.branchPred.lookups 29000272 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29000272 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 311632 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26370508 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25723888 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.383706 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 595117 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63666 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155672620 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.547943 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 573459 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63282 # Number of incorrect RAS predictions. +system.cpu2.numCycles 153009050 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10607285 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 145694636 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29537500 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26820067 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 143529975 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 676631 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 97153 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 5039 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 8049 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 56841 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 4424 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3472431 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 167012 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3661 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154646852 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.855079 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.032629 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10521285 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142969715 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29000272 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26297347 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 141031314 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 650011 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 92984 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 4408 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 9006 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 47091 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 2529 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 579 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3383247 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 163781 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3234 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 152033550 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.852472 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.031588 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98720699 63.84% 63.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 840447 0.54% 64.38% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23990695 15.51% 79.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 599923 0.39% 80.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 812589 0.53% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 861055 0.56% 81.36% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 574182 0.37% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 718315 0.46% 82.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27528947 17.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 97124192 63.88% 63.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 819598 0.54% 64.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23594190 15.52% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 577537 0.38% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 790978 0.52% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 823076 0.54% 81.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 560198 0.37% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 693420 0.46% 82.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27050361 17.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154646852 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189741 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.935904 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10277789 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95381782 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 22559618 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5904125 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 338966 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 283871353 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 338966 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12885148 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76664692 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4829048 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 25619792 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14124701 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 282624473 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 211024 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 6375709 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 73879 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 5159969 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 337473501 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 616062521 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 378507156 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 50 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 325128635 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12344864 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 162095 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 163797 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 28599466 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6606628 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3716011 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 425441 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 346966 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 280674873 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 430305 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278581977 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 102725 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8814114 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13599788 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 65362 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154646852 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.801407 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.400759 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 152033550 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189533 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.934387 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9712542 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 92934302 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 23280371 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5017317 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 325657 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278875678 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 325657 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11857648 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 75889768 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4419845 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 25919685 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12857653 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277706863 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 221466 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5888159 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 42783 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4808995 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331833488 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605194394 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371618079 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 36 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320107208 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11726280 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 151218 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 152719 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 24489304 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6338862 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3553328 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 367719 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 319565 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275826769 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 413139 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273878584 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 98557 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8364175 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12972199 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 61453 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 152033550 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.801435 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.398557 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 91425932 59.12% 59.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5392264 3.49% 62.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3912324 2.53% 65.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4126244 2.67% 67.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 21795400 14.09% 81.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 3071037 1.99% 83.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24235245 15.67% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 469170 0.30% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 219236 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 89826062 59.08% 59.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5325607 3.50% 62.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3883778 2.55% 65.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3618974 2.38% 67.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22318323 14.68% 82.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2568868 1.69% 83.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23837030 15.68% 99.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 450577 0.30% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 204331 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154646852 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 152033550 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2310389 89.01% 89.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 246 0.01% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 223101 8.59% 97.61% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 62004 2.39% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1765790 86.71% 86.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 6 0.00% 86.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 95 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 213483 10.48% 97.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 57008 2.80% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 76436 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 268041478 96.22% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 58746 0.02% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 49744 0.02% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6933130 2.49% 98.77% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3422443 1.23% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 75484 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263736524 96.30% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54819 0.02% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 47031 0.02% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6686249 2.44% 98.80% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3278477 1.20% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278581977 # Type of FU issued -system.cpu2.iq.rate 1.789537 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2595740 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.009318 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 714509188 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 289923619 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 276984093 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 82 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 281101244 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 37 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 733638 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 273878584 # Type of FU issued +system.cpu2.iq.rate 1.789950 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2036382 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007435 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 701925596 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284608270 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272313229 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 61 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 275839453 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 29 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 685704 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1227908 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6601 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5025 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 667461 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1161006 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6104 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4803 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 634153 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 754863 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 24022 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 755552 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 21313 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 338966 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 71689555 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1628683 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 281105178 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 39439 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6606628 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3716011 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 250069 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 194031 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1131651 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5025 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 186633 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 188127 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 374760 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 278001109 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6795315 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 530943 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 325657 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70767994 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1741893 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 276239908 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 40444 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6338884 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3553328 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 236248 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 194416 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1250638 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4803 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 177191 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 184398 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 361589 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273320009 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6554812 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 510377 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10133053 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28226522 # Number of branches executed -system.cpu2.iew.exec_stores 3337738 # Number of stores executed -system.cpu2.iew.exec_rate 1.785806 # Inst execution rate -system.cpu2.iew.wb_sent 277806882 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 276984111 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 215977189 # num instructions producing a value -system.cpu2.iew.wb_consumers 354208085 # num instructions consuming a value +system.cpu2.iew.exec_refs 9748811 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27755327 # Number of branches executed +system.cpu2.iew.exec_stores 3193999 # Number of stores executed +system.cpu2.iew.exec_rate 1.786300 # Inst execution rate +system.cpu2.iew.wb_sent 273134840 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272313245 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212432379 # num instructions producing a value +system.cpu2.iew.wb_consumers 348339663 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.779273 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609747 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.779720 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609843 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9156375 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 364943 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 326343 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 153280377 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.774187 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.653000 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8691419 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 351686 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 314047 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 150733678 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.774964 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.652543 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 95267512 62.15% 62.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4211429 2.75% 64.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1288351 0.84% 65.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24928908 16.26% 82.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 992667 0.65% 82.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 656859 0.43% 83.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 436979 0.29% 83.37% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23484943 15.32% 98.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2012729 1.31% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 93656646 62.13% 62.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4148238 2.75% 64.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1235888 0.82% 65.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24514613 16.26% 81.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1002757 0.67% 82.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 665638 0.44% 83.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 467092 0.31% 83.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23101150 15.33% 98.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1941656 1.29% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 153280377 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137795324 # Number of instructions committed -system.cpu2.commit.committedOps 271948125 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 150733678 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135526613 # Number of instructions committed +system.cpu2.commit.committedOps 267546921 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8427269 # Number of memory references committed -system.cpu2.commit.loads 5378719 # Number of loads committed -system.cpu2.commit.membars 165391 # Number of memory barriers committed -system.cpu2.commit.branches 27813078 # Number of branches committed +system.cpu2.commit.refs 8097053 # Number of memory references committed +system.cpu2.commit.loads 5177878 # Number of loads committed +system.cpu2.commit.membars 162019 # Number of memory barriers committed +system.cpu2.commit.branches 27358633 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248363308 # Number of committed integer instructions. -system.cpu2.commit.function_calls 444774 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 44974 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 263371453 96.85% 96.86% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 56553 0.02% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 47876 0.02% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5378719 1.98% 98.88% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3048550 1.12% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244351653 # Number of committed integer instructions. +system.cpu2.commit.function_calls 425746 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 44568 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 259307312 96.92% 96.94% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52493 0.02% 96.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 45495 0.02% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5177878 1.94% 98.91% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2919175 1.09% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 271948125 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2012729 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 267546921 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1941656 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 432344700 # The number of ROB reads -system.cpu2.rob.rob_writes 563581737 # The number of ROB writes -system.cpu2.timesIdled 114304 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1025768 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4904031691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137795324 # Number of Instructions Simulated -system.cpu2.committedOps 271948125 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.129738 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.129738 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.885161 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.885161 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 370036745 # number of integer regfile reads -system.cpu2.int_regfile_writes 221903617 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72874 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes -system.cpu2.cc_regfile_reads 140867740 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108480868 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90412070 # number of misc regfile reads -system.cpu2.misc_regfile_writes 138782 # number of misc regfile writes +system.cpu2.rob.rob_reads 425004820 # The number of ROB reads +system.cpu2.rob.rob_writes 553782312 # The number of ROB writes +system.cpu2.timesIdled 113608 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 975500 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4910108147 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135526613 # Number of Instructions Simulated +system.cpu2.committedOps 267546921 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.128996 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.128996 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.885742 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.885742 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363608614 # number of integer regfile reads +system.cpu2.int_regfile_writes 218247524 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72984 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 138904210 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106846664 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88678814 # number of misc regfile reads +system.cpu2.misc_regfile_writes 129757 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |