diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 3138 |
1 files changed, 1593 insertions, 1545 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 307acd090..f26bf1c54 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.135764 # Number of seconds simulated -sim_ticks 5135763847500 # Number of ticks simulated -final_tick 5135763847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137881 # Number of seconds simulated +sim_ticks 5137881357500 # Number of ticks simulated +final_tick 5137881357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 259782 # Simulator instruction rate (inst/s) -host_op_rate 516376 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5470381356 # Simulator tick rate (ticks/s) -host_mem_usage 959692 # Number of bytes of host memory used -host_seconds 938.83 # Real time elapsed on the host -sim_insts 243891279 # Number of instructions simulated -sim_ops 484789360 # Number of ops (including micro ops) simulated +host_inst_rate 401147 # Simulator instruction rate (inst/s) +host_op_rate 797370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8430324111 # Simulator tick rate (ticks/s) +host_mem_usage 944704 # Number of bytes of host memory used +host_seconds 609.45 # Real time elapsed on the host +sim_insts 244480058 # Number of instructions simulated +sim_ops 485958826 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2442432 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 470912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6169536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 114240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1582592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 379456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2632640 # Number of bytes read from this memory -system.physmem.bytes_read::total 13794368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 470912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 114240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 379456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9131520 # Number of bytes written to this memory -system.physmem.bytes_written::total 9131520 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38163 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 396800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5697984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 149888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1826880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 430976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2905472 # Number of bytes read from this memory +system.physmem.bytes_read::total 11438656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 149888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 430976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6187584 # Number of bytes written to this memory +system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory +system.physmem.bytes_written::total 9177664 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7358 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 96399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24728 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41135 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215537 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142680 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142680 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 475573 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 89031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 28545 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 45398 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178729 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96681 # Number of write requests responded to by this memory +system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143401 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 91693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1201289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 22244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 308151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 512609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2685943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 91693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 22244 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73885 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1778026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1778026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1778026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 475573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 77230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1109014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 355571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 83882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 565500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2226337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 77230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29173 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 83882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 190285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1204307 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 581968 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1786274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1204307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 587486 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 91693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1201289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 22244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 308151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 512609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4463968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 94056 # Number of read requests accepted -system.physmem.writeReqs 72760 # Number of write requests accepted -system.physmem.readBursts 94056 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 72760 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6015488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4096 # Total number of bytes read from write queue -system.physmem.bytesWritten 4656640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6019584 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4656640 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 64 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 77230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1109014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 355571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 83882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 565500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4012611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 83494 # Number of read requests accepted +system.physmem.writeReqs 76163 # Number of write requests accepted +system.physmem.readBursts 83494 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 76163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5331584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue +system.physmem.bytesWritten 4872768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5343616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4874432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 766 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5609 # Per bank write bursts -system.physmem.perBankRdBursts::1 5668 # Per bank write bursts -system.physmem.perBankRdBursts::2 5585 # Per bank write bursts -system.physmem.perBankRdBursts::3 5594 # Per bank write bursts -system.physmem.perBankRdBursts::4 6037 # Per bank write bursts -system.physmem.perBankRdBursts::5 6612 # Per bank write bursts -system.physmem.perBankRdBursts::6 5733 # Per bank write bursts -system.physmem.perBankRdBursts::7 5990 # Per bank write bursts -system.physmem.perBankRdBursts::8 5523 # Per bank write bursts -system.physmem.perBankRdBursts::9 5460 # Per bank write bursts -system.physmem.perBankRdBursts::10 5647 # Per bank write bursts -system.physmem.perBankRdBursts::11 6128 # Per bank write bursts -system.physmem.perBankRdBursts::12 6059 # Per bank write bursts -system.physmem.perBankRdBursts::13 6267 # Per bank write bursts -system.physmem.perBankRdBursts::14 6194 # Per bank write bursts -system.physmem.perBankRdBursts::15 5886 # Per bank write bursts -system.physmem.perBankWrBursts::0 4545 # Per bank write bursts -system.physmem.perBankWrBursts::1 4402 # Per bank write bursts -system.physmem.perBankWrBursts::2 4127 # Per bank write bursts -system.physmem.perBankWrBursts::3 4299 # Per bank write bursts -system.physmem.perBankWrBursts::4 4675 # Per bank write bursts -system.physmem.perBankWrBursts::5 5126 # Per bank write bursts -system.physmem.perBankWrBursts::6 4327 # Per bank write bursts -system.physmem.perBankWrBursts::7 4679 # Per bank write bursts -system.physmem.perBankWrBursts::8 4360 # Per bank write bursts -system.physmem.perBankWrBursts::9 4207 # Per bank write bursts -system.physmem.perBankWrBursts::10 4528 # Per bank write bursts -system.physmem.perBankWrBursts::11 4822 # Per bank write bursts -system.physmem.perBankWrBursts::12 4836 # Per bank write bursts -system.physmem.perBankWrBursts::13 4641 # Per bank write bursts -system.physmem.perBankWrBursts::14 4944 # Per bank write bursts -system.physmem.perBankWrBursts::15 4242 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 873 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4736 # Per bank write bursts +system.physmem.perBankRdBursts::1 4757 # Per bank write bursts +system.physmem.perBankRdBursts::2 5051 # Per bank write bursts +system.physmem.perBankRdBursts::3 5281 # Per bank write bursts +system.physmem.perBankRdBursts::4 5400 # Per bank write bursts +system.physmem.perBankRdBursts::5 4765 # Per bank write bursts +system.physmem.perBankRdBursts::6 4961 # Per bank write bursts +system.physmem.perBankRdBursts::7 5223 # Per bank write bursts +system.physmem.perBankRdBursts::8 5069 # Per bank write bursts +system.physmem.perBankRdBursts::9 5177 # Per bank write bursts +system.physmem.perBankRdBursts::10 4953 # Per bank write bursts +system.physmem.perBankRdBursts::11 4660 # Per bank write bursts +system.physmem.perBankRdBursts::12 5195 # Per bank write bursts +system.physmem.perBankRdBursts::13 6216 # Per bank write bursts +system.physmem.perBankRdBursts::14 6082 # Per bank write bursts +system.physmem.perBankRdBursts::15 5780 # Per bank write bursts +system.physmem.perBankWrBursts::0 4915 # Per bank write bursts +system.physmem.perBankWrBursts::1 4846 # Per bank write bursts +system.physmem.perBankWrBursts::2 4413 # Per bank write bursts +system.physmem.perBankWrBursts::3 4685 # Per bank write bursts +system.physmem.perBankWrBursts::4 5227 # Per bank write bursts +system.physmem.perBankWrBursts::5 4409 # Per bank write bursts +system.physmem.perBankWrBursts::6 4642 # Per bank write bursts +system.physmem.perBankWrBursts::7 4533 # Per bank write bursts +system.physmem.perBankWrBursts::8 4328 # Per bank write bursts +system.physmem.perBankWrBursts::9 4737 # Per bank write bursts +system.physmem.perBankWrBursts::10 4592 # Per bank write bursts +system.physmem.perBankWrBursts::11 4470 # Per bank write bursts +system.physmem.perBankWrBursts::12 4760 # Per bank write bursts +system.physmem.perBankWrBursts::13 5234 # Per bank write bursts +system.physmem.perBankWrBursts::14 5550 # Per bank write bursts +system.physmem.perBankWrBursts::15 4796 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 5131947184500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 5136881165000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 94056 # Read request sizes (log2) +system.physmem.readPktSize::6 83494 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 72760 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 71094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 76163 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 78715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,474 +168,475 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3262 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.746690 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.799684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.095227 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14318 40.08% 40.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8282 23.18% 63.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3507 9.82% 73.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1954 5.47% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1307 3.66% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 922 2.58% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 623 1.74% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 530 1.48% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4280 11.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35723 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3978 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.627954 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 119.433357 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 3969 99.77% 99.77% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 7 0.18% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38507 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 264.993274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 160.426697 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.053955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15907 41.31% 41.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9655 25.07% 66.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3981 10.34% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2127 5.52% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1469 3.81% 86.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1046 2.72% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 664 1.72% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 555 1.44% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3103 8.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38507 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.615365 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 121.265146 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 3842 99.71% 99.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.21% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 1 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3978 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3978 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.290598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.208175 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.685696 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1 45 1.13% 1.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2-3 5 0.13% 1.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-5 3 0.08% 1.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6-7 4 0.10% 1.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10-11 1 0.03% 1.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14-15 5 0.13% 1.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2627 66.04% 67.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 818 20.56% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 28 0.70% 88.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 32 0.80% 89.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 32 0.80% 90.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 35 0.88% 91.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 65 1.63% 93.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 48 1.21% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 35 0.88% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 29 0.73% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 29 0.73% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 26 0.65% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 31 0.78% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 18 0.45% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 10 0.25% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 17 0.43% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 8 0.20% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 6 0.15% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 2 0.05% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 7 0.18% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 3 0.08% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 4 0.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3978 # Writes before turning the bus around for reads -system.physmem.totQLat 2424873249 # Total ticks spent queuing -system.physmem.totMemAccLat 4187223249 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 469960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25798.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3853 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3853 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.760446 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.599143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.462049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 66 1.71% 1.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 8 0.21% 1.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 10 0.26% 2.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3269 84.84% 87.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 44 1.14% 88.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.67% 88.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 135 3.50% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 114 2.96% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.08% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.36% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.21% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.34% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.05% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.03% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 96 2.49% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.03% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.13% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.34% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.10% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.05% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.13% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3853 # Writes before turning the bus around for reads +system.physmem.totQLat 942120750 # Total ticks spent queuing +system.physmem.totMemAccLat 2504108250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 416530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11309.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44548.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30059.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.04 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.97 # Average write queue length when enqueuing -system.physmem.readRowHits 76538 # Number of row buffer hits during reads -system.physmem.writeRowHits 54491 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.89 # Row buffer hit rate for writes -system.physmem.avgGap 30764118.46 # Average gap between requests -system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4942425043001 # Time in different power states -system.physmem.memoryStateTime::REF 171494180000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.45 # Average write queue length when enqueuing +system.physmem.readRowHits 65566 # Number of row buffer hits during reads +system.physmem.writeRowHits 55368 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.70 # Row buffer hit rate for writes +system.physmem.avgGap 32174481.33 # Average gap between requests +system.physmem.pageHitRate 75.84 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4942580735250 # Time in different power states +system.physmem.memoryStateTime::REF 171564900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 21844559499 # Time in different power states +system.physmem.memoryStateTime::ACT 23734191750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6452408 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 421921 # Transaction distribution -system.membus.trans_dist::ReadResp 421919 # Transaction distribution -system.membus.trans_dist::WriteReq 5915 # Transaction distribution -system.membus.trans_dist::WriteResp 5915 # Transaction distribution -system.membus.trans_dist::Writeback 72760 # Transaction distribution -system.membus.trans_dist::UpgradeReq 778 # Transaction distribution -system.membus.trans_dist::UpgradeResp 778 # Transaction distribution -system.membus.trans_dist::ReadExReq 75224 # Transaction distribution -system.membus.trans_dist::ReadExResp 75224 # Transaction distribution -system.membus.trans_dist::MessageReq 825 # Transaction distribution -system.membus.trans_dist::MessageResp 825 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1650 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1650 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308134 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196326 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1002050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72232 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72232 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1075932 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3300 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3300 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 157715 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995169 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7734720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 8887604 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2941504 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2941504 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 11832408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32744958 # Total data (bytes) -system.membus.snoop_data_through_bus 393088 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 161596500 # Layer occupancy (ticks) +system.membus.throughput 5877722 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 425622 # Transaction distribution +system.membus.trans_dist::ReadResp 425619 # Transaction distribution +system.membus.trans_dist::WriteReq 7303 # Transaction distribution +system.membus.trans_dist::WriteResp 7303 # Transaction distribution +system.membus.trans_dist::Writeback 54691 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 21472 # Transaction distribution +system.membus.trans_dist::UpgradeReq 873 # Transaction distribution +system.membus.trans_dist::UpgradeResp 873 # Transaction distribution +system.membus.trans_dist::ReadExReq 56661 # Transaction distribution +system.membus.trans_dist::ReadExResp 56661 # Transaction distribution +system.membus.trans_dist::MessageReq 1005 # Transaction distribution +system.membus.trans_dist::MessageResp 1005 # Transaction distribution +system.membus.trans_dist::BadAddressError 3 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 2010 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 2010 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 313168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 222539 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 6 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1034159 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 44112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 44112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1080281 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 4020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 4020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160913 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996889 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8815488 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9973290 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1402560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 1402560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 11379870 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30180989 # Total data (bytes) +system.membus.snoop_data_through_bus 18048 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 165986000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315113000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315728000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1650000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2010000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 794070497 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 815495498 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 825000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1005000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1569908183 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1662343876 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 236956000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 28017243 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 104346 # number of replacements -system.l2c.tags.tagsinuse 64811.945905 # Cycle average of tags in use -system.l2c.tags.total_refs 3669840 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168730 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.749778 # Average number of references to valid blocks. +system.l2c.tags.replacements 105452 # number of replacements +system.l2c.tags.tagsinuse 64826.295665 # Cycle average of tags in use +system.l2c.tags.total_refs 3690842 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169644 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.756396 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51276.768453 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121941 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1221.298902 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4234.138382 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 249.507225 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1581.676468 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.253356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1493.843089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4747.335130 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.782421 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50973.887089 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131156 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1039.864675 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3857.355286 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 297.125354 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1525.078899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.736641 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003210 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1792.530465 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5328.582890 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.777800 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.018636 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064608 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003807 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.024134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000111 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.022794 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.072439 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988952 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64384 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2861 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7799 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53379 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.982422 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33692585 # Number of tag accesses -system.l2c.tags.data_accesses 33692585 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 19944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10836 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 348846 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 522725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9533 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5021 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 144714 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 221166 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 56163 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 10079 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 347465 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 563204 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2259696 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.015867 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058859 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004534 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023271 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.027352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.081308 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64192 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 605 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7395 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52837 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979492 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33876235 # Number of tag accesses +system.l2c.tags.data_accesses 33876235 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 20790 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10881 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 323642 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 493790 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 11848 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6379 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 159823 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 243124 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 53625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 12570 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 372046 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 571492 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2280010 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1546042 # number of Writeback hits -system.l2c.Writeback_hits::total 1546042 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 73 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 259 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 69718 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 41748 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 55006 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166472 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 19944 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10838 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 348846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 592443 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9533 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5021 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 144714 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 262914 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 56163 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 10079 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 347465 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 618210 # number of demand (read+write) hits -system.l2c.demand_hits::total 2426170 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19944 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10838 # number of overall hits -system.l2c.overall_hits::cpu0.inst 348846 # number of overall hits -system.l2c.overall_hits::cpu0.data 592443 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9533 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5021 # number of overall hits -system.l2c.overall_hits::cpu1.inst 144714 # number of overall hits -system.l2c.overall_hits::cpu1.data 262914 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 56163 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10079 # number of overall hits -system.l2c.overall_hits::cpu2.inst 347465 # number of overall hits -system.l2c.overall_hits::cpu2.data 618210 # number of overall hits -system.l2c.overall_hits::total 2426170 # number of overall hits +system.l2c.Writeback_hits::writebacks 1547750 # number of Writeback hits +system.l2c.Writeback_hits::total 1547750 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 119 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 62 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 66 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 247 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 66599 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 37683 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 62729 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167011 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 20790 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10883 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 323642 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 560389 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11848 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6379 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 159823 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 280807 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 53625 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 12570 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 372046 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 634221 # number of demand (read+write) hits +system.l2c.demand_hits::total 2447023 # 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miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143944.153084 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 143944.153084 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 128791.165625 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 128791.165625 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129080.048480 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129080.048480 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 86048 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145544.142227 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145544.142227 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145544.142227 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7909 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.879757 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 735 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 735 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 25536 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 25536 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 26271 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 26271 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 26271 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 26271 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92456791 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 92456791 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4688241758 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4688241758 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4780698549 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4780698549 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.809471 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.809471 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.546575 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.546575 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.551587 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.551587 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125791.552381 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 125791.552381 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 183593.427240 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 183593.427240 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 725 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 725 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21472 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 21472 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 725 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 94282037 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1310743323 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1310743323 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 94282037 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 94282037 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.799338 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.459589 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.459589 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.799338 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.799338 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130044.188966 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61044.305281 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61044.305281 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -879,511 +884,555 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52407719 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1793633 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1793101 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 5915 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 5915 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 899960 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 730 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 730 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 172146 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 146613 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 999818 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3602290 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 141650 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4778107 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31993152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119401652 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 525848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152041460 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 269011854 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 141816 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5025953302 # Layer occupancy (ticks) +system.toL2Bus.throughput 53202678 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1873297 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1872762 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 7303 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 7303 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 935388 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 816 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 816 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 157258 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 157258 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1081926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3727147 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 42874 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 142768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4994715 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34620672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 124341034 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 151600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 524032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 159637338 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 270199237 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 3149808 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5231949371 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 868500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2251918114 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2437443949 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4677619434 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4869271823 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19272449 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23963155 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 76057203 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 77561882 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1276582 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 149714 # Transaction distribution -system.iobus.trans_dist::ReadResp 149714 # Transaction distribution -system.iobus.trans_dist::WriteReq 30624 # Transaction distribution -system.iobus.trans_dist::WriteResp 30624 # Transaction distribution -system.iobus.trans_dist::MessageReq 825 # Transaction distribution -system.iobus.trans_dist::MessageResp 825 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4890 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1275815 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 151004 # Transaction distribution +system.iobus.trans_dist::ReadResp 151004 # Transaction distribution +system.iobus.trans_dist::WriteReq 27777 # Transaction distribution +system.iobus.trans_dist::WriteResp 27777 # Transaction distribution +system.iobus.trans_dist::MessageReq 1005 # Transaction distribution +system.iobus.trans_dist::MessageResp 1005 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 588 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287208 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 156 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 308134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 52542 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 52542 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1650 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1650 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 362326 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 594 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 142 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 16180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 313168 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 44394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 44394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 2010 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 2010 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 359572 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3164 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 294 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143604 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6513 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 157715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1670648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1670648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3300 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1831663 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6556225 # Total data (bytes) -system.iobus.reqLayer0.occupancy 1987954 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143631 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1188 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 71 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 8090 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 160913 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1410472 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1410472 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 4020 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 4020 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1575405 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6554984 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2375600 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4046000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4638000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 387000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143605000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143632000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 124000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 469000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9774000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12075000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 232428549 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 194319603 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303046000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306863000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 31488000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 26743757 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 825000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1005000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1167096017 # number of cpu cycles simulated +system.cpu0.numCycles 1069887436 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72932334 # Number of instructions committed -system.cpu0.committedOps 148186849 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 136173063 # Number of integer alu accesses +system.cpu0.committedInsts 70857782 # Number of instructions committed +system.cpu0.committedOps 144307609 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 132405898 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1014433 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14332221 # number of instructions that are conditional controls -system.cpu0.num_int_insts 136173063 # number of integer instructions +system.cpu0.num_func_calls 941314 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14024705 # number of instructions that are conditional controls +system.cpu0.num_int_insts 132405898 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 250637191 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116800630 # number of times the integer registers were written +system.cpu0.num_int_register_reads 243097330 # number of times the integer registers were read +system.cpu0.num_int_register_writes 113712565 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84487712 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56367816 # number of times the CC registers were written -system.cpu0.num_mem_refs 14369378 # number of memory refs -system.cpu0.num_load_insts 10451844 # Number of load instructions -system.cpu0.num_store_insts 3917534 # Number of store instructions -system.cpu0.num_idle_cycles 1108227141.183960 # Number of idle cycles -system.cpu0.num_busy_cycles 58868875.816040 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050440 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949560 # Percentage of idle cycles -system.cpu0.Branches 15712912 # Number of branches fetched -system.cpu0.op_class::No_OpClass 100385 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 133601927 90.16% 90.23% # Class of executed instruction -system.cpu0.op_class::IntMult 62763 0.04% 90.27% # Class of executed instruction -system.cpu0.op_class::IntDiv 53014 0.04% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::MemRead 10451844 7.05% 97.36% # Class of executed instruction -system.cpu0.op_class::MemWrite 3917534 2.64% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82467233 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55021807 # number of times the CC registers were written +system.cpu0.num_mem_refs 13631596 # number of memory refs +system.cpu0.num_load_insts 10001277 # Number of load instructions +system.cpu0.num_store_insts 3630319 # Number of store instructions +system.cpu0.num_idle_cycles 1016044794.752217 # Number of idle cycles +system.cpu0.num_busy_cycles 53842641.247783 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050326 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949674 # Percentage of idle cycles +system.cpu0.Branches 15304700 # Number of branches fetched +system.cpu0.op_class::No_OpClass 96295 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 130472194 90.41% 90.48% # Class of executed instruction +system.cpu0.op_class::IntMult 58212 0.04% 90.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 49897 0.03% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::MemRead 10001277 6.93% 97.48% # Class of executed instruction +system.cpu0.op_class::MemWrite 3630319 2.52% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 148187467 # Class of executed instruction +system.cpu0.op_class::total 144308194 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 855609 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.820181 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129797062 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856121 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 151.610651 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147456803500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 296.387192 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 131.510981 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 82.922008 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.578881 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.256857 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.161957 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997696 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 870298 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.224543 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128999874 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 870810 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 148.137796 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147420132000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.471919 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.049993 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.702632 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.245062 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.267676 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.483794 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996532 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131529533 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131529533 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 88736608 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38254506 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2805948 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129797062 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 88736608 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38254506 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2805948 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129797062 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 88736608 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38254506 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2805948 # number of overall hits -system.cpu0.icache.overall_hits::total 129797062 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 356206 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 146499 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 373635 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 876340 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 356206 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 146499 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 373635 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 876340 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 356206 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 146499 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 373635 # number of overall misses -system.cpu0.icache.overall_misses::total 876340 # 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Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010426 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.173145 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 234.203255 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 22.623054 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.498385 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.457428 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.044186 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 210 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88326830 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88326830 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5302140 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2350453 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3934991 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11587584 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3761995 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1605612 # 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number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683289 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 151041 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 62696 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 101955 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 315692 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 690181 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 288114 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1020686 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1998981 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 690181 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 288114 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1020686 # number of overall misses -system.cpu0.dcache.overall_misses::total 1998981 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3220560254 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 14575132809 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17795693063 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2058114299 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3117330338 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5175444637 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5278674553 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 17692463147 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 22971137700 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5278674553 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 17692463147 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 22971137700 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5841280 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2575871 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4853722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13270873 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3913036 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1668308 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2820304 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8401648 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9754316 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4244179 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7674026 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21672521 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9754316 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4244179 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7674026 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21672521 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.092298 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.087511 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.189284 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.126841 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038599 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.037581 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.036150 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037575 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.070756 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.067885 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.133005 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092236 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070756 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.067885 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133005 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092236 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14287.058948 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15864.418213 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10571.977280 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32826.883677 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30575.551351 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16393.968289 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18321.478835 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17333.894211 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 11491.423730 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18321.478835 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17333.894211 # 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number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 751040 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1284020 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 140767 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 64096 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 121973 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 326836 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148377 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 75751 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 181169 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 405297 # number of SoftPFReq misses +system.cpu0.dcache.demand_misses::cpu0.data 501988 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 235855 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 873013 # 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number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4713906 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7943100 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21680133 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.069073 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060818 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.157823 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.100216 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038809 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035569 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041035 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.038902 # 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number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2768607746 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8066658535 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10835266281 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1923226701 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2756691504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4679918205 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4691834447 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10823350039 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15515184486 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4691834447 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10823350039 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15515184486 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30492689000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33165040000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63657729000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 394150500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 725206000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1119356500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30886839500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33890246000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64777085500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087511 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118564 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060350 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037581 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030000 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017533 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.043751 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.043751 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12282.105892 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14017.294350 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13528.913557 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30675.429070 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32581.924924 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31770.476056 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1547750 # number of writebacks +system.cpu0.dcache.writebacks::total 1547750 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 72 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 345273 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 345345 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1671 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 26387 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 28058 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1743 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 371660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 373403 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1743 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 371660 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 373403 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171687 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 405767 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 577454 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62425 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95586 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 158011 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 75736 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 178762 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 254498 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 234112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 501353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 735465 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 309848 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 680115 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 989963 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2023850750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5632729880 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7656580630 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2144841050 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3093501359 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5238342409 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 984108500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2694382756 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3678491256 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4168691800 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8726231239 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12894923039 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5152800300 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11420613995 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16573414295 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30657477000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33314384500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63971861500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 501111500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 893222000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394333500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31158588500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34207606500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65366195000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060792 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085267 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045070 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034642 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032158 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018807 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.863187 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.843348 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.546074 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050606 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.064849 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034669 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065731 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085623 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045662 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11788.025593 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13881.685499 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13259.204421 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34358.687225 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32363.540257 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33151.757846 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12993.932872 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15072.458106 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14453.910270 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17806.399501 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17405.363564 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17533.020659 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16630.090561 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16792.180727 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16741.448211 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1394,377 +1443,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604023259 # number of cpu cycles simulated +system.cpu1.numCycles 2606024060 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34762499 # Number of instructions committed -system.cpu1.committedOps 67606793 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62736553 # Number of integer alu accesses +system.cpu1.committedInsts 35944624 # Number of instructions committed +system.cpu1.committedOps 69816061 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64937038 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 437056 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6403696 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62736553 # number of integer instructions +system.cpu1.num_func_calls 484528 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6597164 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64937038 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 115724590 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54164636 # number of times the integer registers were written +system.cpu1.num_int_register_reads 120144832 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55989327 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35537675 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26584960 # number of times the CC registers were written -system.cpu1.num_mem_refs 4433444 # number of memory refs -system.cpu1.num_load_insts 2764122 # Number of load instructions -system.cpu1.num_store_insts 1669322 # Number of store instructions -system.cpu1.num_idle_cycles 2476870816.288117 # Number of idle cycles -system.cpu1.num_busy_cycles 127152442.711883 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048829 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951171 # Percentage of idle cycles -system.cpu1.Branches 7001569 # Number of branches fetched -system.cpu1.op_class::No_OpClass 28648 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 63095899 93.33% 93.37% # Class of executed instruction -system.cpu1.op_class::IntMult 28577 0.04% 93.41% # Class of executed instruction -system.cpu1.op_class::IntDiv 20525 0.03% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::MemRead 2764122 4.09% 97.53% # Class of executed instruction -system.cpu1.op_class::MemWrite 1669322 2.47% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36928761 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27400948 # number of times the CC registers were written +system.cpu1.num_mem_refs 4904439 # number of memory refs +system.cpu1.num_load_insts 3100845 # Number of load instructions +system.cpu1.num_store_insts 1803594 # Number of store instructions +system.cpu1.num_idle_cycles 2475176569.081452 # Number of idle cycles +system.cpu1.num_busy_cycles 130847490.918548 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050210 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949790 # Percentage of idle cycles +system.cpu1.Branches 7263647 # Number of branches fetched +system.cpu1.op_class::No_OpClass 35052 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64819822 92.84% 92.89% # Class of executed instruction +system.cpu1.op_class::IntMult 29822 0.04% 92.94% # Class of executed instruction +system.cpu1.op_class::IntDiv 27277 0.04% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::MemRead 3100845 4.44% 97.42% # Class of executed instruction +system.cpu1.op_class::MemWrite 1803594 2.58% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 67607093 # Class of executed instruction +system.cpu1.op_class::total 69816412 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28894520 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28894520 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 314484 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26386768 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25807983 # Number of BTB hits +system.cpu2.branchPred.lookups 29512659 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29512659 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 322904 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26886254 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 26249300 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.806533 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 541788 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 61672 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154118891 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.630931 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 591365 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 64668 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155365551 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9526926 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142222809 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28894520 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26349771 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54464711 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1558370 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 64917 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 23183087 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 4981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6096 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 25004 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3179586 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 151181 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1925 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 88503258 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.167922 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.413230 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10587640 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145508462 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29512659 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26840665 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 143230873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 673912 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 95091 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 7931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8903 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 52631 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 2801 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3432374 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 167414 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3341 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154322486 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.857387 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.033367 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 34173678 38.61% 38.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 596420 0.67% 39.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23721602 26.80% 66.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 320974 0.36% 66.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 619988 0.70% 67.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 815233 0.92% 68.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 353145 0.40% 68.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 523827 0.59% 69.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27378391 30.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98410042 63.77% 63.77% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 833989 0.54% 64.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 24035117 15.57% 79.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 597750 0.39% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 798628 0.52% 80.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 859445 0.56% 81.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 568143 0.37% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 716402 0.46% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27502970 17.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 88503258 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.187482 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.922812 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10770329 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 22316529 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 33210052 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 993418 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1230628 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 279539625 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 15 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1230628 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11632631 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 11620518 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4366536 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 33251587 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 6419117 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278526444 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 145793 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2942087 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 39888 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 2722851 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 332982462 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 606515542 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 372413837 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321866415 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11116047 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 145000 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 146469 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 9034946 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6263244 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3375371 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 381006 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 309187 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276743563 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 411647 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274777165 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 83308 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7862427 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12385425 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 57804 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 88503258 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.104712 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.400001 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154322486 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189956 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.936556 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10280285 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95091051 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22517334 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5911995 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 337607 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283677190 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 337607 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12887048 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76613528 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4915145 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 25582017 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13802994 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 282449598 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 208301 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 6363616 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 49211 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4861555 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 337331977 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 615247721 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 378014471 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 325050122 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12281853 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 158846 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 160455 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 28628976 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6469632 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3638513 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 420201 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 343826 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 280493266 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 428842 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 278404006 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 102314 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8748691 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13528194 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 64074 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154322486 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.804040 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.401684 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 25772149 29.12% 29.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5479119 6.19% 35.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3780646 4.27% 39.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2658058 3.00% 42.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25098242 28.36% 70.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1415095 1.60% 72.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23897363 27.00% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 310729 0.35% 99.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 91857 0.10% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 91177599 59.08% 59.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5361636 3.47% 62.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3887403 2.52% 65.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4108764 2.66% 67.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 21799190 14.13% 81.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 3056480 1.98% 83.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24267786 15.73% 99.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 453628 0.29% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 210000 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 88503258 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154322486 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 130084 34.74% 34.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 34.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 103 0.03% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 196279 52.42% 87.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 48005 12.82% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2321368 89.34% 89.34% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 246 0.01% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 217075 8.35% 97.70% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 59662 2.30% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 79957 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264964709 96.43% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54296 0.02% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50937 0.02% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6495012 2.36% 98.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3132254 1.14% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 72561 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 268083598 96.29% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 57882 0.02% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 47134 0.02% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6794594 2.44% 98.80% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3348237 1.20% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274777165 # Type of FU issued -system.cpu2.iq.rate 1.782891 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 374471 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001363 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 638559252 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 285021199 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273394851 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275071659 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 655974 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 278404006 # Type of FU issued +system.cpu2.iq.rate 1.791929 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2598351 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.009333 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 713831099 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 289675272 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 276815941 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 63 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 280929766 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 30 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 708692 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1102337 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6308 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4079 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 550460 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1202973 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6613 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5162 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 660777 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656385 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 7890 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 754641 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 21520 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1230628 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6003858 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 2680102 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277155210 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 55656 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6263266 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3375371 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 233323 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 631738 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1840063 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4079 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 177700 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 182074 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 359774 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 274266101 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6377623 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 511064 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 337607 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 71713264 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1590839 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 280922108 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 41019 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6469632 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3638513 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 247100 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 199459 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1088059 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5162 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 186556 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 187873 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 374429 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 277824668 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6659327 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 530499 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9440682 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27899539 # Number of branches executed -system.cpu2.iew.exec_stores 3063059 # Number of stores executed -system.cpu2.iew.exec_rate 1.779575 # Inst execution rate -system.cpu2.iew.wb_sent 274107922 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273394865 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213810949 # num instructions producing a value -system.cpu2.iew.wb_consumers 349940477 # num instructions consuming a value +system.cpu2.iew.exec_refs 9922055 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28210243 # Number of branches executed +system.cpu2.iew.exec_stores 3262728 # Number of stores executed +system.cpu2.iew.exec_rate 1.788200 # Inst execution rate +system.cpu2.iew.wb_sent 277637651 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 276815959 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215923076 # num instructions producing a value +system.cpu2.iew.wb_consumers 354065892 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.773922 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.610992 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.781707 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609839 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8157845 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 353843 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 317282 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 87272630 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.082246 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.874009 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9085200 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 364768 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 325355 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 152966387 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.777091 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.654040 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30201439 34.61% 34.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4017102 4.60% 39.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1154677 1.32% 40.53% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24628965 28.22% 68.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 905267 1.04% 69.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 589610 0.68% 70.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 344278 0.39% 70.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23302755 26.70% 97.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2128537 2.44% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95002675 62.11% 62.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4175839 2.73% 64.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1266091 0.83% 65.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24954040 16.31% 81.98% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 981729 0.64% 82.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 650164 0.43% 83.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 435006 0.28% 83.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23529501 15.38% 98.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1971342 1.29% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 87272630 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136196446 # Number of instructions committed -system.cpu2.commit.committedOps 268995718 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 152966387 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137677652 # Number of instructions committed +system.cpu2.commit.committedOps 271835156 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7985840 # Number of memory references committed -system.cpu2.commit.loads 5160929 # Number of loads committed -system.cpu2.commit.membars 163767 # Number of memory barriers committed -system.cpu2.commit.branches 27540439 # Number of branches committed +system.cpu2.commit.refs 8244394 # Number of memory references committed +system.cpu2.commit.loads 5266658 # Number of loads committed +system.cpu2.commit.membars 166791 # Number of memory barriers committed +system.cpu2.commit.branches 27802655 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245590309 # Number of committed integer instructions. -system.cpu2.commit.function_calls 428081 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 46387 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 260861796 96.98% 96.99% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 52266 0.02% 97.01% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 49429 0.02% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5160929 1.92% 98.95% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2824911 1.05% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 248203210 # Number of committed integer instructions. +system.cpu2.commit.function_calls 440588 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 43200 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 263446464 96.91% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 55564 0.02% 96.95% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 45534 0.02% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5266658 1.94% 98.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2977736 1.10% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 268995718 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2128537 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 271835156 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1971342 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 362270810 # The number of ROB reads -system.cpu2.rob.rob_writes 555542201 # The number of ROB writes -system.cpu2.timesIdled 475518 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65615633 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4908375985 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136196446 # Number of Instructions Simulated -system.cpu2.committedOps 268995718 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.131593 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.131593 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.883710 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.883710 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364616127 # number of integer regfile reads -system.cpu2.int_regfile_writes 219111496 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72926 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139466740 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107376389 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88828545 # number of misc regfile reads -system.cpu2.misc_regfile_writes 129118 # number of misc regfile writes +system.cpu2.rob.rob_reads 431889681 # The number of ROB reads +system.cpu2.rob.rob_writes 563202973 # The number of ROB writes +system.cpu2.timesIdled 114782 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1043065 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4908353341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137677652 # Number of Instructions Simulated +system.cpu2.committedOps 271835156 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.128473 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.128473 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.886153 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.886153 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 369541594 # number of integer regfile reads +system.cpu2.int_regfile_writes 221773447 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72930 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 140769340 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108468562 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90221682 # number of misc regfile reads +system.cpu2.misc_regfile_writes 135530 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |