diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
3 files changed, 920 insertions, 888 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini index 24fafe7e3..f714521bf 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini @@ -21,7 +21,7 @@ exit_on_work_items=false init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9.smp kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -31,7 +31,7 @@ memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 -readfile=/z/stever/hg/gem5/tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -710,7 +710,7 @@ response_latency=2 use_default_range=false width=16 default=system.pc.pci_host.pio -master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave +master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave[0] slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port system.ruby.l1_cntrl1.sequencer.pio_master_port system.ruby.l1_cntrl1.sequencer.mem_master_port [system.mem_ctrls] @@ -1083,7 +1083,7 @@ pci_dev=4 pci_func=0 pio_latency=30000 system=system -dma=system.ruby.dma_cntrl0.dma_sequencer.slave +dma=system.ruby.dma_cntrl0.dma_sequencer.slave[0] pio=system.iobus.master[2] [system.pc.south_bridge.ide.disks0] @@ -1106,7 +1106,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1129,7 +1129,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1423,7 +1423,11 @@ version=0 type=DMASequencer clk_domain=system.ruby.clk_domain eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true system=system using_ruby_tester=false version=0 @@ -1475,7 +1479,11 @@ version=1 type=DMASequencer clk_domain=system.ruby.clk_domain eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true system=system using_ruby_tester=false version=1 @@ -1539,6 +1547,7 @@ version=0 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1562,6 +1571,7 @@ size=32768 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1642,12 +1652,14 @@ slave=system.ruby.network.master[1] [system.ruby.l1_cntrl0.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1706,6 +1718,7 @@ version=1 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1729,6 +1742,7 @@ size=32768 type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -1809,12 +1823,14 @@ slave=system.ruby.network.master[3] [system.ruby.l1_cntrl1.sequencer] type=RubySequencer clk_domain=system.cpu_clk_domain +coreid=99 dcache=system.ruby.l1_cntrl1.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 eventq_index=0 icache=system.ruby.l1_cntrl1.L1Icache icache_hit_latency=1 +is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false ruby_system=system.ruby @@ -1890,6 +1906,7 @@ slave=system.ruby.network.master[5] type=RubyCache children=replacement_policy assoc=2 +block_size=0 dataAccessLatency=1 dataArrayBanks=1 eventq_index=0 @@ -3555,6 +3572,7 @@ version= type=RubyPortProxy clk_domain=system.clk_domain eventq_index=0 +is_cpu_sequencer=true no_retry_on_stall=false ruby_system=system.ruby support_data_reqs=true diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout index b6083331b..0662b1db4 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout +Redirecting stderr to build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2015 02:51:00 -gem5 started Dec 30 2015 02:51:16 -gem5 executing on zizzer, pid 30304 -command line: build/X86_MESI_Two_Level/gem5.opt -d build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level -re /z/stever/hg/gem5/tests/run.py build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level +gem5 compiled Mar 15 2016 21:26:21 +gem5 started Mar 15 2016 21:35:42 +gem5 executing on phenom, pid 15979 +command line: build/X86_MESI_Two_Level/gem5.opt -d build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9.smp 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5221333868500 because m5_exit instruction encountered +Exiting @ tick 5220166723500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index c56d79e86..867862e29 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.221334 # Number of seconds simulated -sim_ticks 5221333868500 # Number of ticks simulated -final_tick 5221333868500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.220167 # Number of seconds simulated +sim_ticks 5220166723500 # Number of ticks simulated +final_tick 5220166723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231127 # Simulator instruction rate (inst/s) -host_op_rate 448792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7989012150 # Simulator tick rate (ticks/s) -host_mem_usage 840496 # Number of bytes of host memory used -host_seconds 653.56 # Real time elapsed on the host -sim_insts 151056351 # Number of instructions simulated -sim_ops 293314763 # Number of ops (including micro ops) simulated +host_inst_rate 149296 # Simulator instruction rate (inst/s) +host_op_rate 289896 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5158950187 # Simulator tick rate (ticks/s) +host_mem_usage 785372 # Number of bytes of host memory used +host_seconds 1011.87 # Real time elapsed on the host +sim_insts 151067812 # Number of instructions simulated +sim_ops 293336428 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11629312 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11629312 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9426176 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9426176 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 181708 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 181708 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 147284 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 147284 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2227268 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2227268 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1805320 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1805320 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 4032588 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 4032588 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 181708 # Number of read requests accepted -system.mem_ctrls.writeReqs 147284 # Number of write requests accepted -system.mem_ctrls.readBursts 181708 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 147284 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11602432 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 26880 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9421952 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11629312 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9426176 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 420 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 38 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11621312 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11621312 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9422976 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9422976 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 181583 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 181583 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 147234 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 147234 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2226234 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2226234 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1805110 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1805110 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 4031344 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 4031344 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 181583 # Number of read requests accepted +system.mem_ctrls.writeReqs 147234 # Number of write requests accepted +system.mem_ctrls.readBursts 181583 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 147234 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11591808 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 29504 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9419008 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11621312 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9422976 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 33 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 11314 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 10807 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 10914 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11597 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11232 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 10764 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 11927 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10886 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 12498 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 12229 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 11811 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 12012 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 11054 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10768 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 10808 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10667 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 10064 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 9271 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 8835 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 9280 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9017 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9023 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 9283 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 11329 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10774 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10935 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11505 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11170 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 10899 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 11836 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10884 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 12484 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 12159 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 11756 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 12007 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 11147 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10761 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10863 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10613 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 10067 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 9205 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8897 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9266 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9038 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9160 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 9230 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 8385 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 9360 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 9330 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 9168 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 9776 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 9055 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 9213 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 9312 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8846 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 9312 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 9251 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 9047 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9790 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 9121 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 9097 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9389 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 8917 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5221333759000 # Total gap between requests +system.mem_ctrls.totGap 5220166614000 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 181708 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 181583 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 147284 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 181180 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 108 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 147234 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 181021 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 101 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2017 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2735 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8763 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9316 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8850 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9486 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9467 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8661 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9271 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9346 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8739 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8814 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8669 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8742 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8346 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8398 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8475 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 8270 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 148 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 123 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 118 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 107 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 92 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 78 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 67 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2012 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2729 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8785 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9320 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8843 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9495 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9462 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8653 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9363 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9364 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8726 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8830 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8641 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8729 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8351 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8407 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8469 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 8257 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 137 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 112 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 95 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 89 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 83 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 61 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 32 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 21 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 9 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -184,75 +184,76 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 59929 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 350.820471 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 206.478602 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 350.358122 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 19905 33.21% 33.21% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 13767 22.97% 56.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6125 10.22% 66.41% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3674 6.13% 72.54% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2562 4.28% 76.81% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2015 3.36% 80.17% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1654 2.76% 82.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1396 2.33% 85.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8831 14.74% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 59929 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 8213 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.069159 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 311.468449 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 8207 99.93% 99.93% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 59923 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 350.629174 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 206.226666 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 350.561474 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 19936 33.27% 33.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 13794 23.02% 56.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6108 10.19% 66.48% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3634 6.06% 72.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2579 4.30% 76.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1995 3.33% 80.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1624 2.71% 82.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1412 2.36% 85.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8841 14.75% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 59923 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 8207 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.065919 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 311.578267 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 8201 99.93% 99.93% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 8213 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 8213 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.924997 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.593825 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 3.939969 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 6150 74.88% 74.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 17 0.21% 75.09% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 147 1.79% 76.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 19 0.23% 77.11% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 39 0.47% 77.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 480 5.84% 83.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 195 2.37% 85.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 58 0.71% 86.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 616 7.50% 94.01% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 111 1.35% 95.36% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 6 0.07% 95.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.59% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 281 3.42% 99.01% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 5 0.06% 99.07% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 6 0.07% 99.15% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 4 0.05% 99.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.28% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 4 0.05% 99.33% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.34% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 1 0.01% 99.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 6 0.07% 99.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 3 0.04% 99.46% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 3 0.04% 99.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 6 0.07% 99.57% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 2 0.02% 99.60% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 8 0.10% 99.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 3 0.04% 99.73% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 2 0.02% 99.76% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 6 0.07% 99.83% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 4 0.05% 99.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::46 1 0.01% 99.89% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 3 0.04% 99.94% # Writes before turning the bus around for reads +system.mem_ctrls.rdPerTurnAround::total 8207 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 8207 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 17.932497 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.599692 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 3.953739 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 6146 74.89% 74.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 20 0.24% 75.13% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 127 1.55% 76.68% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 26 0.32% 77.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 39 0.48% 77.47% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 486 5.92% 83.39% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 193 2.35% 85.74% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 58 0.71% 86.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 617 7.52% 93.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 104 1.27% 95.24% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 8 0.10% 95.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 15 0.18% 95.52% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 293 3.57% 99.09% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 4 0.05% 99.13% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 1 0.01% 99.15% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 3 0.04% 99.18% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 10 0.12% 99.31% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 2 0.02% 99.39% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 2 0.02% 99.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::36 5 0.06% 99.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.49% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 5 0.06% 99.55% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 2 0.02% 99.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.61% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 5 0.06% 99.67% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 2 0.02% 99.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.73% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 3 0.04% 99.77% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 5 0.06% 99.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::46 2 0.02% 99.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::49 2 0.02% 99.94% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::50 1 0.01% 99.95% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::51 4 0.05% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 8213 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1928702995 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5327852995 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 906440000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 10638.89 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::total 8207 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1926054246 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5322091746 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 905610000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 10634.02 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29388.89 # Average memory access latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29384.02 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s @@ -263,252 +264,252 @@ system.mem_ctrls.busUtilRead 0.02 # Da system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 25.93 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 146985 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 121591 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.08 # Row buffer hit rate for reads +system.mem_ctrls.readRowHits 146815 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 121555 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 81.06 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 82.58 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 15870701.29 # Average gap between requests -system.mem_ctrls.pageHitRate 81.75 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 222112800 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 121192500 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 697632000 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 474063840 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 341031690480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 139634929485 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3010309497750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3492491118855 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 668.889543 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5007813786500 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 174351580000 # Time in different power states +system.mem_ctrls.avgGap 15875598.32 # Average gap between requests +system.mem_ctrls.pageHitRate 81.74 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 222014520 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 121138875 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 696781800 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 474647040 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 340955406480 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 139500530325 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3009726629250 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3491697148290 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 668.887101 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5006844557250 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 174312580000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 39168401500 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 39009485750 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 230950440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 126014625 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 716406600 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 479908800 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 341031690480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 139433194800 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3010486458000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3492504623745 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 668.892130 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5008096006750 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 174351580000 # Time in different power states +system.mem_ctrls_1.actEnergy 231003360 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 126043500 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 715962000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 479027520 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 340955406480 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 139411599210 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3009804639000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3491723681070 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 668.892184 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5006961679500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 174312580000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 38879557000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 38884946750 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10442667737 # number of cpu cycles simulated +system.cpu0.numCycles 10440333447 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.committedInsts 100536787 # Number of instructions committed -system.cpu0.committedOps 194797820 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 182088728 # Number of integer alu accesses +system.cpu0.committedInsts 100619599 # Number of instructions committed +system.cpu0.committedOps 194912227 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 182208047 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu0.num_func_calls 1786032 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 17861747 # number of instructions that are conditional controls -system.cpu0.num_int_insts 182088728 # number of integer instructions +system.cpu0.num_func_calls 1789060 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 17876463 # number of instructions that are conditional controls +system.cpu0.num_int_insts 182208047 # number of integer instructions system.cpu0.num_fp_insts 48 # number of float instructions -system.cpu0.num_int_register_reads 340615084 # number of times the integer registers were read -system.cpu0.num_int_register_writes 155370018 # number of times the integer registers were written +system.cpu0.num_int_register_reads 340866599 # number of times the integer registers were read +system.cpu0.num_int_register_writes 155423898 # number of times the integer registers were written system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 104545129 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 75102334 # number of times the CC registers were written -system.cpu0.num_mem_refs 18441276 # number of memory refs -system.cpu0.num_load_insts 11598405 # Number of load instructions -system.cpu0.num_store_insts 6842871 # Number of store instructions -system.cpu0.num_idle_cycles 9945199528.030096 # Number of idle cycles -system.cpu0.num_busy_cycles 497468208.969905 # Number of busy cycles -system.cpu0.not_idle_fraction 0.047638 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.952362 # Percentage of idle cycles -system.cpu0.Branches 20259444 # Number of branches fetched -system.cpu0.op_class::No_OpClass 186601 0.10% 0.10% # Class of executed instruction -system.cpu0.op_class::IntAlu 175972167 90.34% 90.43% # Class of executed instruction -system.cpu0.op_class::IntMult 117562 0.06% 90.49% # Class of executed instruction -system.cpu0.op_class::IntDiv 85295 0.04% 90.54% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::FloatCvt 16 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.54% # Class of executed instruction -system.cpu0.op_class::MemRead 11594261 5.95% 96.49% # Class of executed instruction -system.cpu0.op_class::MemWrite 6842871 3.51% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 104641558 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 75150612 # number of times the CC registers were written +system.cpu0.num_mem_refs 18466644 # number of memory refs +system.cpu0.num_load_insts 11577076 # Number of load instructions +system.cpu0.num_store_insts 6889568 # Number of store instructions +system.cpu0.num_idle_cycles 9942379374.520096 # Number of idle cycles +system.cpu0.num_busy_cycles 497954072.479905 # Number of busy cycles +system.cpu0.not_idle_fraction 0.047695 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.952305 # Percentage of idle cycles +system.cpu0.Branches 20277624 # Number of branches fetched +system.cpu0.op_class::No_OpClass 187137 0.10% 0.10% # Class of executed instruction +system.cpu0.op_class::IntAlu 176059705 90.33% 90.42% # Class of executed instruction +system.cpu0.op_class::IntMult 119089 0.06% 90.48% # Class of executed instruction +system.cpu0.op_class::IntDiv 84733 0.04% 90.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 16 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.53% # Class of executed instruction +system.cpu0.op_class::MemRead 11572910 5.94% 96.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 6889568 3.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 194798773 # Class of executed instruction +system.cpu0.op_class::total 194913158 # Class of executed instruction system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10442335269 # number of cpu cycles simulated +system.cpu1.numCycles 10439192066 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 50519564 # Number of instructions committed -system.cpu1.committedOps 98516943 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 91922966 # Number of integer alu accesses +system.cpu1.committedInsts 50448213 # Number of instructions committed +system.cpu1.committedOps 98424201 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 91824874 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu1.num_func_calls 994306 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9151218 # number of instructions that are conditional controls -system.cpu1.num_int_insts 91922966 # number of integer instructions +system.cpu1.num_func_calls 991908 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9137643 # number of instructions that are conditional controls +system.cpu1.num_int_insts 91824874 # number of integer instructions system.cpu1.num_fp_insts 48 # number of float instructions -system.cpu1.num_int_register_reads 171998815 # number of times the integer registers were read -system.cpu1.num_int_register_writes 78483807 # number of times the integer registers were written +system.cpu1.num_int_register_reads 171791517 # number of times the integer registers were read +system.cpu1.num_int_register_writes 78447804 # number of times the integer registers were written system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 52229792 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 37031955 # number of times the CC registers were written -system.cpu1.num_mem_refs 8648347 # number of memory refs -system.cpu1.num_load_insts 5505950 # Number of load instructions -system.cpu1.num_store_insts 3142397 # Number of store instructions -system.cpu1.num_idle_cycles 10281378678.091957 # Number of idle cycles -system.cpu1.num_busy_cycles 160956590.908042 # Number of busy cycles -system.cpu1.not_idle_fraction 0.015414 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.984586 # Percentage of idle cycles -system.cpu1.Branches 10509145 # Number of branches fetched -system.cpu1.op_class::No_OpClass 118838 0.12% 0.12% # Class of executed instruction -system.cpu1.op_class::IntAlu 89646727 91.00% 91.12% # Class of executed instruction -system.cpu1.op_class::IntMult 68401 0.07% 91.19% # Class of executed instruction -system.cpu1.op_class::IntDiv 39449 0.04% 91.23% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::FloatCvt 16 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 91.23% # Class of executed instruction -system.cpu1.op_class::MemRead 5501755 5.58% 96.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 3142397 3.19% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 52143431 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 36991088 # number of times the CC registers were written +system.cpu1.num_mem_refs 8627580 # number of memory refs +system.cpu1.num_load_insts 5530314 # Number of load instructions +system.cpu1.num_store_insts 3097266 # Number of store instructions +system.cpu1.num_idle_cycles 10278680276.738028 # Number of idle cycles +system.cpu1.num_busy_cycles 160511789.261972 # Number of busy cycles +system.cpu1.not_idle_fraction 0.015376 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.984624 # Percentage of idle cycles +system.cpu1.Branches 10492962 # Number of branches fetched +system.cpu1.op_class::No_OpClass 118368 0.12% 0.12% # Class of executed instruction +system.cpu1.op_class::IntAlu 89576077 91.01% 91.13% # Class of executed instruction +system.cpu1.op_class::IntMult 66940 0.07% 91.20% # Class of executed instruction +system.cpu1.op_class::IntDiv 40064 0.04% 91.24% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::FloatCvt 16 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 91.24% # Class of executed instruction +system.cpu1.op_class::MemRead 5526131 5.61% 96.85% # Class of executed instruction +system.cpu1.op_class::MemWrite 3097266 3.15% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 98517583 # Class of executed instruction -system.iobus.trans_dist::ReadReq 883857 # Transaction distribution -system.iobus.trans_dist::ReadResp 883857 # Transaction distribution -system.iobus.trans_dist::WriteReq 36766 # Transaction distribution -system.iobus.trans_dist::WriteResp 36766 # Transaction distribution -system.iobus.trans_dist::MessageReq 1833 # Transaction distribution -system.iobus.trans_dist::MessageResp 1833 # Transaction distribution +system.cpu1.op_class::total 98424862 # Class of executed instruction +system.iobus.trans_dist::ReadReq 883871 # Transaction distribution +system.iobus.trans_dist::ReadResp 883871 # Transaction distribution +system.iobus.trans_dist::WriteReq 36792 # Transaction distribution +system.iobus.trans_dist::WriteResp 36792 # Transaction distribution +system.iobus.trans_dist::MessageReq 1835 # Transaction distribution +system.iobus.trans_dist::MessageResp 1835 # Transaction distribution system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1736 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1682 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3418 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 712 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 74 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1422 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1234 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 811270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 178 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 811278 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio 2214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1754122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1753576 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4922 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 652 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31650 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 676 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 876 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31738 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12896 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 13284 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 70 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 72 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio 92 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 87372 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1844912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 88002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1844996 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3472 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3364 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6836 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3506 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 356 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 37 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2844 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2468 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7234 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1622534 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 356 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1622550 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 360 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio 4401 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2100077 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2099537 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3180 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 326 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15825 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1752 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15869 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6642 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 140 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 144 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9237 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 52465 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2159378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 53095 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2159468 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 43000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9037000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9083500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 944500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -520,7 +521,7 @@ system.iobus.reqLayer6.occupancy 21127500 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 458718000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 1770984 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 1783484 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 31828500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -536,21 +537,21 @@ system.iobus.reqLayer15.occupancy 9500 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 410369779 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 410414499 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 7666639 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 7700146 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1751500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2482464 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2638190 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1948163500 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1947717500 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 60411500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 60917000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -563,48 +564,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 11180898 # delay histogram for all message -system.ruby.delayHist::mean 0.431734 # delay histogram for all message -system.ruby.delayHist::stdev 1.809496 # delay histogram for all message -system.ruby.delayHist | 10578004 94.61% 94.61% | 2065 0.02% 94.63% | 600258 5.37% 99.99% | 191 0.00% 100.00% | 301 0.00% 100.00% | 12 0.00% 100.00% | 64 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 11180898 # delay histogram for all message +system.ruby.delayHist::samples 11184165 # delay histogram for all message +system.ruby.delayHist::mean 0.431974 # delay histogram for all message +system.ruby.delayHist::stdev 1.810021 # delay histogram for all message +system.ruby.delayHist | 10580766 94.60% 94.60% | 2101 0.02% 94.62% | 600708 5.37% 99.99% | 188 0.00% 100.00% | 323 0.00% 100.00% | 9 0.00% 100.00% | 67 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 11184165 # delay histogram for all message system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 197955008 +system.ruby.outstanding_req_hist_seqr::samples 197976054 system.ruby.outstanding_req_hist_seqr::mean 1.000129 system.ruby.outstanding_req_hist_seqr::gmean 1.000089 -system.ruby.outstanding_req_hist_seqr::stdev 0.011356 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 197929478 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 197955008 +system.ruby.outstanding_req_hist_seqr::stdev 0.011359 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 197950506 99.99% 99.99% | 25548 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 197976054 system.ruby.latency_hist_seqr::bucket_size 128 system.ruby.latency_hist_seqr::max_bucket 1279 -system.ruby.latency_hist_seqr::samples 197955007 -system.ruby.latency_hist_seqr::mean 1.340882 -system.ruby.latency_hist_seqr::gmean 1.042158 -system.ruby.latency_hist_seqr::stdev 5.088799 -system.ruby.latency_hist_seqr | 197919440 99.98% 99.98% | 26716 0.01% 100.00% | 2921 0.00% 100.00% | 3323 0.00% 100.00% | 1640 0.00% 100.00% | 892 0.00% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00% -system.ruby.latency_hist_seqr::total 197955007 +system.ruby.latency_hist_seqr::samples 197976053 +system.ruby.latency_hist_seqr::mean 1.340875 +system.ruby.latency_hist_seqr::gmean 1.042170 +system.ruby.latency_hist_seqr::stdev 5.085216 +system.ruby.latency_hist_seqr | 197940485 99.98% 99.98% | 26707 0.01% 100.00% | 2933 0.00% 100.00% | 3350 0.00% 100.00% | 1606 0.00% 100.00% | 905 0.00% 100.00% | 4 0.00% 100.00% | 34 0.00% 100.00% | 22 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.latency_hist_seqr::total 197976053 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 195243038 +system.ruby.hit_latency_hist_seqr::samples 195263006 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 195243038 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 195243038 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 195263006 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 195263006 system.ruby.miss_latency_hist_seqr::bucket_size 128 system.ruby.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.miss_latency_hist_seqr::samples 2711969 -system.ruby.miss_latency_hist_seqr::mean 25.882013 -system.ruby.miss_latency_hist_seqr::gmean 20.371762 -system.ruby.miss_latency_hist_seqr::stdev 35.771321 -system.ruby.miss_latency_hist_seqr | 2676402 98.69% 98.69% | 26716 0.99% 99.67% | 2921 0.11% 99.78% | 3323 0.12% 99.90% | 1640 0.06% 99.96% | 892 0.03% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 2711969 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 16386626 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 1208734 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17595360 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 114457588 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 551053 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 115008641 # Number of cache demand accesses +system.ruby.miss_latency_hist_seqr::samples 2713047 +system.ruby.miss_latency_hist_seqr::mean 25.874270 +system.ruby.miss_latency_hist_seqr::gmean 20.370607 +system.ruby.miss_latency_hist_seqr::stdev 35.731774 +system.ruby.miss_latency_hist_seqr | 2677479 98.69% 98.69% | 26707 0.98% 99.67% | 2933 0.11% 99.78% | 3350 0.12% 99.90% | 1606 0.06% 99.96% | 905 0.03% 100.00% | 4 0.00% 100.00% | 34 0.00% 100.00% | 22 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 2713047 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 16414226 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 1206044 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17620270 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 114568727 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 549758 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 115118485 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -614,13 +615,13 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 14 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 7947912 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 682964 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8630876 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 56450912 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 269218 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 56720130 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 13 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 7924165 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 686474 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8610639 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 56355888 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 270771 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 56626659 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -631,605 +632,616 @@ system.ruby.l1_cntrl1.prefetcher.partial_hits 0 system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl1.fully_busy_cycles 14 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2479139 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 232830 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2711969 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 2479845 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 233202 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2713047 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.059057 -system.ruby.network.routers0.msg_count.Control::0 1759787 -system.ruby.network.routers0.msg_count.Request_Control::2 45499 -system.ruby.network.routers0.msg_count.Response_Data::1 1788765 -system.ruby.network.routers0.msg_count.Response_Control::1 1174136 -system.ruby.network.routers0.msg_count.Response_Control::2 1170507 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system.ruby.network.routers4.throttle0.link_utilization 0.000259 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 819 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 816 system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58968 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58752 system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle1.link_utilization 0.000228 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47555 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380440 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47552 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380416 system.ruby.network.routers5.throttle0.link_utilization 0 system.ruby.network.routers5.throttle1.link_utilization 0 -system.ruby.network.routers6.throttle0.link_utilization 0.081039 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 45499 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 1747107 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 1155827 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 363992 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 125791704 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 9246616 -system.ruby.network.routers6.throttle1.link_utilization 0.043776 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 41487 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 940551 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 636259 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 331896 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 67719672 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 5090072 -system.ruby.network.routers6.throttle2.link_utilization 0.061594 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2711969 -system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 208719 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 128788 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1822364 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 572036 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 494 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1169798 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21695752 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 15027768 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 1030304 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14578912 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+system.ruby.network.routers6.throttle2.link_utilization 0.061627 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2713047 +system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 208936 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 128034 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1823096 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 572153 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 500 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1169611 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21704376 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 15043392 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 1024272 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14584768 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41195016 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+system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 816 system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58968 +system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58752 system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6276167 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.731662 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.309437 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5702991 90.87% 90.87% | 569 0.01% 90.88% | 572047 9.11% 99.99% | 186 0.00% 99.99% | 295 0.00% 100.00% | 12 0.00% 100.00% | 64 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6276167 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6277907 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.731657 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.309527 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5704590 90.87% 90.87% | 579 0.01% 90.88% | 572160 9.11% 99.99% | 182 0.00% 99.99% | 317 0.01% 100.00% | 9 0.00% 100.00% | 67 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6277907 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4817745 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.048807 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.619369 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4787452 99.37% 99.37% | 575 0.01% 99.38% | 658 0.01% 99.40% | 838 0.02% 99.41% | 27971 0.58% 99.99% | 240 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% | 3 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4817745 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4818510 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.049390 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.622960 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4787836 99.36% 99.36% | 592 0.01% 99.38% | 677 0.01% 99.39% | 845 0.02% 99.41% | 28317 0.59% 99.99% | 231 0.00% 100.00% | 4 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4818510 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 86986 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000069 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.011745 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 86983 100.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 86986 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 87748 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000137 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.016538 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 87742 99.99% 99.99% | 0 0.00% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 87748 # delay histogram for vnet_2 system.ruby.LD.latency_hist_seqr::bucket_size 128 system.ruby.LD.latency_hist_seqr::max_bucket 1279 -system.ruby.LD.latency_hist_seqr::samples 15432045 -system.ruby.LD.latency_hist_seqr::mean 2.853347 -system.ruby.LD.latency_hist_seqr::gmean 1.313273 -system.ruby.LD.latency_hist_seqr::stdev 9.004183 -system.ruby.LD.latency_hist_seqr | 15417229 99.90% 99.90% | 12840 0.08% 99.99% | 810 0.01% 99.99% | 753 0.00% 100.00% | 313 0.00% 100.00% | 86 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 15432045 +system.ruby.LD.latency_hist_seqr::samples 15434919 +system.ruby.LD.latency_hist_seqr::mean 2.853771 +system.ruby.LD.latency_hist_seqr::gmean 1.313299 +system.ruby.LD.latency_hist_seqr::stdev 9.010453 +system.ruby.LD.latency_hist_seqr | 15420072 99.90% 99.90% | 12855 0.08% 99.99% | 824 0.01% 99.99% | 752 0.00% 100.00% | 311 0.00% 100.00% | 93 0.00% 100.00% | 1 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 15434919 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 13998259 +system.ruby.LD.hit_latency_hist_seqr::samples 14000797 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 13998259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 13998259 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 14000797 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 14000797 system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.miss_latency_hist_seqr::samples 1433786 -system.ruby.LD.miss_latency_hist_seqr::mean 20.947839 -system.ruby.LD.miss_latency_hist_seqr::gmean 18.787632 -system.ruby.LD.miss_latency_hist_seqr::stdev 22.620333 -system.ruby.LD.miss_latency_hist_seqr | 1418970 98.97% 98.97% | 12840 0.90% 99.86% | 810 0.06% 99.92% | 753 0.05% 99.97% | 313 0.02% 99.99% | 86 0.01% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 1433786 +system.ruby.LD.miss_latency_hist_seqr::samples 1434122 +system.ruby.LD.miss_latency_hist_seqr::mean 20.951441 +system.ruby.LD.miss_latency_hist_seqr::gmean 18.789020 +system.ruby.LD.miss_latency_hist_seqr::stdev 22.643422 +system.ruby.LD.miss_latency_hist_seqr | 1419275 98.96% 98.96% | 12855 0.90% 99.86% | 824 0.06% 99.92% | 752 0.05% 99.97% | 311 0.02% 99.99% | 93 0.01% 100.00% | 1 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 1434122 system.ruby.ST.latency_hist_seqr::bucket_size 128 system.ruby.ST.latency_hist_seqr::max_bucket 1279 -system.ruby.ST.latency_hist_seqr::samples 9612989 -system.ruby.ST.latency_hist_seqr::mean 3.237898 -system.ruby.ST.latency_hist_seqr::gmean 1.143931 -system.ruby.ST.latency_hist_seqr::stdev 17.979843 -system.ruby.ST.latency_hist_seqr | 9598427 99.85% 99.85% | 8665 0.09% 99.94% | 1602 0.02% 99.96% | 2295 0.02% 99.98% | 1192 0.01% 99.99% | 757 0.01% 100.00% | 4 0.00% 100.00% | 23 0.00% 100.00% | 18 0.00% 100.00% | 6 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 9612989 +system.ruby.ST.latency_hist_seqr::samples 9614411 +system.ruby.ST.latency_hist_seqr::mean 3.236789 +system.ruby.ST.latency_hist_seqr::gmean 1.144007 +system.ruby.ST.latency_hist_seqr::stdev 17.965589 +system.ruby.ST.latency_hist_seqr | 9599857 99.85% 99.85% | 8650 0.09% 99.94% | 1610 0.02% 99.96% | 2319 0.02% 99.98% | 1166 0.01% 99.99% | 762 0.01% 100.00% | 3 0.00% 100.00% | 22 0.00% 100.00% | 17 0.00% 100.00% | 5 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 9614411 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 9259401 +system.ruby.ST.hit_latency_hist_seqr::samples 9260487 system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9259401 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 9259401 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9260487 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 9260487 system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.miss_latency_hist_seqr::samples 353588 -system.ruby.ST.miss_latency_hist_seqr::mean 61.841694 -system.ruby.ST.miss_latency_hist_seqr::gmean 38.700068 -system.ruby.ST.miss_latency_hist_seqr::stdev 72.272561 -system.ruby.ST.miss_latency_hist_seqr | 339026 95.88% 95.88% | 8665 2.45% 98.33% | 1602 0.45% 98.79% | 2295 0.65% 99.43% | 1192 0.34% 99.77% | 757 0.21% 99.99% | 4 0.00% 99.99% | 23 0.01% 99.99% | 18 0.01% 100.00% | 6 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 353588 +system.ruby.ST.miss_latency_hist_seqr::samples 353924 +system.ruby.ST.miss_latency_hist_seqr::mean 61.762782 +system.ruby.ST.miss_latency_hist_seqr::gmean 38.656662 +system.ruby.ST.miss_latency_hist_seqr::stdev 72.192186 +system.ruby.ST.miss_latency_hist_seqr | 339370 95.89% 95.89% | 8650 2.44% 98.33% | 1610 0.45% 98.79% | 2319 0.66% 99.44% | 1166 0.33% 99.77% | 762 0.22% 99.99% | 3 0.00% 99.99% | 22 0.01% 99.99% | 17 0.00% 100.00% | 5 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 353924 system.ruby.IFETCH.latency_hist_seqr::bucket_size 128 system.ruby.IFETCH.latency_hist_seqr::max_bucket 1279 -system.ruby.IFETCH.latency_hist_seqr::samples 171728771 -system.ruby.IFETCH.latency_hist_seqr::mean 1.087728 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.013814 -system.ruby.IFETCH.latency_hist_seqr::stdev 1.877484 -system.ruby.IFETCH.latency_hist_seqr | 171723029 100.00% 100.00% | 4832 0.00% 100.00% | 479 0.00% 100.00% | 259 0.00% 100.00% | 120 0.00% 100.00% | 42 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 171728771 +system.ruby.IFETCH.latency_hist_seqr::samples 171745144 +system.ruby.IFETCH.latency_hist_seqr::mean 1.087707 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.013816 +system.ruby.IFETCH.latency_hist_seqr::stdev 1.870223 +system.ruby.IFETCH.latency_hist_seqr | 171739420 100.00% 100.00% | 4825 0.00% 100.00% | 474 0.00% 100.00% | 262 0.00% 100.00% | 112 0.00% 100.00% | 43 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 171745144 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 170908500 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 170924615 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 170908500 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 170908500 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 170924615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 170924615 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 820271 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 19.366341 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 17.675078 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 20.056386 -system.ruby.IFETCH.miss_latency_hist_seqr | 814529 99.30% 99.30% | 4832 0.59% 99.89% | 479 0.06% 99.95% | 259 0.03% 99.98% | 120 0.01% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 820271 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 820529 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 19.358062 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 17.674355 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 19.917428 +system.ruby.IFETCH.miss_latency_hist_seqr | 814805 99.30% 99.30% | 4825 0.59% 99.89% | 474 0.06% 99.95% | 262 0.03% 99.98% | 112 0.01% 99.99% | 43 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 820529 system.ruby.RMW_Read.latency_hist_seqr::bucket_size 128 system.ruby.RMW_Read.latency_hist_seqr::max_bucket 1279 -system.ruby.RMW_Read.latency_hist_seqr::samples 500824 -system.ruby.RMW_Read.latency_hist_seqr::mean 4.015135 -system.ruby.RMW_Read.latency_hist_seqr::gmean 1.504010 -system.ruby.RMW_Read.latency_hist_seqr::stdev 10.229460 -system.ruby.RMW_Read.latency_hist_seqr | 500636 99.96% 99.96% | 143 0.03% 99.99% | 19 0.00% 99.99% | 10 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist_seqr::total 500824 +system.ruby.RMW_Read.latency_hist_seqr::samples 500947 +system.ruby.RMW_Read.latency_hist_seqr::mean 4.014067 +system.ruby.RMW_Read.latency_hist_seqr::gmean 1.503920 +system.ruby.RMW_Read.latency_hist_seqr::stdev 10.213309 +system.ruby.RMW_Read.latency_hist_seqr | 500762 99.96% 99.96% | 143 0.03% 99.99% | 15 0.00% 99.99% | 11 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist_seqr::total 500947 system.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist_seqr::samples 434822 +system.ruby.RMW_Read.hit_latency_hist_seqr::samples 434941 system.ruby.RMW_Read.hit_latency_hist_seqr::mean 1 system.ruby.RMW_Read.hit_latency_hist_seqr::gmean 1 -system.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 434822 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist_seqr::total 434822 +system.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 434941 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist_seqr::total 434941 system.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist_seqr::samples 66002 -system.ruby.RMW_Read.miss_latency_hist_seqr::mean 23.878882 -system.ruby.RMW_Read.miss_latency_hist_seqr::gmean 22.130008 -system.ruby.RMW_Read.miss_latency_hist_seqr::stdev 18.427339 -system.ruby.RMW_Read.miss_latency_hist_seqr | 65814 99.72% 99.72% | 143 0.22% 99.93% | 19 0.03% 99.96% | 10 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist_seqr::total 66002 +system.ruby.RMW_Read.miss_latency_hist_seqr::samples 66006 +system.ruby.RMW_Read.miss_latency_hist_seqr::mean 23.875011 +system.ruby.RMW_Read.miss_latency_hist_seqr::gmean 22.132571 +system.ruby.RMW_Read.miss_latency_hist_seqr::stdev 18.367061 +system.ruby.RMW_Read.miss_latency_hist_seqr | 65821 99.72% 99.72% | 143 0.22% 99.94% | 15 0.02% 99.96% | 11 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist_seqr::total 66006 system.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 64 system.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 639 -system.ruby.Locked_RMW_Read.latency_hist_seqr::samples 340189 -system.ruby.Locked_RMW_Read.latency_hist_seqr::mean 3.322221 -system.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 1.405053 -system.ruby.Locked_RMW_Read.latency_hist_seqr::stdev 8.368395 -system.ruby.Locked_RMW_Read.latency_hist_seqr | 339841 99.90% 99.90% | 89 0.03% 99.92% | 235 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist_seqr::total 340189 +system.ruby.Locked_RMW_Read.latency_hist_seqr::samples 340316 +system.ruby.Locked_RMW_Read.latency_hist_seqr::mean 3.332085 +system.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 1.406714 +system.ruby.Locked_RMW_Read.latency_hist_seqr::stdev 8.468226 +system.ruby.Locked_RMW_Read.latency_hist_seqr | 339968 99.90% 99.90% | 90 0.03% 99.92% | 233 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 7 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist_seqr::total 340316 system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::samples 301867 +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::samples 301850 system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::mean 1 system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::gmean 1 -system.ruby.Locked_RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::total 301867 +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 301850 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::total 301850 system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 64 system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 639 -system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 38322 -system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 21.614634 -system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 20.468455 -system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::stdev 15.638998 -system.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 37974 99.09% 99.09% | 89 0.23% 99.32% | 235 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 38322 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 38466 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 21.632403 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 20.474141 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::stdev 16.027002 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 38118 99.10% 99.10% | 90 0.23% 99.33% | 233 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 7 0.02% 99.96% | 5 0.01% 99.98% | 1 0.00% 99.98% | 2 0.01% 99.98% | 6 0.02% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 38466 system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 340189 +system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 340316 system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 1 system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 1 -system.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist_seqr::total 340189 +system.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 340316 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist_seqr::total 340316 system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::samples 340189 +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::samples 340316 system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::mean 1 system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::gmean 1 -system.ruby.Locked_RMW_Write.hit_latency_hist_seqr | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::total 340189 -system.ruby.Directory_Controller.Fetch 181234 0.00% 0.00% -system.ruby.Directory_Controller.Data 103288 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 181708 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 147284 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 819 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr | 0 0.00% 0.00% | 340316 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::total 340316 +system.ruby.Directory_Controller.Fetch 181113 0.00% 0.00% +system.ruby.Directory_Controller.Data 102911 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 181583 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 147234 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 816 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 13460 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 181234 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 474 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 43996 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 474 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 43996 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 100203 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 345 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 2740 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 13460 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 181234 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 100203 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 345 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 345 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 2740 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 2740 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest | 819 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.ReadRequest::total 819 +system.ruby.Directory_Controller.CleanReplacement 13434 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 181113 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 470 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 44323 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 470 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 44323 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 100152 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 346 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 2413 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 13434 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 181113 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 100152 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 346 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 346 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 2413 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 2413 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest | 816 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.ReadRequest::total 816 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.WriteRequest::total 46736 -system.ruby.DMA_Controller.Data | 819 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.Data::total 819 +system.ruby.DMA_Controller.Data | 816 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.Data::total 816 system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.Ack::total 46736 -system.ruby.DMA_Controller.READY.ReadRequest | 819 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.READY.ReadRequest::total 819 +system.ruby.DMA_Controller.READY.ReadRequest | 816 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.READY.ReadRequest::total 816 system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.READY.WriteRequest::total 46736 -system.ruby.DMA_Controller.BUSY_RD.Data | 819 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.BUSY_RD.Data::total 819 +system.ruby.DMA_Controller.BUSY_RD.Data | 816 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.BUSY_RD.Data::total 816 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 10196156 66.07% 66.07% | 5235889 33.93% 100.00% -system.ruby.L1Cache_Controller.Load::total 15432045 -system.ruby.L1Cache_Controller.Ifetch | 115008645 66.97% 66.97% | 56720131 33.03% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 171728776 -system.ruby.L1Cache_Controller.Store | 7399204 68.55% 68.55% | 3394987 31.45% 100.00% -system.ruby.L1Cache_Controller.Store::total 10794191 -system.ruby.L1Cache_Controller.Inv | 18502 52.28% 52.28% | 16888 47.72% 100.00% -system.ruby.L1Cache_Controller.Inv::total 35390 -system.ruby.L1Cache_Controller.L1_Replacement | 1730128 65.23% 65.23% | 922339 34.77% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2652467 -system.ruby.L1Cache_Controller.Fwd_GETX | 12336 51.16% 51.16% | 11775 48.84% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 24111 -system.ruby.L1Cache_Controller.Fwd_GETS | 14657 53.34% 53.34% | 12824 46.66% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 27481 +system.ruby.L1Cache_Controller.Load | 10174731 65.92% 65.92% | 5260188 34.08% 100.00% +system.ruby.L1Cache_Controller.Load::total 15434919 +system.ruby.L1Cache_Controller.Ifetch | 115118489 67.03% 67.03% | 56626661 32.97% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 171745150 +system.ruby.L1Cache_Controller.Store | 7445539 68.97% 68.97% | 3350451 31.03% 100.00% +system.ruby.L1Cache_Controller.Store::total 10795990 +system.ruby.L1Cache_Controller.Inv | 18648 52.30% 52.30% | 17011 47.70% 100.00% +system.ruby.L1Cache_Controller.Inv::total 35659 +system.ruby.L1Cache_Controller.L1_Replacement | 1725795 65.05% 65.05% | 927205 34.95% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2653000 +system.ruby.L1Cache_Controller.Fwd_GETX | 12362 50.94% 50.94% | 11904 49.06% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 24266 +system.ruby.L1Cache_Controller.Fwd_GETS | 14780 53.13% 53.13% | 13039 46.87% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 27819 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 528 32.39% 32.39% | 1102 67.61% 100.00% -system.ruby.L1Cache_Controller.Data::total 1630 -system.ruby.L1Cache_Controller.Data_Exclusive | 840528 62.87% 62.87% | 496439 37.13% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1336967 -system.ruby.L1Cache_Controller.DataS_fromL1 | 12824 46.66% 46.66% | 14661 53.34% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 27485 -system.ruby.L1Cache_Controller.Data_all_Acks | 893227 67.59% 67.59% | 428349 32.41% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1321576 -system.ruby.L1Cache_Controller.Ack | 12680 52.16% 52.16% | 11631 47.84% 100.00% -system.ruby.L1Cache_Controller.Ack::total 24311 -system.ruby.L1Cache_Controller.Ack_all | 13208 50.92% 50.92% | 12733 49.08% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 25941 -system.ruby.L1Cache_Controller.WB_Ack | 1129939 64.87% 64.87% | 611895 35.13% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1741834 -system.ruby.L1Cache_Controller.NP.Load | 881498 62.40% 62.40% | 531116 37.60% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1412614 -system.ruby.L1Cache_Controller.NP.Ifetch | 550890 67.18% 67.18% | 269077 32.82% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 819967 -system.ruby.L1Cache_Controller.NP.Store | 298763 70.81% 70.81% | 123170 29.19% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 421933 -system.ruby.L1Cache_Controller.NP.Inv | 5770 62.77% 62.77% | 3422 37.23% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 9192 -system.ruby.L1Cache_Controller.I.Load | 10081 47.61% 47.61% | 11091 52.39% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 21172 -system.ruby.L1Cache_Controller.I.Ifetch | 163 53.62% 53.62% | 141 46.38% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 304 -system.ruby.L1Cache_Controller.I.Store | 5712 48.96% 48.96% | 5955 51.04% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11667 -system.ruby.L1Cache_Controller.I.L1_Replacement | 9112 53.33% 53.33% | 7975 46.67% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 17087 -system.ruby.L1Cache_Controller.S.Load | 850604 63.10% 63.10% | 497430 36.90% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1348034 -system.ruby.L1Cache_Controller.S.Ifetch | 114457588 66.97% 66.97% | 56450912 33.03% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 170908500 -system.ruby.L1Cache_Controller.S.Store | 12680 52.16% 52.16% | 11632 47.84% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 24312 -system.ruby.L1Cache_Controller.S.Inv | 12467 48.73% 48.73% | 13116 51.27% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 25583 -system.ruby.L1Cache_Controller.S.L1_Replacement | 591077 66.15% 66.15% | 302469 33.85% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 893546 -system.ruby.L1Cache_Controller.E.Load | 2398193 64.14% 64.14% | 1340570 35.86% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3738763 -system.ruby.L1Cache_Controller.E.Store | 120078 73.14% 73.14% | 44106 26.86% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 164184 -system.ruby.L1Cache_Controller.E.Inv | 72 60.00% 60.00% | 48 40.00% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 120 -system.ruby.L1Cache_Controller.E.L1_Replacement | 718924 61.46% 61.46% | 450874 38.54% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1169798 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 233 64.01% 64.01% | 131 35.99% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 364 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 999 46.02% 46.02% | 1172 53.98% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2171 -system.ruby.L1Cache_Controller.M.Load | 6055780 67.95% 67.95% | 2855682 32.05% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8911462 -system.ruby.L1Cache_Controller.M.Store | 6961971 68.44% 68.44% | 3210124 31.56% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10172095 -system.ruby.L1Cache_Controller.M.Inv | 193 39.07% 39.07% | 301 60.93% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 494 -system.ruby.L1Cache_Controller.M.L1_Replacement | 411015 71.85% 71.85% | 161021 28.15% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 572036 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 12103 50.97% 50.97% | 11644 49.03% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23747 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13658 53.96% 53.96% | 11652 46.04% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 25310 +system.ruby.L1Cache_Controller.Data | 521 31.46% 31.46% | 1135 68.54% 100.00% +system.ruby.L1Cache_Controller.Data::total 1656 +system.ruby.L1Cache_Controller.Data_Exclusive | 836671 62.58% 62.58% | 500206 37.42% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1336877 +system.ruby.L1Cache_Controller.DataS_fromL1 | 13039 46.86% 46.86% | 14784 53.14% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 27823 +system.ruby.L1Cache_Controller.Data_all_Acks | 892759 67.52% 67.52% | 429359 32.48% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1322118 +system.ruby.L1Cache_Controller.Ack | 12812 52.14% 52.14% | 11761 47.86% 100.00% +system.ruby.L1Cache_Controller.Ack::total 24573 +system.ruby.L1Cache_Controller.Ack_all | 13333 50.83% 50.83% | 12896 49.17% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 26229 +system.ruby.L1Cache_Controller.WB_Ack | 1127309 64.72% 64.72% | 614455 35.28% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1741764 +system.ruby.L1Cache_Controller.NP.Load | 877314 62.10% 62.10% | 535446 37.90% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1412760 +system.ruby.L1Cache_Controller.NP.Ifetch | 549594 67.01% 67.01% | 270630 32.99% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 820224 +system.ruby.L1Cache_Controller.NP.Store | 299910 71.06% 71.06% | 122153 28.94% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 422063 +system.ruby.L1Cache_Controller.NP.Inv | 5790 62.89% 62.89% | 3417 37.11% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 9207 +system.ruby.L1Cache_Controller.I.Load | 10201 47.75% 47.75% | 11161 52.25% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 21362 +system.ruby.L1Cache_Controller.I.Ifetch | 164 53.77% 53.77% | 141 46.23% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 305 +system.ruby.L1Cache_Controller.I.Store | 5805 49.38% 49.38% | 5950 50.62% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11755 +system.ruby.L1Cache_Controller.I.L1_Replacement | 9048 52.68% 52.68% | 8128 47.32% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17176 +system.ruby.L1Cache_Controller.S.Load | 854922 63.25% 63.25% | 496689 36.75% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1351611 +system.ruby.L1Cache_Controller.S.Ifetch | 114568727 67.03% 67.03% | 56355888 32.97% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 170924615 +system.ruby.L1Cache_Controller.S.Store | 12814 52.14% 52.14% | 11764 47.86% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 24578 +system.ruby.L1Cache_Controller.S.Inv | 12592 48.75% 48.75% | 13236 51.25% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 25828 +system.ruby.L1Cache_Controller.S.L1_Replacement | 589438 65.93% 65.93% | 304622 34.07% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 894060 +system.ruby.L1Cache_Controller.E.Load | 2373511 63.51% 63.51% | 1363700 36.49% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3737211 +system.ruby.L1Cache_Controller.E.Store | 119848 72.96% 72.96% | 44409 27.04% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 164257 +system.ruby.L1Cache_Controller.E.Inv | 68 57.63% 57.63% | 50 42.37% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 118 +system.ruby.L1Cache_Controller.E.L1_Replacement | 715361 61.16% 61.16% | 454250 38.84% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1169611 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 230 60.05% 60.05% | 153 39.95% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 383 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 951 42.97% 42.97% | 1262 57.03% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2213 +system.ruby.L1Cache_Controller.M.Load | 6058783 67.98% 67.98% | 2853192 32.02% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8911975 +system.ruby.L1Cache_Controller.M.Store | 7007162 68.88% 68.88% | 3166175 31.12% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10173337 +system.ruby.L1Cache_Controller.M.Inv | 195 39.00% 39.00% | 305 61.00% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 500 +system.ruby.L1Cache_Controller.M.L1_Replacement | 411948 72.00% 72.00% | 160205 28.00% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 572153 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 12132 50.80% 50.80% | 11750 49.20% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23882 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13829 54.01% 54.01% | 11777 45.99% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 25606 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 840528 62.87% 62.87% | 496439 37.13% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1336967 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 12824 46.66% 46.66% | 14661 53.34% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 27485 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 589280 66.24% 66.24% | 300325 33.76% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 889605 -system.ruby.L1Cache_Controller.IM.Data | 528 32.39% 32.39% | 1102 67.61% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1630 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 303947 70.36% 70.36% | 128024 29.64% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431971 -system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.L1Cache_Controller.SM.Inv::total 1 -system.ruby.L1Cache_Controller.SM.Ack | 12680 52.16% 52.16% | 11631 47.84% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 24311 -system.ruby.L1Cache_Controller.SM.Ack_all | 13208 50.92% 50.92% | 12733 49.08% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 25941 -system.ruby.L1Cache_Controller.M_I.Ifetch | 4 80.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.M_I.Ifetch::total 5 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 1129939 64.87% 64.87% | 611895 35.13% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1741834 -system.ruby.L2Cache_Controller.L1_GET_INSTR 820271 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1434178 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 433604 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 24312 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1741834 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 100151 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 13512 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 181234 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 116748 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 25808 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2171 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1865 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7090 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 27485 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1794879 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 6170 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15428 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 32321 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 133485 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 804813 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 69338 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1923 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 24311 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 291 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6674 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Inv | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS.Inv::total 1 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 836671 62.58% 62.58% | 500206 37.42% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1336877 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 13038 46.86% 46.86% | 14784 53.14% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 27822 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 587563 66.02% 66.02% | 302388 33.98% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 889951 +system.ruby.L1Cache_Controller.IM.Data | 521 31.46% 31.46% | 1135 68.54% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1656 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 305196 70.62% 70.62% | 126971 29.38% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 432167 +system.ruby.L1Cache_Controller.SM.Inv | 2 40.00% 40.00% | 3 60.00% 100.00% +system.ruby.L1Cache_Controller.SM.Inv::total 5 +system.ruby.L1Cache_Controller.SM.Ack | 12812 52.14% 52.14% | 11761 47.86% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 24573 +system.ruby.L1Cache_Controller.SM.Ack_all | 13333 50.83% 50.83% | 12896 49.17% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 26229 +system.ruby.L1Cache_Controller.IS_I.DataS_fromL1 | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_I.DataS_fromL1::total 1 +system.ruby.L1Cache_Controller.M_I.Ifetch | 4 66.67% 66.67% | 2 33.33% 100.00% +system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 +system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 1127309 64.72% 64.72% | 614454 35.28% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1741763 +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 1 +system.ruby.L2Cache_Controller.L1_GET_INSTR 820529 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1434524 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 433826 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 24578 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1741764 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 1 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 100099 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 13487 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 181113 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 116345 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 26110 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2213 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1845 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7085 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 27823 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1795273 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 5518 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15422 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 32337 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 133354 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 805077 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 69426 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1949 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 24573 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 290 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6672 0.00% 0.00% system.ruby.L2Cache_Controller.SS.MEM_Inv 5 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1304646 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 274082 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 99609 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6704 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 2851 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1304540 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 274254 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 99553 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6682 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 2525 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 27481 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 24111 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1741834 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 251 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 134 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 27819 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 24266 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1741763 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX_old 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 256 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 133 0.00% 0.00% system.ruby.L2Cache_Controller.MT.MEM_Inv 229 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 116748 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 2851 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 442 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 116345 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 2525 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 447 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.Ack_all 38 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.MEM_Inv 229 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 52 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 82 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1570 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 6674 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 295 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 296 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 53 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 80 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1551 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 6672 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 294 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 295 0.00% 0.00% system.ruby.L2Cache_Controller.S_I.MEM_Inv 5 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 32321 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 15428 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 133485 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 233 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 32337 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 15422 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 133354 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 237 0.00% 0.00% system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 26234 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 159 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 5 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 26522 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 165 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1768645 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 25308 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2170 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 6 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1768751 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 25603 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2212 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 8 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 7 0.00% 0.00% system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 27478 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 27815 0.00% 0.00% ---------- End Simulation Statistics ---------- |