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-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/EMPTY0
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini1990
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json2677
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr87
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout10
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt1925
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal141
7 files changed, 0 insertions, 6830 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/EMPTY b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/EMPTY
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/EMPTY
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
deleted file mode 100644
index bf97d6d87..000000000
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ /dev/null
@@ -1,1990 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus voltage_domain
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-cache_line_size=64
-clk_domain=system.clk_domain
-e820_table=system.e820_table
-eventq_index=0
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
-kernel_addr_check=true
-load_addr_mask=18446744073709551615
-load_offset=0
-mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-eventq_index=0
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-eventq_index=0
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.apicbridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-master=system.membus.slave[0]
-slave=system.iobus.master[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=apic_clk_domain dcache dtb icache interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu0.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu0.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.membus.slave[3]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu0.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu0.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.toL2Bus.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dtb isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=
-isa=system.cpu1.isa
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=true
-system=system
-tracer=system.cpu1.tracer
-workload=
-
-[system.cpu1.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-
-[system.cpu1.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu1.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu2]
-type=DerivO3CPU
-children=branchPred dtb fuPool isa itb tracer
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu2.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu2.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu2.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=
-isa=system.cpu2.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu2.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=true
-numIQEntries=64
-numPhysCCRegs=1280
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=true
-system=system
-tracer=system.cpu2.tracer
-trapLatency=13
-wbWidth=8
-workload=
-
-[system.cpu2.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-
-[system.cpu2.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu2.dtb.walker
-
-[system.cpu2.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-
-[system.cpu2.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
-eventq_index=0
-
-[system.cpu2.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu2.fuPool.FUList0.opList
-
-[system.cpu2.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
-
-[system.cpu2.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu2.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=1
-pipelined=false
-
-[system.cpu2.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
-
-[system.cpu2.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu2.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu2.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu2.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
-
-[system.cpu2.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu2.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu2.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu2.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu2.fuPool.FUList4.opList
-
-[system.cpu2.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
-
-[system.cpu2.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu2.fuPool.FUList6.opList
-
-[system.cpu2.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
-
-[system.cpu2.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu2.fuPool.FUList8.opList
-
-[system.cpu2.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu2.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu2.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu2.itb.walker
-
-[system.cpu2.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-
-[system.cpu2.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1 entries2 entries3 entries4
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
-eventq_index=0
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-eventq_index=0
-range_type=1
-size=654336
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=654336
-eventq_index=0
-range_type=2
-size=394240
-
-[system.e820_table.entries2]
-type=X86E820Entry
-addr=1048576
-eventq_index=0
-range_type=1
-size=133169152
-
-[system.e820_table.entries3]
-type=X86E820Entry
-addr=134217728
-eventq_index=0
-range_type=2
-size=3087007744
-
-[system.e820_table.entries4]
-type=X86E820Entry
-addr=4294901760
-eventq_index=0
-range_type=2
-size=65536
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-eventq_index=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-eventq_index=0
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-eventq_index=0
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-eventq_index=0
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=PCI
-eventq_index=0
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=ISA
-eventq_index=0
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=1
-eventq_index=0
-parent_bus=0
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=false
-width=16
-default=system.pc.pci_host.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[18]
-mem_side=system.membus.slave[4]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.physmem.port
-slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu0.interrupts.int_master system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854776824
-pio_latency=100000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.master[13]
-
-[system.pc.com_1.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.pc.fake_com_3]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.pc.fake_com_4]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.pc.fake_floppy]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=100000
-pio_size=2
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.pc.i_dont_exist1]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.pc.i_dont_exist2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776045
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.pc.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=13835058055282163712
-conf_device_bits=8
-conf_size=16777216
-eventq_index=0
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=9223372036854775808
-platform=system.pc
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-eventq_index=0
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=100000
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.master[1]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.dma1]
-type=I8237
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854775808
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=9223372036854775808
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-eventq_index=0
-host=system.pc.pci_host
-io_shift=0
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=30000
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[3]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/work/gem5/dist/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-clk_domain=system.clk_domain
-eventq_index=0
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=100000
-system=system
-int_master=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-clk_domain=system.clk_domain
-command_port=9223372036854775908
-data_port=9223372036854775904
-eventq_index=0
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=100000
-system=system
-pio=system.iobus.master[4]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=100000
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.master[5]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=100000
-slave=Null
-system=system
-pio=system.iobus.master[6]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=100000
-system=system
-pio=system.iobus.master[7]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-clk_domain=system.clk_domain
-eventq_index=0
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=100000
-system=system
-pio=system.iobus.master[8]
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[3]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-eventq_index=0
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-eventq_index=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
deleted file mode 100644
index aed66fce8..000000000
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
+++ /dev/null
@@ -1,2677 +0,0 @@
-{
- "name": null,
- "sim_quantum": 0,
- "system": {
- "kernel": "/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9",
- "mmap_using_noreserve": false,
- "kernel_addr_check": true,
- "bridge": {
- "ranges": [
- "3221225472:4294901760",
- "9223372036854775808:11529215046068469759",
- "13835058055282163712:18446744073709551615"
- ],
- "slave": {
- "peer": "system.membus.master[0]",
- "role": "SLAVE"
- },
- "name": "bridge",
- "req_size": 16,
- "clk_domain": "system.clk_domain",
- "delay": 50000,
- "eventq_index": 0,
- "master": {
- "peer": "system.iobus.slave[0]",
- "role": "MASTER"
- },
- "cxx_class": "Bridge",
- "path": "system.bridge",
- "resp_size": 16,
- "type": "Bridge"
- },
- "iobus": {
- "slave": {
- "peer": [
- "system.bridge.master",
- "system.pc.south_bridge.ide.dma",
- "system.pc.south_bridge.io_apic.int_master"
- ],
- "role": "SLAVE"
- },
- "name": "iobus",
- "default": {
- "peer": "system.pc.pci_host.pio",
- "role": "MASTER"
- },
- "forward_latency": 1,
- "clk_domain": "system.clk_domain",
- "width": 16,
- "eventq_index": 0,
- "master": {
- "peer": [
- "system.apicbridge.slave",
- "system.pc.south_bridge.cmos.pio",
- "system.pc.south_bridge.dma1.pio",
- "system.pc.south_bridge.ide.pio",
- "system.pc.south_bridge.keyboard.pio",
- "system.pc.south_bridge.pic1.pio",
- "system.pc.south_bridge.pic2.pio",
- "system.pc.south_bridge.pit.pio",
- "system.pc.south_bridge.speaker.pio",
- "system.pc.south_bridge.io_apic.pio",
- "system.pc.i_dont_exist1.pio",
- "system.pc.i_dont_exist2.pio",
- "system.pc.behind_pci.pio",
- "system.pc.com_1.pio",
- "system.pc.fake_com_2.pio",
- "system.pc.fake_com_3.pio",
- "system.pc.fake_com_4.pio",
- "system.pc.fake_floppy.pio",
- "system.iocache.cpu_side"
- ],
- "role": "MASTER"
- },
- "response_latency": 2,
- "cxx_class": "NoncoherentXBar",
- "path": "system.iobus",
- "type": "NoncoherentXBar",
- "use_default_range": false,
- "frontend_latency": 2
- },
- "apicbridge": {
- "ranges": [
- "11529215046068469760:11529215046068473855"
- ],
- "slave": {
- "peer": "system.iobus.master[0]",
- "role": "SLAVE"
- },
- "name": "apicbridge",
- "req_size": 16,
- "clk_domain": "system.clk_domain",
- "delay": 50000,
- "eventq_index": 0,
- "master": {
- "peer": "system.membus.slave[0]",
- "role": "MASTER"
- },
- "cxx_class": "Bridge",
- "path": "system.apicbridge",
- "resp_size": 16,
- "type": "Bridge"
- },
- "symbolfile": "",
- "l2c": {
- "cpu_side": {
- "peer": "system.toL2Bus.master[0]",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "clk_domain": "system.cpu_clk_domain",
- "write_buffers": 8,
- "response_latency": 20,
- "cxx_class": "Cache",
- "size": 4194304,
- "tags": {
- "name": "tags",
- "eventq_index": 0,
- "hit_latency": 20,
- "clk_domain": "system.cpu_clk_domain",
- "sequential_access": false,
- "assoc": 8,
- "cxx_class": "LRU",
- "path": "system.l2c.tags",
- "block_size": 64,
- "type": "LRU",
- "size": 4194304
- },
- "system": "system",
- "max_miss_count": 0,
- "eventq_index": 0,
- "mem_side": {
- "peer": "system.membus.slave[2]",
- "role": "MASTER"
- },
- "type": "Cache",
- "forward_snoops": true,
- "writeback_clean": false,
- "hit_latency": 20,
- "tgts_per_mshr": 12,
- "demand_mshr_reserve": 1,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": false,
- "prefetch_on_access": false,
- "path": "system.l2c",
- "name": "l2c",
- "mshrs": 20,
- "sequential_access": false,
- "assoc": 8
- },
- "readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh",
- "intel_mp_table": {
- "oem_table_addr": 0,
- "name": "intel_mp_table",
- "ext_entries": [
- {
- "parent_bus": 0,
- "name": "ext_entries",
- "type": "X86IntelMPBusHierarchy",
- "subtractive_decode": true,
- "eventq_index": 0,
- "cxx_class": "X86ISA::IntelMP::BusHierarchy",
- "path": "system.intel_mp_table.ext_entries",
- "bus_id": 1
- }
- ],
- "oem_id": "",
- "eventq_index": 0,
- "spec_rev": 4,
- "base_entries": [
- {
- "enable": true,
- "local_apic_version": 20,
- "name": "base_entries00",
- "family": 0,
- "local_apic_id": 0,
- "bootstrap": true,
- "feature_flags": 0,
- "eventq_index": 0,
- "stepping": 0,
- "cxx_class": "X86ISA::IntelMP::Processor",
- "path": "system.intel_mp_table.base_entries00",
- "model": 0,
- "type": "X86IntelMPProcessor"
- },
- {
- "enable": true,
- "name": "base_entries01",
- "cxx_class": "X86ISA::IntelMP::IOAPIC",
- "version": 17,
- "eventq_index": 0,
- "address": 4273995776,
- "path": "system.intel_mp_table.base_entries01",
- "type": "X86IntelMPIOAPIC",
- "id": 1
- },
- {
- "bus_type": "PCI",
- "name": "base_entries02",
- "type": "X86IntelMPBus",
- "eventq_index": 0,
- "cxx_class": "X86ISA::IntelMP::Bus",
- "path": "system.intel_mp_table.base_entries02",
- "bus_id": 0
- },
- {
- "bus_type": "ISA",
- "name": "base_entries03",
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- "opLat": 1,
- "name": "opList06",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList06",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdMultAcc",
- "opLat": 1,
- "name": "opList07",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList07",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdShift",
- "opLat": 1,
- "name": "opList08",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList08",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdShiftAcc",
- "opLat": 1,
- "name": "opList09",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList09",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdSqrt",
- "opLat": 1,
- "name": "opList10",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList10",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdFloatAdd",
- "opLat": 1,
- "name": "opList11",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList11",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdFloatAlu",
- "opLat": 1,
- "name": "opList12",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList12",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdFloatCmp",
- "opLat": 1,
- "name": "opList13",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList13",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdFloatCvt",
- "opLat": 1,
- "name": "opList14",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList14",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdFloatDiv",
- "opLat": 1,
- "name": "opList15",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList15",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdFloatMisc",
- "opLat": 1,
- "name": "opList16",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList16",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdFloatMult",
- "opLat": 1,
- "name": "opList17",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList17",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdFloatMultAcc",
- "opLat": 1,
- "name": "opList18",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList18",
- "type": "OpDesc"
- },
- {
- "opClass": "SimdFloatSqrt",
- "opLat": 1,
- "name": "opList19",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList5.opList19",
- "type": "OpDesc"
- }
- ],
- "name": "FUList5",
- "eventq_index": 0,
- "cxx_class": "FUDesc",
- "path": "system.cpu2.fuPool.FUList5",
- "type": "FUDesc"
- },
- {
- "count": 0,
- "opList": [
- {
- "opClass": "MemWrite",
- "opLat": 1,
- "name": "opList",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList6.opList",
- "type": "OpDesc"
- }
- ],
- "name": "FUList6",
- "eventq_index": 0,
- "cxx_class": "FUDesc",
- "path": "system.cpu2.fuPool.FUList6",
- "type": "FUDesc"
- },
- {
- "count": 4,
- "opList": [
- {
- "opClass": "MemRead",
- "opLat": 1,
- "name": "opList0",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList7.opList0",
- "type": "OpDesc"
- },
- {
- "opClass": "MemWrite",
- "opLat": 1,
- "name": "opList1",
- "pipelined": true,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList7.opList1",
- "type": "OpDesc"
- }
- ],
- "name": "FUList7",
- "eventq_index": 0,
- "cxx_class": "FUDesc",
- "path": "system.cpu2.fuPool.FUList7",
- "type": "FUDesc"
- },
- {
- "count": 1,
- "opList": [
- {
- "opClass": "IprAccess",
- "opLat": 3,
- "name": "opList",
- "pipelined": false,
- "eventq_index": 0,
- "cxx_class": "OpDesc",
- "path": "system.cpu2.fuPool.FUList8.opList",
- "type": "OpDesc"
- }
- ],
- "name": "FUList8",
- "eventq_index": 0,
- "cxx_class": "FUDesc",
- "path": "system.cpu2.fuPool.FUList8",
- "type": "FUDesc"
- }
- ],
- "eventq_index": 0,
- "cxx_class": "FUPool",
- "path": "system.cpu2.fuPool",
- "type": "FUPool"
- },
- "socket_id": 0,
- "renameToFetchDelay": 1,
- "path": "system.cpu2",
- "numRobs": 1,
- "switched_out": true,
- "smtLSQPolicy": "Partitioned",
- "fetchBufferSize": 64,
- "simpoint_start_insts": [],
- "max_insts_any_thread": 0,
- "smtROBThreshold": 100,
- "numIQEntries": 64,
- "branchPred": {
- "choiceCtrBits": 2,
- "name": "branchPred",
- "globalCtrBits": 2,
- "numThreads": 1,
- "localHistoryTableSize": 2048,
- "choicePredictorSize": 8192,
- "instShiftAmt": 2,
- "localCtrBits": 2,
- "eventq_index": 0,
- "BTBTagSize": 16,
- "BTBEntries": 4096,
- "cxx_class": "TournamentBP",
- "path": "system.cpu2.branchPred",
- "localPredictorSize": 2048,
- "type": "TournamentBP",
- "RASSize": 16,
- "globalPredictorSize": 8192
- },
- "LFSTSize": 1024,
- "isa": [
- {
- "eventq_index": 0,
- "path": "system.cpu2.isa",
- "type": "X86ISA",
- "name": "isa",
- "cxx_class": "X86ISA::ISA"
- }
- ],
- "smtROBPolicy": "Partitioned",
- "iewToFetchDelay": 1,
- "do_statistics_insts": true,
- "dispatchWidth": 8,
- "commitToDecodeDelay": 1,
- "smtIQPolicy": "Partitioned",
- "issueWidth": 8,
- "LSQCheckLoads": true,
- "commitToRenameDelay": 1,
- "cachePorts": 200,
- "system": "system",
- "checker": null,
- "numPhysFloatRegs": 256,
- "eventq_index": 0,
- "type": "DerivO3CPU",
- "wbWidth": 8,
- "interrupts": [],
- "smtCommitPolicy": "RoundRobin",
- "issueToExecuteDelay": 1,
- "dtb": {
- "name": "dtb",
- "eventq_index": 0,
- "cxx_class": "X86ISA::TLB",
- "walker": {
- "name": "walker",
- "clk_domain": "system.cpu_clk_domain",
- "system": "system",
- "eventq_index": 0,
- "cxx_class": "X86ISA::Walker",
- "path": "system.cpu2.dtb.walker",
- "type": "X86PagetableWalker",
- "num_squash_per_cycle": 4
- },
- "path": "system.cpu2.dtb",
- "type": "X86TLB",
- "size": 64
- },
- "numROBEntries": 192,
- "fetchQueueSize": 32,
- "iewToCommitDelay": 1,
- "smtNumFetchingThreads": 1,
- "forwardComSize": 5,
- "do_checkpoint_insts": true,
- "cxx_class": "DerivO3CPU",
- "commitToIEWDelay": 1,
- "commitWidth": 8,
- "clk_domain": "system.cpu_clk_domain",
- "function_trace_start": 0,
- "smtFetchPolicy": "SingleThread",
- "profile": 0,
- "LSQDepCheckShift": 4,
- "trapLatency": 13,
- "iewToDecodeDelay": 1,
- "numPhysCCRegs": 1280,
- "renameToIEWDelay": 2,
- "progress_interval": 0,
- "LQEntries": 32
- }
- ],
- "intrctrl": {
- "name": "intrctrl",
- "sys": "system",
- "eventq_index": 0,
- "cxx_class": "IntrControl",
- "path": "system.intrctrl",
- "type": "IntrControl"
- },
- "multi_thread": false,
- "work_begin_ckpt_count": 0,
- "work_begin_cpu_id_exit": -1,
- "work_item_id": -1,
- "num_work_ids": 16
- },
- "time_sync_period": 100000000000,
- "eventq_index": 0,
- "time_sync_spin_threshold": 100000000,
- "cxx_class": "Root",
- "path": "root",
- "time_sync_enable": false,
- "type": "Root",
- "full_system": true
-} \ No newline at end of file
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
deleted file mode 100755
index 30a665fe2..000000000
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
+++ /dev/null
@@ -1,87 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Reading current count from inactive timer.
-warn: Don't know what interrupt to clear for console.
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: x86 cpuid: unknown family 0x8086
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9400, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6996, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12287, Bank: 1
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7603, Bank: 3
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10369, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9709, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7701, Bank: 2
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11369, Bank: 1
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: Tried to clear PCI interrupt 14
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8909, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6789, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8215, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8557, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11226, Bank: 4
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7944, Bank: 0
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
deleted file mode 100755
index 73370e2b3..000000000
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
+++ /dev/null
@@ -1,10 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Dec 4 2015 15:10:31
-gem5 started Dec 4 2015 16:03:32
-gem5 executing on e104799-lin, pid 2775
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
-
-Global frequency set at 1000000000000 ticks per second
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
deleted file mode 100644
index 70169df1b..000000000
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ /dev/null
@@ -1,1925 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 5.142303 # Number of seconds simulated
-sim_ticks 5142302696000 # Number of ticks simulated
-final_tick 5142302696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 292534 # Simulator instruction rate (inst/s)
-host_op_rate 581577 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6171937350 # Simulator tick rate (ticks/s)
-host_mem_usage 967756 # Number of bytes of host memory used
-host_seconds 833.17 # Real time elapsed on the host
-sim_insts 243732330 # Number of instructions simulated
-sim_ops 484555405 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 495360 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5776768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 125248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2074112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 3968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 322688 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2420672 # Number of bytes read from this memory
-system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11247552 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 495360 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 125248 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 322688 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 943296 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9049984 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9049984 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7740 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 90262 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1957 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 32408 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 62 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 5042 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 37823 # Number of read requests responded to by this memory
-system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 175743 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 141406 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 141406 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 96330 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1123382 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 24356 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 403343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 772 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 62752 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 470737 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5513 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2187260 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 96330 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 24356 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 62752 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 183438 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1759909 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1759909 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1759909 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 96330 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1123382 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 24356 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 403343 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 772 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 62752 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 470737 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5513 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3947169 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 77737 # Number of read requests accepted
-system.physmem.writeReqs 69857 # Number of write requests accepted
-system.physmem.readBursts 77737 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 69857 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 4969408 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 5760 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4469312 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 4975168 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 4470848 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 4738 # Per bank write bursts
-system.physmem.perBankRdBursts::1 4587 # Per bank write bursts
-system.physmem.perBankRdBursts::2 5683 # Per bank write bursts
-system.physmem.perBankRdBursts::3 5272 # Per bank write bursts
-system.physmem.perBankRdBursts::4 4460 # Per bank write bursts
-system.physmem.perBankRdBursts::5 4242 # Per bank write bursts
-system.physmem.perBankRdBursts::6 4391 # Per bank write bursts
-system.physmem.perBankRdBursts::7 4725 # Per bank write bursts
-system.physmem.perBankRdBursts::8 4783 # Per bank write bursts
-system.physmem.perBankRdBursts::9 4859 # Per bank write bursts
-system.physmem.perBankRdBursts::10 4723 # Per bank write bursts
-system.physmem.perBankRdBursts::11 4859 # Per bank write bursts
-system.physmem.perBankRdBursts::12 4897 # Per bank write bursts
-system.physmem.perBankRdBursts::13 5764 # Per bank write bursts
-system.physmem.perBankRdBursts::14 5025 # Per bank write bursts
-system.physmem.perBankRdBursts::15 4639 # Per bank write bursts
-system.physmem.perBankWrBursts::0 4788 # Per bank write bursts
-system.physmem.perBankWrBursts::1 4346 # Per bank write bursts
-system.physmem.perBankWrBursts::2 4813 # Per bank write bursts
-system.physmem.perBankWrBursts::3 4456 # Per bank write bursts
-system.physmem.perBankWrBursts::4 4399 # Per bank write bursts
-system.physmem.perBankWrBursts::5 4368 # Per bank write bursts
-system.physmem.perBankWrBursts::6 4481 # Per bank write bursts
-system.physmem.perBankWrBursts::7 4596 # Per bank write bursts
-system.physmem.perBankWrBursts::8 3541 # Per bank write bursts
-system.physmem.perBankWrBursts::9 3660 # Per bank write bursts
-system.physmem.perBankWrBursts::10 3623 # Per bank write bursts
-system.physmem.perBankWrBursts::11 4308 # Per bank write bursts
-system.physmem.perBankWrBursts::12 4463 # Per bank write bursts
-system.physmem.perBankWrBursts::13 5017 # Per bank write bursts
-system.physmem.perBankWrBursts::14 4599 # Per bank write bursts
-system.physmem.perBankWrBursts::15 4375 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 5141302561000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 77737 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 69857 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 73816 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 3057 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 363 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 113 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 36 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 31 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 33 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 55 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1288 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2083 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 3603 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3481 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3524 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 3460 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 3947 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4206 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4307 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 4204 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 4830 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5601 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4215 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 3967 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 3931 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 3499 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 3423 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 3455 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 163 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 121 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 84 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 87 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 94 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 74 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 93 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 78 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 91 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 49 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 68 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 56 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 42 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 31 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 36 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 34726 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 271.798192 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 162.605386 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 302.611478 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 14316 41.23% 41.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 8644 24.89% 66.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 3494 10.06% 76.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 1847 5.32% 81.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1254 3.61% 85.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 948 2.73% 87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 605 1.74% 89.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 474 1.36% 90.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 3144 9.05% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 34726 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 3354 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 23.146989 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 204.184053 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511 3351 99.91% 99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5632-6143 1 0.03% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3354 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 3354 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.820811 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.786469 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.927460 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 11 0.33% 0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 7 0.21% 0.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 8 0.24% 0.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 2796 83.36% 84.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 40 1.19% 85.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 43 1.28% 86.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 85 2.53% 89.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 115 3.43% 92.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 62 1.85% 94.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 12 0.36% 94.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 6 0.18% 94.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 11 0.33% 95.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 4 0.12% 95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 2 0.06% 95.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 2 0.06% 95.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 122 3.64% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 2 0.06% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 1 0.03% 99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 2 0.06% 99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 3 0.09% 99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.03% 99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.03% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.03% 99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.03% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.03% 99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 8 0.24% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.03% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 1 0.03% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.03% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.03% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 1 0.03% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 2 0.06% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3354 # Writes before turning the bus around for reads
-system.physmem.totQLat 822128507 # Total ticks spent queuing
-system.physmem.totMemAccLat 2278009757 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 388235000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10588.03 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29338.03 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 0.97 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.87 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.87 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.01 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 3.53 # Average write queue length when enqueuing
-system.physmem.readRowHits 61504 # Number of row buffer hits during reads
-system.physmem.writeRowHits 51248 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.21 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.36 # Row buffer hit rate for writes
-system.physmem.avgGap 34834089.20 # Average gap between requests
-system.physmem.pageHitRate 76.44 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 129729600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 70607625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 297164400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 234880560 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 250511061840 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 94606706745 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2237443433250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 2583293584020 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.968853 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 3690534116962 # Time in different power states
-system.physmem_0.memoryStateTime::REF 128073140000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 17232140788 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 132798960 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 72319500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 308451000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 217637280 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 250511061840 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 94562869185 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2235084583500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 2580889721265 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.037449 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 3690605945988 # Time in different power states
-system.physmem_1.memoryStateTime::REF 128073140000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 17153124512 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 902046715 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.committedInsts 73959427 # Number of instructions committed
-system.cpu0.committedOps 150307597 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 138246700 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 1066960 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 14495182 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 138246700 # number of integer instructions
-system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 254560897 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 118518911 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 85690938 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 57098279 # number of times the CC registers were written
-system.cpu0.num_mem_refs 14889374 # number of memory refs
-system.cpu0.num_load_insts 10848208 # Number of load instructions
-system.cpu0.num_store_insts 4041166 # Number of store instructions
-system.cpu0.num_idle_cycles 853760386.040518 # Number of idle cycles
-system.cpu0.num_busy_cycles 48286328.959482 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.053530 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.946470 # Percentage of idle cycles
-system.cpu0.Branches 15948833 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 97349 0.06% 0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu 135200596 89.95% 90.01% # Class of executed instruction
-system.cpu0.op_class::IntMult 70034 0.05% 90.06% # Class of executed instruction
-system.cpu0.op_class::IntDiv 52579 0.03% 90.10% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.10% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.10% # Class of executed instruction
-system.cpu0.op_class::MemRead 10846498 7.22% 97.31% # Class of executed instruction
-system.cpu0.op_class::MemWrite 4041166 2.69% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 150308222 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 1651251 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.996861 # Cycle average of tags in use
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-system.cpu0.dcache.tags.sampled_refs 1651763 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 12.382417 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 417.977148 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 68.931894 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 25.087819 # Average occupied blocks per requestor
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-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
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-system.cpu0.dcache.demand_miss_latency::total 18450114431 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.overall_miss_latency::total 18450114431 # number of overall miss cycles
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-system.cpu0.dcache.overall_avg_miss_latency::total 9161.048966 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 149019 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 19247 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.742453 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 1557863 # number of writebacks
-system.cpu0.dcache.writebacks::total 1557863 # number of writebacks
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-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 369355 # number of ReadReq MSHR uncacheable
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14178.730205 # average SoftPFReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17207.810520 # average overall mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16324.601428 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17217.241591 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174549.974995 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 171860.939463 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173142.048977 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171846.801987 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 168350.926203 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170012.046896 # average overall mshr uncacheable latency
-system.cpu0.icache.tags.replacements 956706 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.794700 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 133067935 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 957218 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 139.015287 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 150766905000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 303.387688 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.665696 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 141.741316 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.592554 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.128253 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.276839 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.997646 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 135039924 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 135039924 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 90259731 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 39032907 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 3775297 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 133067935 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 90259731 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 39032907 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 3775297 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 133067935 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 90259731 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 39032907 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 3775297 # number of overall hits
-system.cpu0.icache.overall_hits::total 133067935 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 368418 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 164616 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 481723 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1014757 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 368418 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 164616 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 481723 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1014757 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 368418 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 164616 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 481723 # number of overall misses
-system.cpu0.icache.overall_misses::total 1014757 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2280778000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6376139484 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 8656917484 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 2280778000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 6376139484 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 8656917484 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 2280778000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 6376139484 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 8656917484 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 90628149 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 39197523 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 4257020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 134082692 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 90628149 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 39197523 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 4257020 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 134082692 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 90628149 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 39197523 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 4257020 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 134082692 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004065 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004200 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.113160 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.007568 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004065 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004200 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.113160 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.007568 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004065 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004200 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.113160 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.007568 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13855.141663 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13236.111799 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 8531.025146 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13855.141663 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13236.111799 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 8531.025146 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13855.141663 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13236.111799 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 8531.025146 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 3656 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 267 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.692884 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 956706 # number of writebacks
-system.cpu0.icache.writebacks::total 956706 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 57525 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 57525 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 57525 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 57525 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 57525 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 57525 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 164616 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 424198 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 588814 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 164616 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 424198 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 588814 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 164616 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 424198 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 588814 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2116162000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5491871486 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 7608033486 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2116162000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5491871486 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 7608033486 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2116162000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5491871486 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 7608033486 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004200 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.099647 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004391 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004200 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.099647 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.004391 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004200 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.099647 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.004391 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12855.141663 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12946.481327 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12920.945300 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12855.141663 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12946.481327 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12920.945300 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12855.141663 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12946.481327 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12920.945300 # average overall mshr miss latency
-system.cpu1.numCycles 2608017339 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.committedInsts 35627427 # Number of instructions committed
-system.cpu1.committedOps 68998423 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 64051827 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 468203 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 6587290 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 64051827 # number of integer instructions
-system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 118624529 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 55196381 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 36419223 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 27076219 # number of times the CC registers were written
-system.cpu1.num_mem_refs 4628508 # number of memory refs
-system.cpu1.num_load_insts 2883555 # Number of load instructions
-system.cpu1.num_store_insts 1744953 # Number of store instructions
-system.cpu1.num_idle_cycles 2479194289.218051 # Number of idle cycles
-system.cpu1.num_busy_cycles 128823049.781949 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.049395 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.950605 # Percentage of idle cycles
-system.cpu1.Branches 7222524 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 27694 0.04% 0.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu 64285165 93.17% 93.21% # Class of executed instruction
-system.cpu1.op_class::IntMult 28263 0.04% 93.25% # Class of executed instruction
-system.cpu1.op_class::IntDiv 29212 0.04% 93.29% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.29% # Class of executed instruction
-system.cpu1.op_class::MemRead 2883455 4.18% 97.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1744953 2.53% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 68998742 # Class of executed instruction
-system.cpu2.branchPred.lookups 31199361 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 31199361 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 851763 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 30042490 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 0 # Number of BTB hits
-system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 863549 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 181695 # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups 30042490 # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits 24994810 # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses 5047680 # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted 585906 # Number of mispredicted indirect branches.
-system.cpu2.numCycles 154015967 # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 10525182 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 153136013 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 31199361 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 25858359 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 140984091 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 1735783 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 143780 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 16316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 7923 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 66490 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 26 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 488 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 4257020 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 368090 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 3025 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 152611536 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.969429 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 3.111517 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 95212585 62.39% 62.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 896814 0.59% 62.98% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 23718994 15.54% 78.52% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 549190 0.36% 78.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 778244 0.51% 79.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 799023 0.52% 79.91% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 532989 0.35% 80.26% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 720428 0.47% 80.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 29403269 19.27% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 152611536 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.202572 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.994287 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10167862 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 90185488 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 25340442 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 4831486 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 868543 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 293911699 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 868543 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 12378234 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 76415835 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 3891181 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 27683635 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 10156457 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 290176548 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 179480 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 5269403 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 20140 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 2921556 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 344456385 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 633379614 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 389227303 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 120 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 317474127 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 26982256 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 189266 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 192828 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 22388341 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 7330700 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 4149427 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 414211 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 341335 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 283979915 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 425629 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 278392066 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 405323 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 19156154 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 28402257 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 93435 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 152611536 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.824188 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 2.420511 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 90358507 59.21% 59.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 4845557 3.18% 62.38% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 3452107 2.26% 64.65% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 3415281 2.24% 66.88% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 22680576 14.86% 81.74% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 2703807 1.77% 83.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 24243891 15.89% 99.40% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 602713 0.39% 99.80% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 309097 0.20% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 152611536 # Number of insts issued each cycle
-system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 1789790 87.09% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 208308 10.14% 97.22% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 57058 2.78% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 101487 0.04% 0.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 267636712 96.14% 96.17% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 50542 0.02% 96.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 41904 0.02% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 34 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 7148788 2.57% 98.77% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3412599 1.23% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 278392066 # Type of FU issued
-system.cpu2.iq.rate 1.807553 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 2055156 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.007382 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 711855943 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 303565687 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 275033680 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 174 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 83 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 280345636 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 99 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 602114 # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2634716 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 13210 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 5396 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1520030 # Number of stores squashed
-system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 706535 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 868543 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 71343644 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 2239546 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 284405544 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 59883 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 7330707 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 4149427 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 256703 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 145075 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 1788429 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 5396 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 270430 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 847907 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1118337 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 276410000 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 6693207 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1826872 # Number of squashed instructions skipped in execute
-system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 0 # number of nop insts executed
-system.cpu2.iew.exec_refs 9818298 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 27929809 # Number of branches executed
-system.cpu2.iew.exec_stores 3125091 # Number of stores executed
-system.cpu2.iew.exec_rate 1.794684 # Inst execution rate
-system.cpu2.iew.wb_sent 275971770 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 275033763 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 214243041 # num instructions producing a value
-system.cpu2.iew.wb_consumers 350261962 # num instructions consuming a value
-system.cpu2.iew.wb_rate 1.785748 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.611665 # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts 19130941 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 332194 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 855634 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 149565660 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.773464 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.653305 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 93221920 62.33% 62.33% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 3884084 2.60% 64.93% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1108913 0.74% 65.67% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 24362236 16.29% 81.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 961331 0.64% 82.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 644406 0.43% 83.03% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 409687 0.27% 83.30% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 23249373 15.54% 98.85% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1723710 1.15% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 149565660 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 134145476 # Number of instructions committed
-system.cpu2.commit.committedOps 265249385 # Number of ops (including micro ops) committed
-system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 7325387 # Number of memory references committed
-system.cpu2.commit.loads 4695990 # Number of loads committed
-system.cpu2.commit.membars 151817 # Number of memory barriers committed
-system.cpu2.commit.branches 27066281 # Number of branches committed
-system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 241954507 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 387238 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 47651 0.02% 0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 257791047 97.19% 97.21% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 45496 0.02% 97.22% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 40577 0.02% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 4695201 1.77% 99.01% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 2629397 0.99% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 265249385 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1723710 # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads 432186718 # The number of ROB reads
-system.cpu2.rob.rob_writes 571865889 # The number of ROB writes
-system.cpu2.timesIdled 138407 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1404431 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 4914533165 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 134145476 # Number of Instructions Simulated
-system.cpu2.committedOps 265249385 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.148126 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.148126 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.870984 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.870984 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 365815904 # number of integer regfile reads
-system.cpu2.int_regfile_writes 220629753 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 73051 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 138624705 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 107019387 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 89775262 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 129105 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 3544820 # Transaction distribution
-system.iobus.trans_dist::ReadResp 3544820 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57702 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57702 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1686 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1686 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7065558 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27910 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 7109792 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3372 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3372 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 7208416 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3532779 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13955 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 3561050 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6744 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6744 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 6595586 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 2583988 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 36000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 4499500 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 934500 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 19000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 17500 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 199160500 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 352000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 77500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 13461500 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 11500 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 119181081 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 1081000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 283709000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 25934000 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1055000 # Layer occupancy (ticks)
-system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47571 # number of replacements
-system.iocache.tags.tagsinuse 0.093993 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 5004596403009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.093993 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005875 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.005875 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428634 # Number of tag accesses
-system.iocache.tags.data_accesses 428634 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 906 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47626 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses
-system.iocache.overall_misses::total 47626 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 120463801 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 120463801 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2718328280 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 2718328280 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 2838792081 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 2838792081 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 2838792081 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 2838792081 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 132962.252759 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 132962.252759 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 58183.396404 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 58183.396404 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 59605.931235 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 59605.931235 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 59605.931235 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 59605.931235 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 354 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 28 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 12.642857 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 46667 # number of writebacks
-system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 711 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 22880 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 22880 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 23591 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 23591 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 23591 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 23591 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 84913801 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 84913801 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1572541335 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 1572541335 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 1657455136 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 1657455136 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 1657455136 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 1657455136 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.784768 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 0.784768 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.489726 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 0.489726 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.495339 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 0.495339 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.495339 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.495339 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119428.693390 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 119428.693390 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68729.953453 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68729.953453 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 70257.943114 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70257.943114 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 70257.943114 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70257.943114 # average overall mshr miss latency
-system.l2c.tags.replacements 102742 # number of replacements
-system.l2c.tags.tagsinuse 64807.232548 # Cycle average of tags in use
-system.l2c.tags.total_refs 4917874 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 166881 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 29.469346 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 50676.768734 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131121 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1597.619840 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 5190.937172 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003338 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 233.485852 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 1577.800752 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 27.152241 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker 0.957955 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1336.692253 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 4165.683291 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.773266 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.024378 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.079207 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.003563 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.024075 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000414 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.020396 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.063563 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.988880 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 64139 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 571 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3312 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 7441 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 52737 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.978683 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 43620877 # Number of tag accesses
-system.l2c.tags.data_accesses 43620877 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 21700 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 11096 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 4762 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 2301 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 121788 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 15231 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 176878 # number of ReadReq hits
-system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
-system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
-system.l2c.WritebackDirty_hits::writebacks 1557863 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 1557863 # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks 955842 # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total 955842 # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data 146 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 66 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 62 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 274 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 74219 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 34448 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 53501 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 162168 # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst 360664 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst 162659 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst 419122 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total 942445 # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 526913 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 240478 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data 560799 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 1328190 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 21700 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 11098 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 360664 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 601132 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 4762 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 2301 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 162659 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 274926 # number of demand (read+write) hits
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-system.l2c.demand_mshr_misses::cpu1.inst 1957 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 32655 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker 62 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 5042 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 38275 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 77993 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 1957 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 32655 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker 62 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 5042 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 38275 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 77993 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data 175968 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data 193387 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total 369355 # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2768 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4032 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total 6800 # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data 178736 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data 197419 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total 376155 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 73500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 4800500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 73500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 4947500 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6159500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 5718500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 11878000 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1836096500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1998176500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 3834273000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 139728500 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 379329000 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total 519057500 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 360827000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 746886000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 1107713000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 139728500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 2196923500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4800500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 73500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 379329000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 2745062500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 5465991000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 139728500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 2196923500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4800500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 73500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 379329000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 2745062500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 5465991000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28515609500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30818304000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 59333913500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28515609500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30818304000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 59333913500 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000434 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000509 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000066 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.000362 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.816156 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.820290 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.355995 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.446725 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.348470 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.194490 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011888 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011887 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007312 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019733 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.016934 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.010648 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000434 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011888 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000509 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000066 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011887 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.058652 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.027993 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000434 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011888 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000509 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000066 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011887 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.058652 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.027993 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 77304.687500 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21022.184300 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20206.713781 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20621.527778 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66013.392536 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69829.687227 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 67948.625707 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71399.335718 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75233.835779 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74161.665952 # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74535.633134 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77317.391304 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76388.731812 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71399.335718 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67276.787628 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75233.835779 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71719.464402 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 70083.097201 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71399.335718 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67276.787628 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75233.835779 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71719.464402 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 70083.097201 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162049.972154 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 159360.784334 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160641.966401 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159540.380785 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 156106.068818 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 157737.936489 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 375707 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 160970 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 1170 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq 5049003 # Transaction distribution
-system.membus.trans_dist::ReadResp 5098173 # Transaction distribution
-system.membus.trans_dist::WriteReq 13918 # Transaction distribution
-system.membus.trans_dist::WriteResp 13918 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 141406 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8879 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 1627 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 897 # Transaction distribution
-system.membus.trans_dist::ReadExReq 127688 # Transaction distribution
-system.membus.trans_dist::ReadExResp 127688 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 49387 # Transaction distribution
-system.membus.trans_dist::MessageReq 1686 # Transaction distribution
-system.membus.trans_dist::MessageResp 1686 # Transaction distribution
-system.membus.trans_dist::BadAddressError 217 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 23840 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3372 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3372 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7109792 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3016050 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456814 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 434 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 10583090 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 119675 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 119675 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10706137 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6744 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6744 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561050 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6032097 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17304384 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 26897531 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3027520 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 3027520 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 29931795 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 596 # Total snoops (count)
-system.membus.snoop_fanout::samples 5365465 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.001972 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.044366 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 5354883 99.80% 99.80% # Request fanout histogram
-system.membus.snoop_fanout::1 10582 0.20% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 5365465 # Request fanout histogram
-system.membus.reqLayer0.occupancy 219694000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 286587500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 2585012 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 464604174 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 267500 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1530012 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1157102500 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 3622087 # Layer occupancy (ticks)
-system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.toL2Bus.snoop_filter.tot_requests 5251700 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 2642649 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 1467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 797 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 797 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 5252356 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 7571420 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 1604861 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 956706 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 97687 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 1618 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1618 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 290139 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 290139 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 957232 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 1362205 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 217 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 4436 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2871137 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15084519 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 67785 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 321441 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 18344882 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 122489920 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 215022523 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 256088 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 1230880 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 338999411 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 130547 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 9049191 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.003896 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.062298 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 9013933 99.61% 99.61% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 35258 0.39% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9049191 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 3319937995 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 330397 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 883646129 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1813359528 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 21309973 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 140489176 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu2.kern.inst.arm 0 # number of arm instructions executed
-system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
-
----------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
deleted file mode 100644
index 2e4dba06f..000000000
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
+++ /dev/null
@@ -1,141 +0,0 @@
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-BIOS-provided physical RAM map:
- BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
- BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
- BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
- BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
-end_pfn_map = 1048576
-kernel direct mapping tables up to 100000000 @ 8000-d000
-DMI 2.5 present.
-Zone PFN ranges:
- DMA 0 -> 4096
- DMA32 4096 -> 1048576
- Normal 1048576 -> 1048576
-early_node_map[2] active PFN ranges
- 0: 0 -> 159
- 0: 256 -> 32768
-Intel MultiProcessor Specification v1.4
-MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
-Processor #0 (Bootup-CPU)
-I/O APIC #1 at 0xFEC00000.
-Setting APIC routing to flat
-Processors: 1
-swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
-swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
-Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
-Built 1 zonelists. Total pages: 30610
-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-Initializing CPU#0
-PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 2000.003 MHz processor.
-Console: colour dummy device 80x25
-console handover: boot [earlyser0] -> real [ttyS0]
-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
-Checking aperture...
-Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
-Mount-cache hash table entries: 256
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
-CPU: L2 Cache: 1024K (64 bytes/line)
-using mwait in idle threads.
-CPU: Fake M5 x86_64 CPU stepping 01
-ACPI: Core revision 20070126
-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
-ACPI: Unable to load the System Description Tables
-Using local APIC timer interrupts.
-result 7812530
-Detected 7.812 MHz APIC timer.
-NET: Registered protocol family 16
-PCI: Using configuration type 1
-ACPI: Interpreter disabled.
-Linux Plug and Play Support v0.97 (c) Adam Belay
-pnp: PnP ACPI: disabled
-SCSI subsystem initialized
-usbcore: registered new interface driver usbfs
-usbcore: registered new interface driver hub
-usbcore: registered new device driver usb
-PCI: Probing PCI hardware
-PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
-PCI-GART: No AMD northbridge found.
-NET: Registered protocol family 2
-Time: tsc clocksource has been installed.
-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
-TCP established hash table entries: 4096 (order: 4, 65536 bytes)
-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
-TCP: Hash tables configured (established 4096 bind 4096)
-TCP reno registered
-Total HugeTLB memory allocated, 0
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
-io scheduler noop registered
-io scheduler deadline registered
-io scheduler cfq registered (default)
-Real Time Clock Driver v1.12ac
-Linux agpgart interface v0.102 (c) Dave Jones
-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
-floppy0: no floppy controllers found
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
-loop: module loaded
-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
-Copyright (c) 1999-2006 Intel Corporation.
-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
-e100: Copyright(c) 1999-2006 Intel Corporation
-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
-tun: Universal TUN/TAP device driver, 1.6
-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
-netconsole: not configured, aborting
-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
-PIIX4: IDE controller at PCI slot 0000:00:04.0
-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
-PIIX4: chipset revision 0
-PIIX4: not 100% native mode: will probe irqs later
- ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
- ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
-hda: M5 IDE Disk, ATA DISK drive
-hdb: M5 IDE Disk, ATA DISK drive
-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
-hda: max request size: 128KiB
-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
- hda: hda1
-hdb: max request size: 128KiB
-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
- hdb: unknown partition table
-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
-Fusion MPT base driver 3.04.04
-Copyright (c) 1999-2007 LSI Logic Corporation
-Fusion MPT SPI Host driver 3.04.04
-Fusion MPT SAS Host driver 3.04.04
-ieee1394: raw1394: /dev/raw1394 device initialized
-USB Universal Host Controller Interface driver v3.0
-usbcore: registered new interface driver usblp
-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
-Initializing USB Mass Storage driver...
-usbcore: registered new interface driver usb-storage
-USB Mass Storage support registered.
-PNP: No PS/2 controller found. Probing ports directly.
-serio: i8042 KBD port at 0x60,0x64 irq 1
-serio: i8042 AUX port at 0x60,0x64 irq 12
-mice: PS/2 mouse device common for all mice
-input: AT Translated Set 2 keyboard as /class/input/input0
-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
-input: PS/2 Generic Mouse as /class/input/input1
-usbcore: registered new interface driver usbhid
-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
-oprofile: using timer interrupt.
-TCP cubic registered
-NET: Registered protocol family 1
-NET: Registered protocol family 10
-IPv6 over IPv4 tunneling driver
-NET: Registered protocol family 17
-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
-VFS: Mounted root (ext2 filesystem).
-Freeing unused kernel memory: 232k freed
- INIT: version 2.86 booting
-mounting filesystems...
-loading script...