diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
3 files changed, 3646 insertions, 3584 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index ded25c3bb..8fd17006a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,133 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.149802 # Number of seconds simulated -sim_ticks 5149801602000 # Number of ticks simulated -final_tick 5149801602000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133932 # Number of seconds simulated +sim_ticks 5133932129000 # Number of ticks simulated +final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149544 # Simulator instruction rate (inst/s) -host_op_rate 295611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1888705545 # Simulator tick rate (ticks/s) -host_mem_usage 733444 # Number of bytes of host memory used -host_seconds 2726.63 # Real time elapsed on the host -sim_insts 407752265 # Number of instructions simulated -sim_ops 806021401 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464448 # Number of bytes read from this memory +host_inst_rate 157497 # Simulator instruction rate (inst/s) +host_op_rate 311329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1982921852 # Simulator tick rate (ticks/s) +host_mem_usage 759792 # Number of bytes of host memory used +host_seconds 2589.07 # Real time elapsed on the host +sim_insts 407772261 # Number of instructions simulated +sim_ops 806052921 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1029696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10712000 # Number of bytes read from this memory -system.physmem.bytes_read::total 14210368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1029696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1029696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9492864 # Number of bytes written to this memory -system.physmem.bytes_written::total 9492864 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38507 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory +system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory +system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167375 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222037 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148326 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148326 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 478552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 758 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 199949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2080080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2759401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1843346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1843346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1843346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 478552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2080080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4602747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222037 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 148326 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 222037 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 148326 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 14210368 # Total number of bytes read from memory -system.physmem.bytesWritten 9492864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14210368 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9492864 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 1678 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 14693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 13767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 13963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13415 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13462 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13512 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14150 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 13288 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9612 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 9534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 9830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 9200 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9484 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 9208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 9093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9396 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8748 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9077 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 10300 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8795 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8716 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry -system.physmem.totGap 5149801548000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 222037 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 148326 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 173642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222430 # Number of read requests accepted +system.physmem.writeReqs 148587 # Number of write requests accepted +system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue +system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14853 # Per bank write bursts +system.physmem.perBankRdBursts::1 13635 # Per bank write bursts +system.physmem.perBankRdBursts::2 14415 # Per bank write bursts +system.physmem.perBankRdBursts::3 13770 # Per bank write bursts +system.physmem.perBankRdBursts::4 14136 # Per bank write bursts +system.physmem.perBankRdBursts::5 13341 # Per bank write bursts +system.physmem.perBankRdBursts::6 13755 # Per bank write bursts +system.physmem.perBankRdBursts::7 13953 # Per bank write bursts +system.physmem.perBankRdBursts::8 13590 # Per bank write bursts +system.physmem.perBankRdBursts::9 13369 # Per bank write bursts +system.physmem.perBankRdBursts::10 13469 # Per bank write bursts +system.physmem.perBankRdBursts::11 13962 # Per bank write bursts +system.physmem.perBankRdBursts::12 14252 # Per bank write bursts +system.physmem.perBankRdBursts::13 14454 # Per bank write bursts +system.physmem.perBankRdBursts::14 13844 # Per bank write bursts +system.physmem.perBankRdBursts::15 13571 # Per bank write bursts +system.physmem.perBankWrBursts::0 10225 # Per bank write bursts +system.physmem.perBankWrBursts::1 9089 # Per bank write bursts +system.physmem.perBankWrBursts::2 9605 # Per bank write bursts +system.physmem.perBankWrBursts::3 9165 # Per bank write bursts +system.physmem.perBankWrBursts::4 9475 # Per bank write bursts +system.physmem.perBankWrBursts::5 8866 # Per bank write bursts +system.physmem.perBankWrBursts::6 9032 # Per bank write bursts +system.physmem.perBankWrBursts::7 9363 # Per bank write bursts +system.physmem.perBankWrBursts::8 8843 # Per bank write bursts +system.physmem.perBankWrBursts::9 8764 # Per bank write bursts +system.physmem.perBankWrBursts::10 9099 # Per bank write bursts +system.physmem.perBankWrBursts::11 9352 # Per bank write bursts +system.physmem.perBankWrBursts::12 9596 # Per bank write bursts +system.physmem.perBankWrBursts::13 9639 # Per bank write bursts +system.physmem.perBankWrBursts::14 9447 # Per bank write bursts +system.physmem.perBankWrBursts::15 9010 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 5133932076000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 222430 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 148587 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -137,343 +139,366 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.140187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.041653 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1280.875932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 27817 44.52% 44.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 9622 15.40% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 5951 9.52% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 3940 6.31% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2520 4.03% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1986 3.18% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1542 2.47% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1215 1.94% 87.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 1005 1.61% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 910 1.46% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 598 0.96% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 543 0.87% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 367 0.59% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 364 0.58% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 356 0.57% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 454 0.73% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 284 0.45% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 192 0.31% 95.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 180 0.29% 95.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 146 0.23% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 174 0.28% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 177 0.28% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 484 0.77% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 176 0.28% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 118 0.19% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 94 0.15% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 80 0.13% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 58 0.09% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 28 0.04% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 25 0.04% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 31 0.05% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 34 0.05% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 13 0.02% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 15 0.02% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 19 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 8 0.01% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 10 0.02% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 8 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.00% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 9 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 9 0.01% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.00% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 7 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 3 0.00% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.00% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 5 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 14 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 6 0.01% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 3 0.00% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 21 0.03% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 7 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 6 0.01% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 3 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 5 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 3 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 4 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 4 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 2 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.00% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 7 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 339 0.54% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 8 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 3 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 4 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 3 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 28 0.04% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 15 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 10 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 3 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 3 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 6 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 7 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 6 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 8 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 12 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 11 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 62 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62488 # Bytes accessed per row activation -system.physmem.totQLat 4021160000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8281507500 # Sum of mem lat for all requests -system.physmem.totBusLat 1109590000 # Total cycles spent in databus access -system.physmem.totBankLat 3150757500 # Total cycles spent in bank access -system.physmem.avgQLat 18120.03 # Average queueing delay per request -system.physmem.avgBankLat 14197.85 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37317.87 # Average memory access latency -system.physmem.avgRdBW 2.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.84 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.76 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.84 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 22 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 3 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 28 0.04% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 23 0.03% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 5 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 2 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 26 0.04% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 3 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 25 0.04% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 6 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 3 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 5 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 25 0.04% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 2 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 3 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 26 0.04% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 3 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 76 0.11% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 6 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 6 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 6 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 14 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 3 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 3 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation +system.physmem.totQLat 5163279754 # Total ticks spent queuing +system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers +system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks +system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.63 # Average write queue length over time -system.physmem.readRowHits 198603 # Number of row buffer hits during reads -system.physmem.writeRowHits 109131 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes -system.physmem.avgGap 13904740.88 # Average gap between requests -system.membus.throughput 5073674 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662109 # Transaction distribution -system.membus.trans_dist::ReadResp 662107 # Transaction distribution -system.membus.trans_dist::WriteReq 13770 # Transaction distribution -system.membus.trans_dist::WriteResp 13770 # Transaction distribution -system.membus.trans_dist::Writeback 148326 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2172 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1696 # Transaction distribution -system.membus.trans_dist::ReadExReq 179020 # Transaction distribution -system.membus.trans_dist::ReadExResp 179014 # Transaction distribution -system.membus.trans_dist::MessageReq 1646 # Transaction distribution -system.membus.trans_dist::MessageResp 1646 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473242 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719372 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132805 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132805 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1855469 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550173 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18252032 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20044007 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5451200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5451200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25501791 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25501791 # Total data (bytes) -system.membus.snoop_data_through_bus 626624 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250581000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing +system.physmem.readRowHits 193089 # Number of row buffer hits during reads +system.physmem.writeRowHits 108689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes +system.physmem.avgGap 13837457.79 # Average gap between requests +system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 5101771 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662370 # Transaction distribution +system.membus.trans_dist::ReadResp 662362 # Transaction distribution +system.membus.trans_dist::WriteReq 13778 # Transaction distribution +system.membus.trans_dist::WriteResp 13778 # Transaction distribution +system.membus.trans_dist::Writeback 148587 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution +system.membus.trans_dist::ReadExReq 179504 # Transaction distribution +system.membus.trans_dist::ReadExResp 179502 # Transaction distribution +system.membus.trans_dist::MessageReq 1643 # Transaction distribution +system.membus.trans_dist::MessageResp 1643 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25543633 # Total data (bytes) +system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583304500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3292000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1605050249 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1646000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3149132971 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429400997 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47576 # number of replacements -system.iocache.tags.tagsinuse 0.153339 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992838664000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.153339 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.009584 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.009584 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152977935 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152977935 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10361858110 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10361858110 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10514836045 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10514836045 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10514836045 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10514836045 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -482,40 +507,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 168107.620879 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 168107.620879 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221786.346533 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 221786.346533 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220760.781965 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220760.781965 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 148180 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13622 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.877991 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105623935 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 105623935 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7930990116 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7930990116 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8036614051 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8036614051 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -524,18 +549,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116070.258242 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 116070.258242 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169755.781592 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 169755.781592 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -545,16 +570,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 636182 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225558 # Transaction distribution -system.iobus.trans_dist::ReadResp 225558 # Transaction distribution -system.iobus.trans_dist::WriteReq 57591 # Transaction distribution -system.iobus.trans_dist::WriteResp 57591 # Transaction distribution -system.iobus.trans_dist::MessageReq 1646 # Transaction distribution -system.iobus.trans_dist::MessageResp 1646 # Transaction distribution +system.iobus.throughput 638153 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225567 # Transaction distribution +system.iobus.trans_dist::ReadResp 225567 # Transaction distribution +system.iobus.trans_dist::WriteReq 57606 # Transaction distribution +system.iobus.trans_dist::WriteResp 57606 # Transaction distribution +system.iobus.trans_dist::MessageReq 1643 # Transaction distribution +system.iobus.trans_dist::MessageResp 1643 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -570,15 +595,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3292 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3292 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -594,20 +619,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6584 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6584 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276210 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276210 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3927144 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276232 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -637,456 +662,456 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424444048 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53407003 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1646000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85588006 # Number of BP lookups -system.cpu.branchPred.condPredicted 85588006 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 877454 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79215990 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77530840 # Number of BTB hits +system.cpu.branchPred.lookups 85592238 # Number of BP lookups +system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.872715 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1437704 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180381 # Number of incorrect RAS predictions. -system.cpu.numCycles 453669464 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions. +system.cpu.numCycles 453841851 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25482716 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422686689 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85588006 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78968544 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162633276 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3972302 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 106554 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 71193509 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 45334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89294 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8469801 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382535 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2385 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262601517 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.178991 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100383881 38.23% 38.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1533037 0.58% 38.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71821115 27.35% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 895642 0.34% 66.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1564995 0.60% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2390879 0.91% 68.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1017520 0.39% 68.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1329446 0.51% 68.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81665002 31.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262601517 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188657 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.931706 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29392698 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68340203 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158479192 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3338868 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3050556 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832478930 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 959 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3050556 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32088006 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43079490 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12529275 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158770454 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13083736 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829577701 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21771 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6064622 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5141489 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991205554 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800191267 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1106790785 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 123 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963930499 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27275048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 452761 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 458610 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29575764 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16714812 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9817459 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1139197 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 962008 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824812969 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1184552 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820895267 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 151456 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19155682 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29185416 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 129934 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262601517 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.126011 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400353 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76255592 29.04% 29.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15761044 6.00% 35.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10531368 4.01% 39.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7369443 2.81% 41.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75730840 28.84% 70.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3739599 1.42% 72.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72299562 27.53% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 768121 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 145948 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262601517 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 345012 32.94% 32.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 32.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 974 0.09% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547730 52.30% 85.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153356 14.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 307746 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793434579 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149572 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124688 0.02% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17663300 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9215382 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820895267 # Type of FU issued -system.cpu.iq.rate 1.809457 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1047313 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001276 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905699959 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845163637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 816985295 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 199 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821634741 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1691465 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued +system.cpu.iq.rate 1.808871 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2728859 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17017 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11975 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1400009 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931860 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12243 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3050556 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31208951 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2150350 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 825997521 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 243405 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16714812 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9817459 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 689575 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1619766 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11975 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 493977 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506066 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1000043 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819488058 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17361171 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1407208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26390625 # number of memory reference insts executed -system.cpu.iew.exec_branches 83079645 # Number of branches executed -system.cpu.iew.exec_stores 9029454 # Number of stores executed -system.cpu.iew.exec_rate 1.806355 # Inst execution rate -system.cpu.iew.wb_sent 819086222 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 816985349 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638544896 # num instructions producing a value -system.cpu.iew.wb_consumers 1043866074 # num instructions consuming a value +system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed +system.cpu.iew.exec_branches 83090404 # Number of branches executed +system.cpu.iew.exec_stores 9036920 # Number of stores executed +system.cpu.iew.exec_rate 1.805776 # Inst execution rate +system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638560375 # num instructions producing a value +system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.800838 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611712 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19867682 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054616 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 887449 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259550960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.105446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863698 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88027122 33.92% 33.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11847553 4.56% 38.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3827434 1.47% 39.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74752127 28.80% 68.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2379438 0.92% 69.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1475953 0.57% 70.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 857436 0.33% 70.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70850710 27.30% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5533187 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259550960 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407752265 # Number of instructions committed -system.cpu.commit.committedOps 806021401 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407772261 # Number of instructions committed +system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22403400 # Number of memory references committed -system.cpu.commit.loads 13985950 # Number of loads committed -system.cpu.commit.membars 474657 # Number of memory barriers committed -system.cpu.commit.branches 82156128 # Number of branches committed +system.cpu.commit.refs 22412414 # Number of memory references committed +system.cpu.commit.loads 13990896 # Number of loads committed +system.cpu.commit.membars 474709 # Number of memory barriers committed +system.cpu.commit.branches 82160310 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734862948 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155170 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5533187 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734896243 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155289 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079828496 # The number of ROB reads -system.cpu.rob.rob_writes 1654843441 # The number of ROB writes -system.cpu.timesIdled 1258915 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 191067947 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9845938983 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407752265 # Number of Instructions Simulated -system.cpu.committedOps 806021401 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407752265 # Number of Instructions Simulated -system.cpu.cpi 1.112611 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112611 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088694796 # number of integer regfile reads -system.cpu.int_regfile_writes 653771353 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.cc_regfile_reads 415601025 # number of cc regfile reads -system.cpu.cc_regfile_writes 321483560 # number of cc regfile writes -system.cpu.misc_regfile_reads 264032145 # number of misc regfile reads -system.cpu.misc_regfile_writes 402444 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53392020 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3013693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3013151 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1577044 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334035 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121437 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 151603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8199918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61058944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207524391 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 566848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5217216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 274367399 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274343271 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 615040 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4030545417 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1080212949 # The number of ROB reads +system.cpu.rob.rob_writes 1654925831 # The number of ROB writes +system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407772261 # Number of Instructions Simulated +system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated +system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads +system.cpu.int_regfile_writes 653799671 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads +system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes +system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads +system.cpu.misc_regfile_writes 402440 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1435258580 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141587747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 14741736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 105191645 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 953576 # number of replacements -system.cpu.icache.tags.tagsinuse 510.036469 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7463561 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 954088 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.822718 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147479259250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.036469 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996165 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996165 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7463561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7463561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7463561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7463561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7463561 # number of overall hits -system.cpu.icache.overall_hits::total 7463561 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1006237 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1006237 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1006237 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1006237 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1006237 # number of overall misses -system.cpu.icache.overall_misses::total 1006237 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14239259264 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14239259264 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14239259264 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14239259264 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14239259264 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14239259264 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8469798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8469798 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8469798 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8469798 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8469798 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8469798 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118803 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118803 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118803 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118803 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118803 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118803 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14150.999480 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14150.999480 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14150.999480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14150.999480 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7035 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 587 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 207 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.985507 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 587 # average number of cycles each access was blocked +system.cpu.icache.tags.replacements 959142 # number of replacements +system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits +system.cpu.icache.overall_hits::total 7468451 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses +system.cpu.icache.overall_misses::total 1013022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52085 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52085 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52085 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52085 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52085 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52085 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954152 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 954152 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 954152 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 954152 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 954152 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 954152 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11748055164 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11748055164 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11748055164 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11748055164 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11748055164 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11748055164 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112653 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112653 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112653 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11694537694 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11694537694 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11694537694 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113155 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.113155 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.113155 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12185.313376 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12185.313376 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8937 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.031585 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 20273 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8949 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.265393 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104907998500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031585 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376974 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376974 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20288 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 20288 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 8004 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.959011 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21893 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 8020 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.729800 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5103903665500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.959011 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.434938 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.434938 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21891 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21891 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20290 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 20290 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20290 # 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number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 106143491 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 106143491 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30111 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30111 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21893 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21893 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21893 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21893 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8894 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8894 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8894 # 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number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30785 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30113 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30113 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30113 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30113 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.326226 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.326226 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.326205 # 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number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30787 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.288907 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.288907 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.288888 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.288888 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.288888 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.288888 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11450.696762 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11450.696762 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11450.696762 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1095,78 +1120,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1536 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1536 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86483019 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86483019 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86483019 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86483019 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86483019 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86483019 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.326226 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.326226 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.326205 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.326205 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8804.135091 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2197 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2197 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8894 # 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number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 84047009 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.288907 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.288907 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.904441 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92410 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.337976 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 4994136871250 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.904441 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.931528 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.931528 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92410 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92410 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92410 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92410 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92410 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92410 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70084 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 70084 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70084 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 70084 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70084 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 70084 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 863900211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 863900211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 863900211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 863900211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 863900211 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 863900211 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162494 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 162494 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162494 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 162494 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162494 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 162494 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.431302 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.431302 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.431302 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.431302 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.431302 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.431302 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12326.639618 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12326.639618 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12326.639618 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12326.639618 # average overall miss latency +system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1175,146 +1200,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 17433 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 17433 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70084 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70084 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70084 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 70084 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70084 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 70084 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 723600921 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 723600921 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 723600921 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 723600921 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 723600921 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 723600921 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.431302 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.431302 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.431302 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10324.766295 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1656223 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995363 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18981681 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1656735 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.457283 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995363 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10886449 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10886449 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8092566 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8092566 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18979015 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18979015 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18979015 # number of overall hits -system.cpu.dcache.overall_hits::total 18979015 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2233485 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2233485 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315362 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2548847 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2548847 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2548847 # number of overall misses -system.cpu.dcache.overall_misses::total 2548847 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33146878091 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33146878091 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12110851955 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12110851955 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45257730046 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45257730046 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45257730046 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45257730046 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13119934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13119934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8407928 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8407928 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21527862 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21527862 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21527862 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21527862 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170236 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170236 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037508 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037508 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118398 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118398 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118398 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118398 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14840.877862 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14840.877862 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38403.016074 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38403.016074 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17756.157998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17756.157998 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021679 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820352 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820352 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101622 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068785 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73953.509479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60687.872649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61851.512879 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16087 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169067 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185220 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4502000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075523016 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11379203177 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4502000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075523016 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10298851911 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11379203177 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251387000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251387000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372677500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372677500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823198 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823198 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461846 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461846 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068880 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068880 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66856.655436 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69205.271768 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68485.890487 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.383721 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.383721 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.769844 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.769844 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index e0fd581aa..d95103a1f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,365 +1,323 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.304492 # Number of seconds simulated -sim_ticks 5304492233500 # Number of ticks simulated -final_tick 5304492233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.303604 # Number of seconds simulated +sim_ticks 5303604289000 # Number of ticks simulated +final_tick 5303604289000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155930 # Simulator instruction rate (inst/s) -host_op_rate 299191 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7641192165 # Simulator tick rate (ticks/s) -host_mem_usage 831032 # Number of bytes of host memory used -host_seconds 694.20 # Real time elapsed on the host -sim_insts 108246430 # Number of instructions simulated -sim_ops 207697456 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 136600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 67168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 857797264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 68434149 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 89360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 41152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 170486264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 28476493 # Number of bytes read from this memory -system.physmem.bytes_read::total 1125563554 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857797264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 170486264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1028283528 # Number of instructions bytes read from this memory +host_inst_rate 170166 # Simulator instruction rate (inst/s) +host_op_rate 326512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8335943745 # Simulator tick rate (ticks/s) +host_mem_usage 875260 # Number of bytes of host memory used +host_seconds 636.23 # Real time elapsed on the host +sim_insts 108265301 # Number of instructions simulated +sim_ops 207738037 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 35128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 87544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 33280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 839536560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 65163112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 137640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 74624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 188924512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 31786983 # Number of bytes read from this memory +system.physmem.bytes_read::total 1125779383 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 839536560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 188924512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1028461072 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 47724441 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 22209848 # Number of bytes written to this memory -system.physmem.bytes_written::total 72925409 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 17075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 107224658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 11945854 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 21310783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4242510 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144766394 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 45585342 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 24372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 72949070 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 807 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 104942070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 11447211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 17205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 9328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 23615564 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4748353 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144795641 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 7033055 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 3067077 # Number of write requests responded to by this memory -system.physmem.num_writes::total 10146870 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 25752 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 12662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 161711475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12901169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 16846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 7758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32139978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5368373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 212190631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 161711475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32139978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 193851453 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563881 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 6738169 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 3365460 # Number of write requests responded to by this memory +system.physmem.num_writes::total 10150367 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 16507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 6275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 158295475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12286571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 25952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 14070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35621909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5993468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 212266851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 158295475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35621909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 193917384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563976 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 8996986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 4186989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13747859 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 25752 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 12665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 161711475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 21898154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 16846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 7758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32139978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 9555362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 225938490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 804 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 46736 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 804 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 46736 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 51456 # Total number of bytes read from memory -system.physmem.bytesWritten 2991104 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 35104 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 324 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 128 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 3280 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 3344 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 3056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2576 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2704 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2608 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2816 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3072 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2720 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 3008 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 3136 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry -system.physmem.totGap 163206922999 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 292 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 512 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 46736 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 537 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5562.279330 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3318.964815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3321.501933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 31 5.77% 5.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 6 1.12% 6.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4 0.74% 7.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 7 1.30% 8.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 7 1.30% 10.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2 0.37% 10.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1 0.19% 10.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 2 0.37% 11.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1 0.19% 11.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1 0.19% 11.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2 0.37% 11.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1 0.19% 12.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.56% 12.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1 0.19% 12.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1 0.19% 13.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 62 11.55% 24.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.19% 24.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 1 0.19% 24.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.56% 25.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2 0.37% 25.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.19% 26.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 16 2.98% 29.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.19% 29.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.19% 29.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 5 0.93% 30.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.19% 30.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.19% 30.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.19% 30.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 1 0.19% 31.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.19% 31.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.19% 31.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 35 6.52% 37.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.19% 38.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.19% 38.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.19% 38.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 8 1.49% 40.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.19% 40.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.56% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.19% 40.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 6 1.12% 42.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.19% 42.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 310 57.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 537 # Bytes accessed per row activation -system.physmem.totQLat 42021352 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 52311352 # Sum of mem lat for all requests -system.physmem.totBusLat 4020000 # Total cycles spent in databus access -system.physmem.totBankLat 6270000 # Total cycles spent in bank access -system.physmem.avgQLat 52265.36 # Average queueing delay per request -system.physmem.avgBankLat 7798.51 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 65063.87 # Average memory access latency -system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bw_write::cpu0.data 8595163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 4595480 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13754622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 16507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 6278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 158295475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 20881734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 25952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 14070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35621909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 10588948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 226021473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 0 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 0 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 0 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 0 # Per bank write bursts +system.physmem.perBankRdBursts::1 0 # Per bank write bursts +system.physmem.perBankRdBursts::2 0 # Per bank write bursts +system.physmem.perBankRdBursts::3 0 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 0 # Per bank write bursts +system.physmem.perBankRdBursts::7 0 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 0 # Per bank write bursts +system.physmem.perBankRdBursts::10 0 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 0 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation +system.physmem.totQLat 0 # Total ticks spent queuing +system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 0 # Total ticks spent in databus transfers +system.physmem.totBankLat 0 # Total ticks spent accessing banks +system.physmem.avgQLat nan # Average queueing delay per DRAM burst +system.physmem.avgBankLat nan # Average bank access latency per DRAM burst +system.physmem.avgBusLat nan # Average bus latency per DRAM burst +system.physmem.avgMemAccLat nan # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.00 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 735 # Number of row buffer hits during reads -system.physmem.writeRowHits 46268 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 99.00 # Row buffer hit rate for writes -system.physmem.avgGap 3433044.24 # Average gap between requests -system.piobus.throughput 959190 # Throughput (bytes/s) -system.piobus.trans_dist::ReadReq 865004 # Transaction distribution -system.piobus.trans_dist::ReadResp 865004 # Transaction distribution -system.piobus.trans_dist::WriteReq 86867 # Transaction distribution -system.piobus.trans_dist::WriteResp 86867 # Transaction distribution -system.piobus.trans_dist::MessageReq 2698 # Transaction distribution -system.piobus.trans_dist::MessageResp 2698 # Transaction distribution -system.piobus.pkt_count_system.pc.south_bridge.ide.dma::system.physmem.port 95080 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.ide.dma::total 95080 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1704 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1648 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3352 # Packet count per connected master and slave (bytes) +system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests +system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state +system.piobus.throughput 388759 # Throughput (bytes/s) +system.piobus.trans_dist::ReadReq 864194 # Transaction distribution +system.piobus.trans_dist::ReadResp 864194 # Transaction distribution +system.piobus.trans_dist::WriteReq 40126 # Transaction distribution +system.piobus.trans_dist::WriteResp 40126 # Transaction distribution +system.piobus.trans_dist::MessageReq 2700 # Transaction distribution +system.piobus.trans_dist::MessageResp 2700 # Transaction distribution +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1702 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1644 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3346 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 7290 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 5756 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 988 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 82 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 46 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1028 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1014 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 178 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 20480 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 20120 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 751796 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 751828 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1723300 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 3752 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1721420 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 5240 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 376 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 8 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 33180 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 344 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 340 # Packet count per connected master and slave (bytes) system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 33180 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 6188 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 8322 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 85362 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 1020 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1020 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1024 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1024 # Packet count per connected master and slave (bytes) -system.piobus.pkt_count::total 1909138 # Packet count per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026208 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026208 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3408 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3296 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6704 # Cumulative packet size per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 6556 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 8324 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 87220 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 1032 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 1032 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 1022 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 1022 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::total 1814040 # Packet count per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3404 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3288 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6692 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 4565 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 3669 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 494 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 41 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 23 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2056 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2028 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 89 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 10240 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 10060 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1503586 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1503650 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1995120 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 2095 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1994078 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 2965 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 188 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 4 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 16590 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 688 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 680 # Cumulative packet size per connected master and slave (bytes) system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 16590 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 3094 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 16641 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 55896 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 2040 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2040 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2048 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2048 # Cumulative packet size per connected master and slave (bytes) -system.piobus.tot_pkt_size::total 5088016 # Cumulative packet size per connected master and slave (bytes) -system.piobus.data_through_bus 5088016 # Total data (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 3278 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 16645 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 56948 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 2064 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 2064 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 2044 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 2044 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::total 2061826 # Cumulative packet size per connected master and slave (bytes) +system.piobus.data_through_bus 2061826 # Total data (bytes) system.piobus.reqLayer0.occupancy 51000 # Layer occupancy (ticks) system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer2.occupancy 10166500 # Layer occupancy (ticks) +system.piobus.reqLayer2.occupancy 10114500 # Layer occupancy (ticks) system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer3.occupancy 152000 # Layer occupancy (ticks) system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer4.occupancy 1062500 # Layer occupancy (ticks) +system.piobus.reqLayer4.occupancy 1060500 # Layer occupancy (ticks) system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer5.occupancy 98500 # Layer occupancy (ticks) system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%) @@ -369,13 +327,13 @@ system.piobus.reqLayer7.occupancy 22149500 # La system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer8.occupancy 586857000 # Layer occupancy (ticks) system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer9.occupancy 1330000 # Layer occupancy (ticks) +system.piobus.reqLayer9.occupancy 1313000 # Layer occupancy (ticks) system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer10.occupancy 41670000 # Layer occupancy (ticks) system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer12.occupancy 23281000 # Layer occupancy (ticks) +system.piobus.reqLayer12.occupancy 23288000 # Layer occupancy (ticks) system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%) @@ -385,36 +343,32 @@ system.piobus.reqLayer15.occupancy 10500 # La system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer17.occupancy 473785500 # Layer occupancy (ticks) +system.piobus.reqLayer17.occupancy 473822500 # Layer occupancy (ticks) system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer18.occupancy 3210816 # Layer occupancy (ticks) +system.piobus.reqLayer18.occupancy 3230956 # Layer occupancy (ticks) system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer19.occupancy 8819500 # Layer occupancy (ticks) +system.piobus.reqLayer19.occupancy 8830000 # Layer occupancy (ticks) system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer20.occupancy 3135584 # Layer occupancy (ticks) +system.piobus.reqLayer20.occupancy 3180944 # Layer occupancy (ticks) system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.piobus.reqLayer21.occupancy 421722676 # Layer occupancy (ticks) -system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%) system.piobus.reqLayer22.occupancy 1069500 # Layer occupancy (ticks) system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer0.occupancy 52207182 # Layer occupancy (ticks) +system.piobus.respLayer0.occupancy 2420900 # Layer occupancy (ticks) system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer1.occupancy 2368900 # Layer occupancy (ticks) +system.piobus.respLayer1.occupancy 1925709500 # Layer occupancy (ticks) system.piobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer2.occupancy 1927202500 # Layer occupancy (ticks) +system.piobus.respLayer2.occupancy 68943500 # Layer occupancy (ticks) system.piobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer3.occupancy 67468000 # Layer occupancy (ticks) +system.piobus.respLayer3.occupancy 649000 # Layer occupancy (ticks) system.piobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer4.occupancy 641000 # Layer occupancy (ticks) +system.piobus.respLayer4.occupancy 642000 # Layer occupancy (ticks) system.piobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.piobus.respLayer5.occupancy 638500 # Layer occupancy (ticks) -system.piobus.respLayer5.utilization 0.0 # Layer utilization (%) -system.ruby.l1_cntrl0.L1Dcache.demand_hits 17400971 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 1603411 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 19004382 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 106716418 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 508240 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 107224658 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 16641315 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 1559170 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 18200485 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 104473354 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 468716 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 104942070 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -424,12 +378,12 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.L1Dcache.demand_hits 7028238 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 297663 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 7325901 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 21021438 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 289345 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 21310783 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 7796271 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 344075 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8140346 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 23285981 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 329583 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 23615564 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -439,514 +393,580 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l2_cntrl0.L2cache.demand_hits 2449214 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 249445 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2698659 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 0.088789 -system.ruby.network.routers0.msg_count.Control::0 2111651 -system.ruby.network.routers0.msg_count.Request_Control::0 68326 -system.ruby.network.routers0.msg_count.Response_Data::1 2154834 -system.ruby.network.routers0.msg_count.Response_Control::1 1565369 -system.ruby.network.routers0.msg_count.Response_Control::2 1557069 -system.ruby.network.routers0.msg_count.Writeback_Data::0 1435847 -system.ruby.network.routers0.msg_count.Writeback_Data::1 52 -system.ruby.network.routers0.msg_count.Writeback_Control::0 59460 -system.ruby.network.routers0.msg_bytes.Control::0 16893208 -system.ruby.network.routers0.msg_bytes.Request_Control::0 546608 -system.ruby.network.routers0.msg_bytes.Response_Data::1 155148048 -system.ruby.network.routers0.msg_bytes.Response_Control::1 12522952 -system.ruby.network.routers0.msg_bytes.Response_Control::2 12456552 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 103380984 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 3744 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 475680 -system.ruby.network.routers1.percent_links_utilized 0.020109 -system.ruby.network.routers1.msg_count.Control::0 587008 -system.ruby.network.routers1.msg_count.Request_Control::0 61976 -system.ruby.network.routers1.msg_count.Response_Data::1 624789 -system.ruby.network.routers1.msg_count.Response_Control::1 278706 -system.ruby.network.routers1.msg_count.Response_Control::2 271876 -system.ruby.network.routers1.msg_count.Writeback_Data::0 187266 -system.ruby.network.routers1.msg_count.Writeback_Data::1 273 -system.ruby.network.routers1.msg_count.Writeback_Control::0 22758 -system.ruby.network.routers1.msg_bytes.Control::0 4696064 -system.ruby.network.routers1.msg_bytes.Request_Control::0 495808 -system.ruby.network.routers1.msg_bytes.Response_Data::1 44984808 -system.ruby.network.routers1.msg_bytes.Response_Control::1 2229648 -system.ruby.network.routers1.msg_bytes.Response_Control::2 2175008 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 13483152 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 19656 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 182064 -system.ruby.network.routers2.percent_links_utilized 0.111786 -system.ruby.network.routers2.msg_count.Control::0 2871394 -system.ruby.network.routers2.msg_count.Request_Control::0 128339 -system.ruby.network.routers2.msg_count.Response_Data::1 2893297 -system.ruby.network.routers2.msg_count.Response_Control::1 1875820 -system.ruby.network.routers2.msg_count.Response_Control::2 1828945 -system.ruby.network.routers2.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers2.msg_count.Writeback_Data::1 325 -system.ruby.network.routers2.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers2.msg_bytes.Control::0 22971152 -system.ruby.network.routers2.msg_bytes.Request_Control::0 1026712 -system.ruby.network.routers2.msg_bytes.Response_Data::1 208317384 -system.ruby.network.routers2.msg_bytes.Response_Control::1 15006560 -system.ruby.network.routers2.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers2.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers2.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers2.msg_bytes.Writeback_Control::0 657744 -system.ruby.dir_cntrl0.memBuffer.memReq 267094 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 172735 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 94359 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 684452 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 920715 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 18 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 5950 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 926683 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 3.469501 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 909950 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 7902 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 10 # memory stalls due to read write turnaround +system.ruby.l2_cntrl0.L2cache.demand_hits 2450353 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 251191 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2701544 # Number of cache demand accesses +system.ruby.network.routers0.percent_links_utilized 0.085942 +system.ruby.network.routers0.msg_count.Control::0 2027886 +system.ruby.network.routers0.msg_count.Request_Control::0 68787 +system.ruby.network.routers0.msg_count.Response_Data::1 2071049 +system.ruby.network.routers0.msg_count.Response_Control::1 1525279 +system.ruby.network.routers0.msg_count.Response_Control::2 1517023 +system.ruby.network.routers0.msg_count.Writeback_Data::0 1403655 +system.ruby.network.routers0.msg_count.Writeback_Data::1 171 +system.ruby.network.routers0.msg_count.Writeback_Control::0 51157 +system.ruby.network.routers0.msg_bytes.Control::0 16223088 +system.ruby.network.routers0.msg_bytes.Request_Control::0 550296 +system.ruby.network.routers0.msg_bytes.Response_Data::1 149115528 +system.ruby.network.routers0.msg_bytes.Response_Control::1 12202232 +system.ruby.network.routers0.msg_bytes.Response_Control::2 12136184 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 101063160 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12312 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 409256 +system.ruby.network.routers1.percent_links_utilized 0.023064 +system.ruby.network.routers1.msg_count.Control::0 673658 +system.ruby.network.routers1.msg_count.Request_Control::0 62763 +system.ruby.network.routers1.msg_count.Response_Data::1 711847 +system.ruby.network.routers1.msg_count.Response_Control::1 320652 +system.ruby.network.routers1.msg_count.Response_Control::2 313476 +system.ruby.network.routers1.msg_count.Writeback_Data::0 219226 +system.ruby.network.routers1.msg_count.Writeback_Data::1 383 +system.ruby.network.routers1.msg_count.Writeback_Control::0 32004 +system.ruby.network.routers1.msg_bytes.Control::0 5389264 +system.ruby.network.routers1.msg_bytes.Request_Control::0 502104 +system.ruby.network.routers1.msg_bytes.Response_Data::1 51252984 +system.ruby.network.routers1.msg_bytes.Response_Control::1 2565216 +system.ruby.network.routers1.msg_bytes.Response_Control::2 2507808 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 15784272 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 27576 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 256032 +system.ruby.network.routers2.percent_links_utilized 0.111968 +system.ruby.network.routers2.msg_count.Control::0 2875657 +system.ruby.network.routers2.msg_count.Request_Control::0 129481 +system.ruby.network.routers2.msg_count.Response_Data::1 2899412 +system.ruby.network.routers2.msg_count.Response_Control::1 1882104 +system.ruby.network.routers2.msg_count.Response_Control::2 1830499 +system.ruby.network.routers2.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers2.msg_count.Writeback_Data::1 554 +system.ruby.network.routers2.msg_count.Writeback_Control::0 83161 +system.ruby.network.routers2.msg_bytes.Control::0 23005256 +system.ruby.network.routers2.msg_bytes.Request_Control::0 1035848 +system.ruby.network.routers2.msg_bytes.Response_Data::1 208757664 +system.ruby.network.routers2.msg_bytes.Response_Control::1 15056832 +system.ruby.network.routers2.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers2.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers2.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers2.msg_bytes.Writeback_Control::0 665288 +system.ruby.dir_cntrl0.memBuffer.memReq 315825 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 174561 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 141264 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 718428 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 922537 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 6012 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 928595 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.940220 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 911376 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 8161 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 74 # memory stalls due to read write turnaround system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 2845 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 8698 3.26% 3.26% | 8135 3.05% 6.30% | 8180 3.06% 9.36% | 8226 3.08% 12.44% | 8503 3.18% 15.63% | 8270 3.10% 18.72% | 8182 3.06% 21.79% | 8201 3.07% 24.86% | 8425 3.15% 28.01% | 8229 3.08% 31.09% | 8315 3.11% 34.21% | 8269 3.10% 37.30% | 8279 3.10% 40.40% | 8033 3.01% 43.41% | 8159 3.05% 46.46% | 7316 2.74% 49.20% | 8194 3.07% 52.27% | 8382 3.14% 55.41% | 8204 3.07% 58.48% | 8117 3.04% 61.52% | 8878 3.32% 64.84% | 8321 3.12% 67.96% | 8274 3.10% 71.06% | 8202 3.07% 74.13% | 8422 3.15% 77.28% | 8239 3.08% 80.37% | 8482 3.18% 83.54% | 9065 3.39% 86.94% | 8995 3.37% 90.30% | 8927 3.34% 93.65% | 8865 3.32% 96.96% | 8107 3.04% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 267094 # Number of accesses per bank - -system.ruby.network.routers3.percent_links_utilized 0.006355 -system.ruby.network.routers3.msg_count.Control::0 172735 -system.ruby.network.routers3.msg_count.Response_Data::1 267094 -system.ruby.network.routers3.msg_count.Response_Control::1 120099 -system.ruby.network.routers3.msg_bytes.Control::0 1381880 -system.ruby.network.routers3.msg_bytes.Response_Data::1 19230768 -system.ruby.network.routers3.msg_bytes.Response_Control::1 960792 -system.ruby.network.routers4.percent_links_utilized 0 -system.ruby.network.routers5.percent_links_utilized 0.045409 -system.ruby.network.routers5.msg_count.Control::0 2871394 -system.ruby.network.routers5.msg_count.Request_Control::0 130302 -system.ruby.network.routers5.msg_count.Response_Data::1 2970007 -system.ruby.network.routers5.msg_count.Response_Control::1 1919997 -system.ruby.network.routers5.msg_count.Response_Control::2 1828945 -system.ruby.network.routers5.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers5.msg_count.Writeback_Data::1 325 -system.ruby.network.routers5.msg_count.Writeback_Control::0 82218 -system.ruby.network.routers5.msg_bytes.Control::0 22971152 -system.ruby.network.routers5.msg_bytes.Request_Control::0 1042416 -system.ruby.network.routers5.msg_bytes.Response_Data::1 213840504 -system.ruby.network.routers5.msg_bytes.Response_Control::1 15359976 -system.ruby.network.routers5.msg_bytes.Response_Control::2 14631560 -system.ruby.network.routers5.msg_bytes.Writeback_Data::0 116864136 -system.ruby.network.routers5.msg_bytes.Writeback_Data::1 23400 -system.ruby.network.routers5.msg_bytes.Writeback_Control::0 657744 -system.ruby.network.msg_count.Control 8614182 -system.ruby.network.msg_count.Request_Control 388943 -system.ruby.network.msg_count.Response_Data 8910021 -system.ruby.network.msg_count.Response_Control 11246826 -system.ruby.network.msg_count.Writeback_Data 4870314 -system.ruby.network.msg_count.Writeback_Control 246654 -system.ruby.network.msg_byte.Control 68913456 -system.ruby.network.msg_byte.Request_Control 3111544 -system.ruby.network.msg_byte.Response_Data 641521512 -system.ruby.network.msg_byte.Response_Control 89974608 -system.ruby.network.msg_byte.Writeback_Data 350662608 -system.ruby.network.msg_byte.Writeback_Control 1973232 +system.ruby.dir_cntrl0.memBuffer.memArbWait 2918 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 10778 3.41% 3.41% | 9652 3.06% 6.47% | 9746 3.09% 9.55% | 9756 3.09% 12.64% | 10001 3.17% 15.81% | 9844 3.12% 18.93% | 9739 3.08% 22.01% | 9701 3.07% 25.08% | 9912 3.14% 28.22% | 9771 3.09% 31.31% | 9821 3.11% 34.42% | 9856 3.12% 37.55% | 9814 3.11% 40.65% | 9541 3.02% 43.67% | 9708 3.07% 46.75% | 8720 2.76% 49.51% | 9704 3.07% 52.58% | 9910 3.14% 55.72% | 9720 3.08% 58.80% | 9615 3.04% 61.84% | 10345 3.28% 65.12% | 9799 3.10% 68.22% | 9732 3.08% 71.30% | 9663 3.06% 74.36% | 9975 3.16% 77.52% | 9775 3.10% 80.61% | 9975 3.16% 83.77% | 10515 3.33% 87.10% | 10479 3.32% 90.42% | 10356 3.28% 93.70% | 10312 3.27% 96.96% | 9590 3.04% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 315825 # Number of accesses per bank + +system.ruby.network.routers3.percent_links_utilized 0.006686 +system.ruby.network.routers3.msg_count.Control::0 174113 +system.ruby.network.routers3.msg_count.Response_Data::1 271479 +system.ruby.network.routers3.msg_count.Response_Control::1 125011 +system.ruby.network.routers3.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers3.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers3.msg_bytes.Control::0 1392904 +system.ruby.network.routers3.msg_bytes.Response_Data::1 19546488 +system.ruby.network.routers3.msg_bytes.Response_Control::1 1000088 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers4.percent_links_utilized 0.000239 +system.ruby.network.routers4.msg_count.Response_Data::1 807 +system.ruby.network.routers4.msg_count.Writeback_Control::0 47543 +system.ruby.network.routers4.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers4.msg_bytes.Response_Data::1 58104 +system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380344 +system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.routers5.percent_links_utilized 0.045581 +system.ruby.network.routers5.msg_count.Control::0 2875657 +system.ruby.network.routers5.msg_count.Request_Control::0 131550 +system.ruby.network.routers5.msg_count.Response_Data::1 2977297 +system.ruby.network.routers5.msg_count.Response_Control::1 1926523 +system.ruby.network.routers5.msg_count.Response_Control::2 1830499 +system.ruby.network.routers5.msg_count.Writeback_Data::0 1622881 +system.ruby.network.routers5.msg_count.Writeback_Data::1 554 +system.ruby.network.routers5.msg_count.Writeback_Control::0 130704 +system.ruby.network.routers5.msg_count.Writeback_Control::1 46736 +system.ruby.network.routers5.msg_bytes.Control::0 23005256 +system.ruby.network.routers5.msg_bytes.Request_Control::0 1052400 +system.ruby.network.routers5.msg_bytes.Response_Data::1 214365384 +system.ruby.network.routers5.msg_bytes.Response_Control::1 15412184 +system.ruby.network.routers5.msg_bytes.Response_Control::2 14643992 +system.ruby.network.routers5.msg_bytes.Writeback_Data::0 116847432 +system.ruby.network.routers5.msg_bytes.Writeback_Data::1 39888 +system.ruby.network.routers5.msg_bytes.Writeback_Control::0 1045632 +system.ruby.network.routers5.msg_bytes.Writeback_Control::1 373888 +system.ruby.network.msg_count.Control 8626971 +system.ruby.network.msg_count.Request_Control 392581 +system.ruby.network.msg_count.Response_Data 8931891 +system.ruby.network.msg_count.Response_Control 11271066 +system.ruby.network.msg_count.Writeback_Data 4870305 +system.ruby.network.msg_count.Writeback_Control 532320 +system.ruby.network.msg_byte.Control 69015768 +system.ruby.network.msg_byte.Request_Control 3140648 +system.ruby.network.msg_byte.Response_Data 643096152 +system.ruby.network.msg_byte.Response_Control 90168528 +system.ruby.network.msg_byte.Writeback_Data 350661960 +system.ruby.network.msg_byte.Writeback_Control 4258560 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10606783749 # number of cpu cycles simulated +system.cpu0.numCycles 10606043496 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 91841555 # Number of instructions committed -system.cpu0.committedOps 177241434 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 167144917 # Number of integer alu accesses +system.cpu0.committedInsts 90093236 # Number of instructions committed +system.cpu0.committedOps 174126687 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 164075837 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 2106041 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16306998 # number of instructions that are conditional controls -system.cpu0.num_int_insts 167144917 # number of integer instructions +system.cpu0.num_func_calls 2042485 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16069367 # number of instructions that are conditional controls +system.cpu0.num_int_insts 164075837 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315702148 # number of times the integer registers were read -system.cpu0.num_int_register_writes 141403252 # number of times the integer registers were written +system.cpu0.num_int_register_reads 309321057 # number of times the integer registers were read +system.cpu0.num_int_register_writes 138932000 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 97172274 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 67502160 # number of times the CC registers were written -system.cpu0.num_mem_refs 19838885 # number of memory refs -system.cpu0.num_load_insts 12792113 # Number of load instructions -system.cpu0.num_store_insts 7046772 # Number of store instructions -system.cpu0.num_idle_cycles 9879393312.871359 # Number of idle cycles -system.cpu0.num_busy_cycles 727390436.128641 # Number of busy cycles -system.cpu0.not_idle_fraction 0.068578 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.931422 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 95439290 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 66446258 # number of times the CC registers were written +system.cpu0.num_mem_refs 19043793 # number of memory refs +system.cpu0.num_load_insts 12292919 # Number of load instructions +system.cpu0.num_store_insts 6750874 # Number of store instructions +system.cpu0.num_idle_cycles 9893327113.048590 # Number of idle cycles +system.cpu0.num_busy_cycles 712716382.951410 # Number of busy cycles +system.cpu0.not_idle_fraction 0.067199 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.932801 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10608984467 # number of cpu cycles simulated +system.cpu1.numCycles 10607208578 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 16404875 # Number of instructions committed -system.cpu1.committedOps 30456022 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 29781645 # Number of integer alu accesses +system.cpu1.committedInsts 18172065 # Number of instructions committed +system.cpu1.committedOps 33611350 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 32888204 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 684501 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2123636 # number of instructions that are conditional controls -system.cpu1.num_int_insts 29781645 # number of integer instructions +system.cpu1.num_func_calls 748563 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2364634 # number of instructions that are conditional controls +system.cpu1.num_int_insts 32888204 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 60931294 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23868275 # number of times the integer registers were written +system.cpu1.num_int_register_reads 67386533 # number of times the integer registers were read +system.cpu1.num_int_register_writes 26370518 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 16456023 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 10042488 # number of times the CC registers were written -system.cpu1.num_mem_refs 7344657 # number of memory refs -system.cpu1.num_load_insts 4252428 # Number of load instructions -system.cpu1.num_store_insts 3092229 # Number of store instructions -system.cpu1.num_idle_cycles 10473305727.446026 # Number of idle cycles -system.cpu1.num_busy_cycles 135678739.553974 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012789 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987211 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 18215408 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 11108428 # number of times the CC registers were written +system.cpu1.num_mem_refs 8150413 # number of memory refs +system.cpu1.num_load_insts 4758811 # Number of load instructions +system.cpu1.num_store_insts 3391602 # Number of store instructions +system.cpu1.num_idle_cycles 10456532847.286028 # Number of idle cycles +system.cpu1.num_busy_cycles 150675730.713972 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014205 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985795 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.ruby.network.routers0.throttle0.link_utilization 0.096297 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 68326 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 2091943 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 1536429 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 546608 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 150619896 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 12291432 -system.ruby.network.routers0.throttle1.link_utilization 0.081281 -system.ruby.network.routers0.throttle1.msg_count.Control::0 2111651 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 62891 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 28940 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 1557069 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 1435847 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 52 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 59460 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 16893208 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 4528152 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 231520 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 12456552 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 103380984 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 3744 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 475680 -system.ruby.network.routers1.throttle0.link_utilization 0.025474 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 61976 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 565416 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 254379 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 495808 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 40709952 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 2035032 -system.ruby.network.routers1.throttle1.link_utilization 0.014743 -system.ruby.network.routers1.throttle1.msg_count.Control::0 587008 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 59373 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 24327 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 271876 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 187266 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 273 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 22758 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4696064 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 4274856 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 194616 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 2175008 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 13483152 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 19656 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 182064 -system.ruby.network.routers2.throttle0.link_utilization 0.100395 -system.ruby.network.routers2.throttle0.msg_count.Control::0 2698659 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 218289 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 116319 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1828945 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 1623113 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 325 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 82218 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-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::0 1026712 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 192600576 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 14076008 -system.ruby.network.routers3.throttle0.link_utilization 0.004877 -system.ruby.network.routers3.throttle0.msg_count.Control::0 172735 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 94359 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 12870 -system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1381880 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 6793848 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 102960 -system.ruby.network.routers3.throttle1.link_utilization 0.007832 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 172735 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 107229 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100.00% -system.ruby.l1_cntrl0.WB_Ack::total 1705331 - -system.ruby.l1_cntrl0.NP.Load | 1269187 90.60% 90.60% | 131722 9.40% 100.00% -system.ruby.l1_cntrl0.NP.Load::total 1400909 - -system.ruby.l1_cntrl0.NP.Ifetch | 507807 63.72% 63.72% | 289135 36.28% 100.00% -system.ruby.l1_cntrl0.NP.Ifetch::total 796942 - -system.ruby.l1_cntrl0.NP.Store | 290704 70.79% 70.79% | 119960 29.21% 100.00% -system.ruby.l1_cntrl0.NP.Store::total 410664 - -system.ruby.l1_cntrl0.NP.Inv | 6486 66.07% 66.07% | 3331 33.93% 100.00% -system.ruby.l1_cntrl0.NP.Inv::total 9817 - -system.ruby.l1_cntrl0.I.Load | 16022 50.92% 50.92% | 15443 49.08% 100.00% -system.ruby.l1_cntrl0.I.Load::total 31465 +system.ruby.network.routers0.throttle0.link_utilization 0.092567 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 68787 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 2008081 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 1496069 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5 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 5 + +system.ruby.l1_cntrl0.Data | 1647 57.45% 57.45% | 1220 42.55% 100.00% +system.ruby.l1_cntrl0.Data::total 2867 + +system.ruby.l1_cntrl0.Data_Exclusive | 1191679 90.64% 90.64% | 123071 9.36% 100.00% +system.ruby.l1_cntrl0.Data_Exclusive::total 1314750 + +system.ruby.l1_cntrl0.DataS_fromL1 | 22264 48.58% 48.58% | 23562 51.42% 100.00% +system.ruby.l1_cntrl0.DataS_fromL1::total 45826 + +system.ruby.l1_cntrl0.Data_all_Acks | 792491 61.12% 61.12% | 504058 38.88% 100.00% +system.ruby.l1_cntrl0.Data_all_Acks::total 1296549 + +system.ruby.l1_cntrl0.Ack | 19805 47.66% 47.66% | 21747 52.34% 100.00% +system.ruby.l1_cntrl0.Ack::total 41552 + +system.ruby.l1_cntrl0.Ack_all | 21452 48.29% 48.29% | 22967 51.71% 100.00% +system.ruby.l1_cntrl0.Ack_all::total 44419 + +system.ruby.l1_cntrl0.WB_Ack | 1454812 85.27% 85.27% | 251230 14.73% 100.00% +system.ruby.l1_cntrl0.WB_Ack::total 1706042 + +system.ruby.l1_cntrl0.NP.Load | 1239865 88.45% 88.45% | 161879 11.55% 100.00% +system.ruby.l1_cntrl0.NP.Load::total 1401744 + +system.ruby.l1_cntrl0.NP.Ifetch | 468275 58.71% 58.71% | 329378 41.29% 100.00% +system.ruby.l1_cntrl0.NP.Ifetch::total 797653 + +system.ruby.l1_cntrl0.NP.Store | 275512 66.93% 66.93% | 136131 33.07% 100.00% +system.ruby.l1_cntrl0.NP.Store::total 411643 + +system.ruby.l1_cntrl0.NP.Inv | 6534 64.01% 64.01% | 3673 35.99% 100.00% +system.ruby.l1_cntrl0.NP.Inv::total 10207 -system.ruby.l1_cntrl0.I.Ifetch | 433 67.34% 67.34% | 210 32.66% 100.00% -system.ruby.l1_cntrl0.I.Ifetch::total 643 +system.ruby.l1_cntrl0.I.Load | 16225 51.38% 51.38% | 15353 48.62% 100.00% +system.ruby.l1_cntrl0.I.Load::total 31578 -system.ruby.l1_cntrl0.I.Store | 7790 46.55% 46.55% | 8946 53.45% 100.00% -system.ruby.l1_cntrl0.I.Store::total 16736 +system.ruby.l1_cntrl0.I.Ifetch | 441 68.27% 68.27% | 205 31.73% 100.00% +system.ruby.l1_cntrl0.I.Ifetch::total 646 -system.ruby.l1_cntrl0.I.L1_Replacement | 13955 53.66% 53.66% | 12049 46.34% 100.00% -system.ruby.l1_cntrl0.I.L1_Replacement::total 26004 +system.ruby.l1_cntrl0.I.Store | 7763 46.41% 46.41% | 8965 53.59% 100.00% +system.ruby.l1_cntrl0.I.Store::total 16728 -system.ruby.l1_cntrl0.S.Load | 738807 59.22% 59.22% | 508786 40.78% 100.00% -system.ruby.l1_cntrl0.S.Load::total 1247593 +system.ruby.l1_cntrl0.I.L1_Replacement | 14196 53.57% 53.57% | 12303 46.43% 100.00% +system.ruby.l1_cntrl0.I.L1_Replacement::total 26499 -system.ruby.l1_cntrl0.S.Ifetch | 106716418 83.54% 83.54% | 21021438 16.46% 100.00% -system.ruby.l1_cntrl0.S.Ifetch::total 127737856 +system.ruby.l1_cntrl0.S.Load | 716363 57.80% 57.80% | 523017 42.20% 100.00% +system.ruby.l1_cntrl0.S.Load::total 1239380 -system.ruby.l1_cntrl0.S.Store | 19708 47.72% 47.72% | 21592 52.28% 100.00% -system.ruby.l1_cntrl0.S.Store::total 41300 +system.ruby.l1_cntrl0.S.Ifetch | 104473354 81.77% 81.77% | 23285981 18.23% 100.00% +system.ruby.l1_cntrl0.S.Ifetch::total 127759335 -system.ruby.l1_cntrl0.S.Inv | 22433 51.85% 51.85% | 20836 48.15% 100.00% -system.ruby.l1_cntrl0.S.Inv::total 43269 +system.ruby.l1_cntrl0.S.Store | 19805 47.66% 47.66% | 21747 52.34% 100.00% +system.ruby.l1_cntrl0.S.Store::total 41552 -system.ruby.l1_cntrl0.S.L1_Replacement | 557412 63.69% 63.69% | 317721 36.31% 100.00% -system.ruby.l1_cntrl0.S.L1_Replacement::total 875133 +system.ruby.l1_cntrl0.S.Inv | 22660 52.04% 52.04% | 20885 47.96% 100.00% +system.ruby.l1_cntrl0.S.Inv::total 43545 -system.ruby.l1_cntrl0.E.Load | 3045109 82.70% 82.70% | 636901 17.30% 100.00% -system.ruby.l1_cntrl0.E.Load::total 3682010 +system.ruby.l1_cntrl0.S.L1_Replacement | 513620 58.60% 58.60% | 362831 41.40% 100.00% +system.ruby.l1_cntrl0.S.L1_Replacement::total 876451 -system.ruby.l1_cntrl0.E.Store | 119075 77.49% 77.49% | 34591 22.51% 100.00% -system.ruby.l1_cntrl0.E.Store::total 153666 +system.ruby.l1_cntrl0.E.Load | 2877485 78.07% 78.07% | 808285 21.93% 100.00% +system.ruby.l1_cntrl0.E.Load::total 3685770 -system.ruby.l1_cntrl0.E.Inv | 21 11.60% 11.60% | 160 88.40% 100.00% -system.ruby.l1_cntrl0.E.Inv::total 181 +system.ruby.l1_cntrl0.E.Store | 114491 74.50% 74.50% | 39180 25.50% 100.00% +system.ruby.l1_cntrl0.E.Store::total 153671 -system.ruby.l1_cntrl0.E.L1_Replacement | 1096110 94.67% 94.67% | 61694 5.33% 100.00% -system.ruby.l1_cntrl0.E.L1_Replacement::total 1157804 +system.ruby.l1_cntrl0.E.Inv | 16 9.64% 9.64% | 150 90.36% 100.00% +system.ruby.l1_cntrl0.E.Inv::total 166 -system.ruby.l1_cntrl0.E.Fwd_GETX | 178 53.13% 53.13% | 157 46.87% 100.00% -system.ruby.l1_cntrl0.E.Fwd_GETX::total 335 +system.ruby.l1_cntrl0.E.L1_Replacement | 1075597 92.92% 92.92% | 82009 7.08% 100.00% +system.ruby.l1_cntrl0.E.L1_Replacement::total 1157606 -system.ruby.l1_cntrl0.E.Fwd_GETS | 1386 57.01% 57.01% | 1045 42.99% 100.00% -system.ruby.l1_cntrl0.E.Fwd_GETS::total 2431 +system.ruby.l1_cntrl0.E.Fwd_GETX | 157 36.77% 36.77% | 270 63.23% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GETX::total 427 -system.ruby.l1_cntrl0.M.Load | 6354074 70.62% 70.62% | 2643672 29.38% 100.00% -system.ruby.l1_cntrl0.M.Load::total 8997746 +system.ruby.l1_cntrl0.E.Fwd_GETS | 1309 50.17% 50.17% | 1300 49.83% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GETS::total 2609 -system.ruby.l1_cntrl0.M.Store | 7143906 69.04% 69.04% | 3204288 30.96% 100.00% -system.ruby.l1_cntrl0.M.Store::total 10348194 +system.ruby.l1_cntrl0.E.Fwd_GET_INSTR | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GET_INSTR::total 1 -system.ruby.l1_cntrl0.M.Inv | 52 16.00% 16.00% | 273 84.00% 100.00% -system.ruby.l1_cntrl0.M.Inv::total 325 +system.ruby.l1_cntrl0.M.Load | 6087722 67.58% 67.58% | 2920243 32.42% 100.00% +system.ruby.l1_cntrl0.M.Load::total 9007965 -system.ruby.l1_cntrl0.M.L1_Replacement | 399197 72.91% 72.91% | 148330 27.09% 100.00% -system.ruby.l1_cntrl0.M.L1_Replacement::total 547527 +system.ruby.l1_cntrl0.M.Store | 6845254 66.13% 66.13% | 3505546 33.87% 100.00% +system.ruby.l1_cntrl0.M.Store::total 10350800 -system.ruby.l1_cntrl0.M.Fwd_GETX | 15599 50.61% 50.61% | 15222 49.39% 100.00% -system.ruby.l1_cntrl0.M.Fwd_GETX::total 30821 +system.ruby.l1_cntrl0.M.Inv | 171 30.87% 30.87% | 383 69.13% 100.00% +system.ruby.l1_cntrl0.M.Inv::total 554 -system.ruby.l1_cntrl0.M.Fwd_GETS | 22167 51.41% 51.41% | 20952 48.59% 100.00% -system.ruby.l1_cntrl0.M.Fwd_GETS::total 43119 +system.ruby.l1_cntrl0.M.L1_Replacement | 379215 69.14% 69.14% | 169221 30.86% 100.00% +system.ruby.l1_cntrl0.M.L1_Replacement::total 548436 + +system.ruby.l1_cntrl0.M.Fwd_GETX | 15687 50.89% 50.89% | 15138 49.11% 100.00% +system.ruby.l1_cntrl0.M.Fwd_GETX::total 30825 + +system.ruby.l1_cntrl0.M.Fwd_GETS | 22248 51.49% 51.49% | 20963 48.51% 100.00% +system.ruby.l1_cntrl0.M.Fwd_GETS::total 43211 system.ruby.l1_cntrl0.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.l1_cntrl0.M.Fwd_GET_INSTR::total 4 -system.ruby.l1_cntrl0.IS.Data_Exclusive | 1216870 92.56% 92.56% | 97821 7.44% 100.00% -system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1314691 - -system.ruby.l1_cntrl0.IS.DataS_fromL1 | 21997 48.29% 48.29% | 23557 51.71% 100.00% -system.ruby.l1_cntrl0.IS.DataS_fromL1::total 45554 - -system.ruby.l1_cntrl0.IS.Data_all_Acks | 554582 63.77% 63.77% | 315132 36.23% 100.00% -system.ruby.l1_cntrl0.IS.Data_all_Acks::total 869714 - -system.ruby.l1_cntrl0.IM.Data | 1706 59.30% 59.30% | 1171 40.70% 100.00% -system.ruby.l1_cntrl0.IM.Data::total 2877 - -system.ruby.l1_cntrl0.IM.Data_all_Acks | 296788 69.91% 69.91% | 127735 30.09% 100.00% -system.ruby.l1_cntrl0.IM.Data_all_Acks::total 424523 - -system.ruby.l1_cntrl0.SM.Ack | 19708 47.72% 47.72% | 21592 52.28% 100.00% -system.ruby.l1_cntrl0.SM.Ack::total 41300 - -system.ruby.l1_cntrl0.SM.Ack_all | 21414 48.47% 48.47% | 22763 51.53% 100.00% -system.ruby.l1_cntrl0.SM.Ack_all::total 44177 - -system.ruby.l1_cntrl0.M_I.Ifetch | 3 50.00% 50.00% | 3 50.00% 100.00% -system.ruby.l1_cntrl0.M_I.Ifetch::total 6 - -system.ruby.l1_cntrl0.M_I.WB_Ack | 1495307 87.68% 87.68% | 210024 12.32% 100.00% -system.ruby.l1_cntrl0.M_I.WB_Ack::total 1705331 - -system.ruby.l2_cntrl0.L1_GET_INSTR 797586 0.00% 0.00% -system.ruby.l2_cntrl0.L1_GETS 1432569 0.00% 0.00% -system.ruby.l2_cntrl0.L1_GETX 427401 0.00% 0.00% -system.ruby.l2_cntrl0.L1_UPGRADE 41300 0.00% 0.00% -system.ruby.l2_cntrl0.L1_PUTX 1705331 0.00% 0.00% -system.ruby.l2_cntrl0.L2_Replacement 94194 0.00% 0.00% -system.ruby.l2_cntrl0.L2_Replacement_clean 13035 0.00% 0.00% -system.ruby.l2_cntrl0.Mem_Data 172735 0.00% 0.00% -system.ruby.l2_cntrl0.Mem_Ack 107229 0.00% 0.00% -system.ruby.l2_cntrl0.WB_Data 45318 0.00% 0.00% -system.ruby.l2_cntrl0.WB_Data_clean 561 0.00% 0.00% -system.ruby.l2_cntrl0.Ack 1963 0.00% 0.00% -system.ruby.l2_cntrl0.Ack_all 7127 0.00% 0.00% -system.ruby.l2_cntrl0.Unblock 45554 0.00% 0.00% -system.ruby.l2_cntrl0.Exclusive_Unblock 1783391 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GET_INSTR 15440 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GETS 31271 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GETX 126024 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GET_INSTR 781852 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GETS 72133 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GETX 3021 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_UPGRADE 41300 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L2_Replacement 241 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L2_Replacement_clean 6705 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GET_INSTR 289 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GETS 1283420 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GETX 267199 0.00% 0.00% -system.ruby.l2_cntrl0.M.L2_Replacement 93756 0.00% 0.00% -system.ruby.l2_cntrl0.M.L2_Replacement_clean 6021 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GETS 45550 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GETX 31156 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_PUTX 1705331 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L2_Replacement 197 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L2_Replacement_clean 309 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive | 1191679 90.64% 90.64% | 123071 9.36% 100.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1314750 + +system.ruby.l1_cntrl0.IS.DataS_fromL1 | 22264 48.58% 48.58% | 23562 51.42% 100.00% +system.ruby.l1_cntrl0.IS.DataS_fromL1::total 45826 + +system.ruby.l1_cntrl0.IS.Data_all_Acks | 510863 58.65% 58.65% | 360182 41.35% 100.00% +system.ruby.l1_cntrl0.IS.Data_all_Acks::total 871045 + +system.ruby.l1_cntrl0.IM.Data | 1647 57.45% 57.45% | 1220 42.55% 100.00% +system.ruby.l1_cntrl0.IM.Data::total 2867 + +system.ruby.l1_cntrl0.IM.Data_all_Acks | 281628 66.19% 66.19% | 143876 33.81% 100.00% +system.ruby.l1_cntrl0.IM.Data_all_Acks::total 425504 + +system.ruby.l1_cntrl0.SM.Ack | 19805 47.66% 47.66% | 21747 52.34% 100.00% +system.ruby.l1_cntrl0.SM.Ack::total 41552 + +system.ruby.l1_cntrl0.SM.Ack_all | 21452 48.29% 48.29% | 22967 51.71% 100.00% +system.ruby.l1_cntrl0.SM.Ack_all::total 44419 + +system.ruby.l1_cntrl0.M_I.Ifetch | 1 20.00% 20.00% | 4 80.00% 100.00% +system.ruby.l1_cntrl0.M_I.Ifetch::total 5 + +system.ruby.l1_cntrl0.M_I.Fwd_GETS | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.l1_cntrl0.M_I.Fwd_GETS::total 1 + +system.ruby.l1_cntrl0.M_I.WB_Ack | 1454812 85.27% 85.27% | 251229 14.73% 100.00% +system.ruby.l1_cntrl0.M_I.WB_Ack::total 1706041 + +system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack::total 1 + +system.ruby.l2_cntrl0.L1_GET_INSTR 798300 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS 1433505 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 428371 0.00% 0.00% +system.ruby.l2_cntrl0.L1_UPGRADE 41552 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 1706043 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 93999 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement_clean 13201 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Data 174113 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Ack 109590 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data 45725 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data_clean 655 0.00% 0.00% +system.ruby.l2_cntrl0.Ack 2069 0.00% 0.00% +system.ruby.l2_cntrl0.Ack_all 7430 0.00% 0.00% +system.ruby.l2_cntrl0.Unblock 45826 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 1784673 0.00% 0.00% +system.ruby.l2_cntrl0.MEM_Inv 4780 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GET_INSTR 15882 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 31693 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 126538 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GET_INSTR 782387 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETS 72751 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETX 3011 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_UPGRADE 41552 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_PUTX 1 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement 271 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement_clean 6989 0.00% 0.00% +system.ruby.l2_cntrl0.SS.MEM_Inv 4 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GET_INSTR 25 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 1283057 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 267570 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 93550 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement_clean 5909 0.00% 0.00% +system.ruby.l2_cntrl0.M.MEM_Inv 2147 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GET_INSTR 5 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GETS 45821 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GETX 31252 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_PUTX 1706041 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement 178 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement_clean 303 0.00% 0.00% +system.ruby.l2_cntrl0.MT.MEM_Inv 239 0.00% 0.00% system.ruby.l2_cntrl0.M_I.L1_GET_INSTR 1 0.00% 0.00% -system.ruby.l2_cntrl0.M_I.Mem_Ack 107229 0.00% 0.00% -system.ruby.l2_cntrl0.MT_I.WB_Data 160 0.00% 0.00% -system.ruby.l2_cntrl0.MT_I.Ack_all 37 0.00% 0.00% -system.ruby.l2_cntrl0.MCT_I.WB_Data 165 0.00% 0.00% -system.ruby.l2_cntrl0.MCT_I.Ack_all 144 0.00% 0.00% -system.ruby.l2_cntrl0.I_I.Ack 1732 0.00% 0.00% -system.ruby.l2_cntrl0.I_I.Ack_all 6705 0.00% 0.00% -system.ruby.l2_cntrl0.S_I.Ack 231 0.00% 0.00% -system.ruby.l2_cntrl0.S_I.Ack_all 241 0.00% 0.00% -system.ruby.l2_cntrl0.ISS.Mem_Data 31271 0.00% 0.00% -system.ruby.l2_cntrl0.IS.Mem_Data 15440 0.00% 0.00% -system.ruby.l2_cntrl0.IM.Mem_Data 126024 0.00% 0.00% -system.ruby.l2_cntrl0.SS_MB.L1_GETS 136 0.00% 0.00% -system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 44321 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.L1_GETS 59 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.L1_GETX 1 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1739070 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.WB_Data 44897 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 561 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.Unblock 96 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IB.WB_Data 96 0.00% 0.00% -system.ruby.l2_cntrl0.MT_SB.Unblock 45458 0.00% 0.00% -system.ruby.dir_cntrl0.Fetch 172735 0.00% 0.00% -system.ruby.dir_cntrl0.Data 94359 0.00% 0.00% -system.ruby.dir_cntrl0.Memory_Data 172735 0.00% 0.00% -system.ruby.dir_cntrl0.Memory_Ack 94359 0.00% 0.00% -system.ruby.dir_cntrl0.CleanReplacement 12870 0.00% 0.00% -system.ruby.dir_cntrl0.I.Fetch 172735 0.00% 0.00% -system.ruby.dir_cntrl0.M.Data 94359 0.00% 0.00% -system.ruby.dir_cntrl0.M.CleanReplacement 12870 0.00% 0.00% -system.ruby.dir_cntrl0.IM.Memory_Data 172735 0.00% 0.00% -system.ruby.dir_cntrl0.MI.Memory_Ack 94359 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.Mem_Ack 109590 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.MEM_Inv 2147 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.WB_Data 384 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.Ack_all 33 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.MEM_Inv 239 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data 170 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.Ack_all 133 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack 1795 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack_all 6989 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.Ack 274 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.Ack_all 275 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.MEM_Inv 4 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.Mem_Data 31693 0.00% 0.00% +system.ruby.l2_cntrl0.IS.Mem_Data 15882 0.00% 0.00% +system.ruby.l2_cntrl0.IM.Mem_Data 126538 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.L1_GETS 134 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 44563 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L1_GETS 49 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1740110 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.L1_PUTX 1 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.WB_Data 45078 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 654 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.Unblock 94 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IB.WB_Data 93 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IB.WB_Data_clean 1 0.00% 0.00% +system.ruby.l2_cntrl0.MT_SB.Unblock 45732 0.00% 0.00% +system.ruby.dma_cntrl0.ReadRequest 807 0.00% 0.00% +system.ruby.dma_cntrl0.WriteRequest 46736 0.00% 0.00% +system.ruby.dma_cntrl0.Data 807 0.00% 0.00% +system.ruby.dma_cntrl0.Ack 46736 0.00% 0.00% +system.ruby.dma_cntrl0.READY.ReadRequest 807 0.00% 0.00% +system.ruby.dma_cntrl0.READY.WriteRequest 46736 0.00% 0.00% +system.ruby.dma_cntrl0.BUSY_RD.Data 807 0.00% 0.00% +system.ruby.dma_cntrl0.BUSY_WR.Ack 46736 0.00% 0.00% +system.ruby.dir_cntrl0.Fetch 174113 0.00% 0.00% +system.ruby.dir_cntrl0.Data 96559 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 174561 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 141264 0.00% 0.00% +system.ruby.dir_cntrl0.DMA_READ 807 0.00% 0.00% +system.ruby.dir_cntrl0.DMA_WRITE 46736 0.00% 0.00% +system.ruby.dir_cntrl0.CleanReplacement 13031 0.00% 0.00% +system.ruby.dir_cntrl0.I.Fetch 174113 0.00% 0.00% +system.ruby.dir_cntrl0.I.DMA_READ 448 0.00% 0.00% +system.ruby.dir_cntrl0.I.DMA_WRITE 44705 0.00% 0.00% +system.ruby.dir_cntrl0.ID.Memory_Data 448 0.00% 0.00% +system.ruby.dir_cntrl0.ID_W.Memory_Ack 44705 0.00% 0.00% +system.ruby.dir_cntrl0.M.Data 94169 0.00% 0.00% +system.ruby.dir_cntrl0.M.DMA_READ 359 0.00% 0.00% +system.ruby.dir_cntrl0.M.DMA_WRITE 2031 0.00% 0.00% +system.ruby.dir_cntrl0.M.CleanReplacement 13031 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 174113 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 94169 0.00% 0.00% +system.ruby.dir_cntrl0.M_DRD.Data 359 0.00% 0.00% +system.ruby.dir_cntrl0.M_DRDI.Memory_Ack 359 0.00% 0.00% +system.ruby.dir_cntrl0.M_DWR.Data 2031 0.00% 0.00% +system.ruby.dir_cntrl0.M_DWRI.Memory_Ack 2031 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index f1500ba2f..e884e1c2d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,155 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137889 # Number of seconds simulated -sim_ticks 5137889173500 # Number of ticks simulated -final_tick 5137889173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137942 # Number of seconds simulated +sim_ticks 5137941673500 # Number of ticks simulated +final_tick 5137941673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239672 # Simulator instruction rate (inst/s) -host_op_rate 476391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5046842796 # Simulator tick rate (ticks/s) -host_mem_usage 957396 # Number of bytes of host memory used -host_seconds 1018.04 # Real time elapsed on the host -sim_insts 243995320 # Number of instructions simulated -sim_ops 484985266 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2475904 # Number of bytes read from this memory +host_inst_rate 248874 # Simulator instruction rate (inst/s) +host_op_rate 494699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5246911955 # Simulator tick rate (ticks/s) +host_mem_usage 994832 # Number of bytes of host memory used +host_seconds 979.23 # Real time elapsed on the host +sim_insts 243705182 # Number of instructions simulated +sim_ops 484425104 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2466368 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 403712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5648960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 122048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1730432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 426944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5894144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1789248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 439808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2919040 # Number of bytes read from this memory -system.physmem.bytes_read::total 13741824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 403712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 122048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 439808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 965568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9081216 # Number of bytes written to this memory -system.physmem.bytes_written::total 9081216 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38686 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu2.inst 385728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2633280 # Number of bytes read from this memory +system.physmem.bytes_read::total 13744640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 426944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 385728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 959872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9091584 # Number of bytes written to this memory +system.physmem.bytes_written::total 9091584 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38537 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6308 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 88265 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 27038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6671 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 92096 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2300 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 27957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6872 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 45610 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214716 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141894 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141894 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 481891 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.inst 6027 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41145 # Number of read requests responded to by this memory +system.physmem.num_reads::total 214760 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142056 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142056 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 480030 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 78575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1099471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 23755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 336798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 83096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1147180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 28650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 348242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 85601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 568140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2674605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 78575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 23755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 85601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1767499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1767499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1767499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 481891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 75074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 512517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2675126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 83096 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 28650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 75074 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 186820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1769499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1769499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1769499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 480030 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 78575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1099471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 23755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 336798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 83096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1147180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 28650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 348242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 85601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 568140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4442104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 101962 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 77214 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 101962 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 77214 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 6525568 # Total number of bytes read from memory -system.physmem.bytesWritten 4941696 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6525568 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4941696 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 761 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6400 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 5890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 5804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6034 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 5639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6508 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6828 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4748 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5043 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4974 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4576 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4071 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4483 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4133 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5171 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry -system.physmem.totGap 5136889044500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 101962 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 77214 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 78859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 669 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.bw_total::cpu2.inst 75074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 512517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4444625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 100936 # Number of read requests accepted +system.physmem.writeReqs 78380 # Number of write requests accepted +system.physmem.readBursts 100936 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 78380 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6458816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue +system.physmem.bytesWritten 5015040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6459904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5016320 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 699 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5898 # Per bank write bursts +system.physmem.perBankRdBursts::1 6403 # Per bank write bursts +system.physmem.perBankRdBursts::2 6411 # Per bank write bursts +system.physmem.perBankRdBursts::3 6523 # Per bank write bursts +system.physmem.perBankRdBursts::4 6306 # Per bank write bursts +system.physmem.perBankRdBursts::5 6840 # Per bank write bursts +system.physmem.perBankRdBursts::6 6199 # Per bank write bursts +system.physmem.perBankRdBursts::7 6896 # Per bank write bursts +system.physmem.perBankRdBursts::8 5528 # Per bank write bursts +system.physmem.perBankRdBursts::9 5898 # Per bank write bursts +system.physmem.perBankRdBursts::10 6128 # Per bank write bursts +system.physmem.perBankRdBursts::11 6570 # Per bank write bursts +system.physmem.perBankRdBursts::12 6317 # Per bank write bursts +system.physmem.perBankRdBursts::13 6334 # Per bank write bursts +system.physmem.perBankRdBursts::14 6542 # Per bank write bursts +system.physmem.perBankRdBursts::15 6126 # Per bank write bursts +system.physmem.perBankWrBursts::0 4721 # Per bank write bursts +system.physmem.perBankWrBursts::1 4902 # Per bank write bursts +system.physmem.perBankWrBursts::2 4923 # Per bank write bursts +system.physmem.perBankWrBursts::3 5159 # Per bank write bursts +system.physmem.perBankWrBursts::4 5192 # Per bank write bursts +system.physmem.perBankWrBursts::5 5457 # Per bank write bursts +system.physmem.perBankWrBursts::6 4843 # Per bank write bursts +system.physmem.perBankWrBursts::7 5797 # Per bank write bursts +system.physmem.perBankWrBursts::8 4085 # Per bank write bursts +system.physmem.perBankWrBursts::9 4367 # Per bank write bursts +system.physmem.perBankWrBursts::10 4807 # Per bank write bursts +system.physmem.perBankWrBursts::11 4903 # Per bank write bursts +system.physmem.perBankWrBursts::12 4884 # Per bank write bursts +system.physmem.perBankWrBursts::13 4699 # Per bank write bursts +system.physmem.perBankWrBursts::14 5116 # Per bank write bursts +system.physmem.perBankWrBursts::15 4505 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 5136941479000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 100936 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 78380 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 75816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -161,534 +163,549 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 349.964889 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.240831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1180.348858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14687 44.84% 44.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5019 15.32% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3032 9.26% 69.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2021 6.17% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1281 3.91% 79.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1132 3.46% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 832 2.54% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 693 2.12% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 503 1.54% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 527 1.61% 90.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 287 0.88% 91.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 266 0.81% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 203 0.62% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 195 0.60% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 197 0.60% 94.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 238 0.73% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 149 0.45% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 112 0.34% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 86 0.26% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 79 0.24% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 89 0.27% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 70 0.21% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 290 0.89% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 98 0.30% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 63 0.19% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 48 0.15% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 49 0.15% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 27 0.08% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 22 0.07% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 16 0.05% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 11 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 13 0.04% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 5 0.02% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 10 0.03% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 3 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 2 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 3 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 4 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 5 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 9 0.03% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 5 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 48 0.15% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 2 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 2 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 13 0.04% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 7 0.02% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 3 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 3 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 3 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 3 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 9 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 10 0.03% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 15 0.05% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 34 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17667 2 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32753 # Bytes accessed per row activation -system.physmem.totQLat 1954361749 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3940385499 # Sum of mem lat for all requests -system.physmem.totBusLat 509480000 # Total cycles spent in databus access -system.physmem.totBankLat 1476543750 # Total cycles spent in bank access -system.physmem.avgQLat 19179.97 # Average queueing delay per request -system.physmem.avgBankLat 14490.69 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38670.66 # Average memory access latency -system.physmem.avgRdBW 1.27 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.96 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.27 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.96 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.217991 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.094116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1121.662575 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16547 46.47% 46.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5535 15.54% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3551 9.97% 71.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2213 6.22% 78.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1334 3.75% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1101 3.09% 85.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 807 2.27% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 584 1.64% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 515 1.45% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 517 1.45% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 309 0.87% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 309 0.87% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 205 0.58% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 200 0.56% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 177 0.50% 95.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 272 0.76% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 139 0.39% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 84 0.24% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 95 0.27% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 94 0.26% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 81 0.23% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 178 0.50% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 83 0.23% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 58 0.16% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 45 0.13% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 38 0.11% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 29 0.08% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 19 0.05% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 15 0.04% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 14 0.04% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 11 0.03% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 8 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 6 0.02% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 5 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 3 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 4 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 8 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 5 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 8 0.02% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 3 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 5 0.01% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 6 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 6 0.02% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 4 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 3 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 4 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 3 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 3 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 20 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 2 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 2 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 2 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 2 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 2 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 3 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 2 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 3 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 3 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 12 0.03% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 6 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 10 0.03% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 3 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 5 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 9 0.03% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 8 0.02% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 29 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35607 # Bytes accessed per row activation +system.physmem.totQLat 2741683498 # Total ticks spent queuing +system.physmem.totMemAccLat 4643457248 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 504595000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1397178750 # Total ticks spent accessing banks +system.physmem.avgQLat 27167.17 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13844.56 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 46011.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.98 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.12 # Average write queue length over time -system.physmem.readRowHits 89443 # Number of row buffer hits during reads -system.physmem.writeRowHits 56909 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes -system.physmem.avgGap 28669515.14 # Average gap between requests -system.membus.throughput 6421183 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 424471 # Transaction distribution -system.membus.trans_dist::ReadResp 424470 # Transaction distribution -system.membus.trans_dist::WriteReq 6959 # Transaction distribution -system.membus.trans_dist::WriteResp 6959 # Transaction distribution -system.membus.trans_dist::Writeback 77214 # Transaction distribution -system.membus.trans_dist::UpgradeReq 768 # Transaction distribution -system.membus.trans_dist::UpgradeResp 768 # Transaction distribution -system.membus.trans_dist::ReadExReq 79729 # Transaction distribution -system.membus.trans_dist::ReadExResp 79729 # Transaction distribution -system.membus.trans_dist::MessageReq 903 # Transaction distribution -system.membus.trans_dist::MessageResp 903 # Transaction distribution +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.11 # Average write queue length when enqueuing +system.physmem.readRowHits 85240 # Number of row buffer hits during reads +system.physmem.writeRowHits 58432 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes +system.physmem.avgGap 28647423.98 # Average gap between requests +system.physmem.pageHitRate 80.13 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6427951 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 423177 # Transaction distribution +system.membus.trans_dist::ReadResp 423176 # Transaction distribution +system.membus.trans_dist::WriteReq 6474 # Transaction distribution +system.membus.trans_dist::WriteResp 6474 # Transaction distribution +system.membus.trans_dist::Writeback 78380 # Transaction distribution +system.membus.trans_dist::UpgradeReq 714 # Transaction distribution +system.membus.trans_dist::UpgradeResp 714 # Transaction distribution +system.membus.trans_dist::ReadExReq 80216 # Transaction distribution +system.membus.trans_dist::ReadExResp 80216 # Transaction distribution +system.membus.trans_dist::MessageReq 892 # Transaction distribution +system.membus.trans_dist::MessageResp 892 # Transaction distribution system.membus.trans_dist::BadAddressError 1 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497960 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 218608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 310648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497624 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 207711 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1028904 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 68108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1098818 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3612 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3612 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160445 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995917 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8655808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9812170 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2811456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2811456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12627238 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32732190 # Total data (bytes) -system.membus.snoop_data_through_bus 259136 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 164966500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::total 1015985 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 78748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 78748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1096517 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159467 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995245 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8228608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9383320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 3247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12634504 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32719620 # Total data (bytes) +system.membus.snoop_data_through_bus 306816 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 163512000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315386000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315210000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1806000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1784000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 820026249 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 830204748 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 903000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 892000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1636763940 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1595294481 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 218001500 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 252511249 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 103793 # number of replacements -system.l2c.tags.tagsinuse 64823.461690 # Cycle average of tags in use -system.l2c.tags.total_refs 3658744 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167885 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.793156 # Average number of references to valid blocks. +system.l2c.tags.replacements 103855 # number of replacements +system.l2c.tags.tagsinuse 64822.347448 # Cycle average of tags in use +system.l2c.tags.total_refs 3646219 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167877 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.719586 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51284.674060 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121869 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1299.911935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4544.856644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 221.437918 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1509.586927 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.216404 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003202 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1337.967786 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4616.684944 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.782542 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51292.264352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121895 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1278.615227 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4499.945934 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 292.458405 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1505.357985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.212632 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1370.507166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4576.860668 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.782658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019835 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.069349 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003379 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000125 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.019510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.068664 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004463 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.022970 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000095 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.070445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989128 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22091 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11658 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 334413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 510225 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10171 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5452 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 152259 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 227659 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 50814 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 10913 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 351942 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 566551 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2254148 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu2.inst 0.020912 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.069837 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989111 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 19693 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10326 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 346717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 513928 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10907 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5932 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 155624 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223811 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 47020 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 9087 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 331652 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 566093 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2240790 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1543420 # number of Writeback hits -system.l2c.Writeback_hits::total 1543420 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 115 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 83 # number of UpgradeReq hits +system.l2c.Writeback_hits::writebacks 1542501 # number of Writeback hits +system.l2c.Writeback_hits::total 1542501 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 58 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 57 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 254 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 69377 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 36565 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 61899 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 167841 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22091 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11660 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 334413 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 579602 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10171 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5452 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 152259 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 264224 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 50814 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 10913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 351942 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 628450 # number of demand (read+write) hits -system.l2c.demand_hits::total 2421991 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22091 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11660 # number of overall hits -system.l2c.overall_hits::cpu0.inst 334413 # number of overall hits -system.l2c.overall_hits::cpu0.data 579602 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10171 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5452 # number of overall hits -system.l2c.overall_hits::cpu1.inst 152259 # number of overall hits -system.l2c.overall_hits::cpu1.data 264224 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 50814 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10913 # number of overall hits -system.l2c.overall_hits::cpu2.inst 351942 # number of overall hits -system.l2c.overall_hits::cpu2.data 628450 # number of overall hits -system.l2c.overall_hits::total 2421991 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 70841 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 36082 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 59675 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 166598 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 19693 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10328 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 346717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 584769 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10907 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5932 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 155624 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 259893 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 47020 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 9087 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 331652 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 625768 # number of demand (read+write) hits +system.l2c.demand_hits::total 2407390 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 19693 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10328 # number of overall hits +system.l2c.overall_hits::cpu0.inst 346717 # number of overall hits +system.l2c.overall_hits::cpu0.data 584769 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10907 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5932 # number of overall hits +system.l2c.overall_hits::cpu1.inst 155624 # number of overall hits +system.l2c.overall_hits::cpu1.data 259893 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 47020 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 9087 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -832,39 +849,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47570 # number of replacements -system.iocache.tags.tagsinuse 0.094174 # Cycle average of tags in use +system.iocache.tags.replacements 47575 # number of replacements +system.iocache.tags.tagsinuse 0.094274 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000166705009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094174 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005886 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005886 # 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number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -873,56 +890,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145777.647514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145777.647514 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 111856.382213 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 111856.382213 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 112500.975286 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 112500.975286 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 75733 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142638.514286 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 142638.514286 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 146525.546661 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 146525.546661 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 146451.282553 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 146451.282553 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 105453 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7002 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6453 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.815910 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.341702 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 739 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 23440 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 23440 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 24179 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 24179 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 24179 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 24179 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93470771 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93470771 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4006299177 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4006299177 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4099769948 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4099769948 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816575 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.816575 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.501712 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.501712 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.507696 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.507696 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126482.775372 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 126482.775372 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 170917.200384 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 170917.200384 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 724 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 27280 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 27280 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 28004 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 28004 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 28004 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 28004 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92126548 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92126548 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 5426189542 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5426189542 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5518316090 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5518316090 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.795604 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.795604 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.583904 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.583904 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.587949 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.587949 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127246.613260 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127246.613260 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 198907.241276 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 198907.241276 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -936,459 +953,459 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52280174 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1811511 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1810976 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6959 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6959 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 914733 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 716 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 716 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 178384 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 154949 # Transaction distribution +system.toL2Bus.throughput 52188015 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1787129 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1786595 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 6474 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 6474 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 905502 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 665 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 665 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 176137 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 148862 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1025990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3658453 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 36523 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 129481 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4850447 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32830848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 121529738 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 130928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 488080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 154979594 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268493674 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 116064 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5106548110 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 991248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3625702 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34347 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 125379 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4776676 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31718784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120252184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 463592 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 152554720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268001344 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 137632 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5049278590 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 882000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2311338505 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2232669307 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4765806692 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4714355905 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 20170721 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 19343965 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 68576287 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 67521559 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1274820 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 150850 # Transaction distribution -system.iobus.trans_dist::ReadResp 150850 # Transaction distribution -system.iobus.trans_dist::WriteReq 29496 # Transaction distribution -system.iobus.trans_dist::WriteResp 29496 # Transaction distribution -system.iobus.trans_dist::MessageReq 903 # Transaction distribution -system.iobus.trans_dist::MessageResp 903 # Transaction distribution +system.iobus.throughput 1276093 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 150466 # Transaction distribution +system.iobus.trans_dist::ReadResp 150466 # Transaction distribution +system.iobus.trans_dist::WriteReq 32862 # Transaction distribution +system.iobus.trans_dist::WriteResp 32862 # Transaction distribution +system.iobus.trans_dist::MessageReq 892 # Transaction distribution +system.iobus.trans_dist::MessageResp 892 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5804 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4556 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287488 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 552 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 500 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15072 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14980 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 312334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 48358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 48358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1806 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1806 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 362498 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 310648 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 56008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 56008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1784 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1784 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 368440 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3277 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2572 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 17 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143595 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1000 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7490 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 160445 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1536536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1536536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1700593 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6549885 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2124548 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 159467 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1782176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1782176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1945211 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6556491 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2113460 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4801000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 3772000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143745000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143596000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 436000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 394000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11266000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11170000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 213288448 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 248070339 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 306278000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 305066000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 29307500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 32957751 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 903000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 892000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1216464910 # number of cpu cycles simulated +system.cpu0.numCycles 1184263733 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71961421 # Number of instructions committed -system.cpu0.committedOps 146368954 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134434152 # Number of integer alu accesses +system.cpu0.committedInsts 72124506 # Number of instructions committed +system.cpu0.committedOps 146682326 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134713165 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 983451 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14191112 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134434152 # number of integer instructions +system.cpu0.num_func_calls 981373 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14229217 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134713165 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 247103574 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115380288 # number of times the integer registers were written +system.cpu0.num_int_register_reads 247622256 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115606613 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83614520 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55784493 # number of times the CC registers were written -system.cpu0.num_mem_refs 14023782 # number of memory refs -system.cpu0.num_load_insts 10248970 # Number of load instructions -system.cpu0.num_store_insts 3774812 # Number of store instructions -system.cpu0.num_idle_cycles 1155422884.085227 # Number of idle cycles -system.cpu0.num_busy_cycles 61042025.914772 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050180 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949820 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 83816060 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55907358 # number of times the CC registers were written +system.cpu0.num_mem_refs 14049102 # number of memory refs +system.cpu0.num_load_insts 10253492 # Number of load instructions +system.cpu0.num_store_insts 3795610 # Number of store instructions +system.cpu0.num_idle_cycles 1123870108.492543 # Number of idle cycles +system.cpu0.num_busy_cycles 60393624.507457 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050997 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949003 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 853207 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.801369 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129244758 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 853719 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 151.390279 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147441059000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 310.509377 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 127.091120 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 73.200872 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.606464 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.248225 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.142970 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997659 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 87593978 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38906796 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2743984 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129244758 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87593978 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38906796 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2743984 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129244758 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87593978 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38906796 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2743984 # number of overall hits -system.cpu0.icache.overall_hits::total 129244758 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 340722 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 154167 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 378624 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 873513 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 340722 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 154167 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 378624 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 873513 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 340722 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 154167 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 378624 # number of overall misses -system.cpu0.icache.overall_misses::total 873513 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2138351750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5548047899 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7686399649 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2138351750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5548047899 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7686399649 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2138351750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5548047899 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7686399649 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87934700 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39060963 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3122608 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130118271 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87934700 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39060963 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3122608 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130118271 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87934700 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39060963 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3122608 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130118271 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003875 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003947 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121252 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006713 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003875 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003947 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121252 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006713 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003875 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003947 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121252 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006713 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13870.359740 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14653.186008 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8799.410712 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8799.410712 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8799.410712 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6480 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 848510 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.789516 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129618382 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 849022 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 152.667872 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147463418500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 302.993641 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 130.368033 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 77.427843 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.591784 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.254625 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.151226 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997636 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 87771297 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 39145197 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2701888 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129618382 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87771297 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 39145197 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2701888 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129618382 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87771297 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 39145197 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2701888 # number of overall hits +system.cpu0.icache.overall_hits::total 129618382 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 353389 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 157925 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 356099 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 867413 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 353389 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 157925 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 356099 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 867413 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 353389 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 157925 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 356099 # number of overall misses +system.cpu0.icache.overall_misses::total 867413 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2216316250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5093590204 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7309906454 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2216316250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5093590204 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7309906454 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2216316250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5093590204 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7309906454 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 88124686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39303122 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3057987 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130485795 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 88124686 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39303122 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3057987 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130485795 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 88124686 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39303122 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3057987 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130485795 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004010 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004018 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116449 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006648 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004010 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004018 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116449 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006648 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004010 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004018 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116449 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006648 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14033.979737 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14303.859893 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8427.250288 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8427.250288 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8427.250288 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4049 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 236 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.887967 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.156780 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 19783 # 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number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 358841 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 513008 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1829084250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4581098483 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6410182733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1829084250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4581098483 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6410182733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1829084250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4581098483 # 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average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 177204 # number of cycles access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 205.523243 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 299.707974 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.766620 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.401413 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.585367 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013216 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5112635 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2556554 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 3831407 # 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miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.197089 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128718 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.039047 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034343 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.037412 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037511 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071890 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.063612 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137399 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.093275 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071890 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063612 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137399 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.093275 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14381.840403 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15985.201248 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10781.404492 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37281.299467 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30788.169660 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17542.647986 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 11838.056851 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11838.056851 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 171453 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11696 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11788 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.150821 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.544706 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1543420 # number of writebacks -system.cpu0.dcache.writebacks::total 1543420 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 365400 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 365400 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 16856 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 16856 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 382256 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 382256 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 382256 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 382256 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231573 # 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number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2821426245 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8425862038 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11247288283 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2033592178 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3216384846 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5249977024 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4855018423 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11642246884 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16497265307 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4855018423 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11642246884 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16497265307 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30662990000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33250431500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63913421500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 506056500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 816755500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1322812000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31169046500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34067187000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65236233500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.084907 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.119506 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061332 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035333 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032681 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018537 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.044713 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044713 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12183.744413 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14542.015719 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13868.624792 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33792.950547 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33699.889420 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33735.876006 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1542501 # number of writebacks +system.cpu0.dcache.writebacks::total 1542501 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 362466 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362466 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17153 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17153 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 379619 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 379619 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 379619 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 379619 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 228350 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 578020 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 806370 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60070 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89425 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 149495 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 288420 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 667445 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 955865 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 288420 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 667445 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 955865 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2826173744 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8314744809 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11140918553 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2108252341 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2905747700 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5014000041 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4934426085 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11220492509 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16154918594 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4934426085 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11220492509 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16154918594 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30636255000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33190282000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63826537000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 532271000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 712236000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1244507000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31168526000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33902518000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65071044000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081996 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121130 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061090 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031391 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017819 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.044275 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.044275 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.499864 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14384.873895 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13816.137199 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35096.592992 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32493.684093 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33539.583538 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1399,306 +1416,306 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606006645 # number of cpu cycles simulated +system.cpu1.numCycles 2606010326 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35315213 # Number of instructions committed -system.cpu1.committedOps 68682433 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63797816 # Number of integer alu accesses +system.cpu1.committedInsts 35502902 # Number of instructions committed +system.cpu1.committedOps 69019443 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64128875 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 457734 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6497995 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63797816 # number of integer instructions +system.cpu1.num_func_calls 466888 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6511590 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64128875 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 117816925 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55078781 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118555351 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55341107 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36195960 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26980721 # number of times the CC registers were written -system.cpu1.num_mem_refs 4621452 # number of memory refs -system.cpu1.num_load_insts 2916499 # Number of load instructions -system.cpu1.num_store_insts 1704953 # Number of store instructions -system.cpu1.num_idle_cycles 2477007170.096548 # Number of idle cycles -system.cpu1.num_busy_cycles 128999474.903452 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049501 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950499 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 36337345 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27074895 # number of times the CC registers were written +system.cpu1.num_mem_refs 4724906 # number of memory refs +system.cpu1.num_load_insts 2973846 # Number of load instructions +system.cpu1.num_store_insts 1751060 # Number of store instructions +system.cpu1.num_idle_cycles 2477242501.972853 # Number of idle cycles +system.cpu1.num_busy_cycles 128767824.027147 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049412 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950588 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28832932 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28832932 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 311283 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26470595 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25835663 # Number of BTB hits +system.cpu2.branchPred.lookups 28668505 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28668505 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 293936 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26313496 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25716329 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.601369 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 539109 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63758 # Number of incorrect RAS predictions. -system.cpu2.numCycles 156318365 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.730568 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 531231 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 59742 # Number of incorrect RAS predictions. +system.cpu2.numCycles 154176343 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9648571 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142153316 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28832932 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26374772 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54477061 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1438031 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 74339 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 25017392 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 3513 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6379 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 22688 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3122610 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 142940 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 90361689 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.101501 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.407201 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9183670 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 141279801 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28668505 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26247560 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54165747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1372429 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 60595 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 24017130 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 2633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7414 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 19025 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3057990 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 134510 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1720 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 88520588 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.147296 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.411069 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 36017869 39.86% 39.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 584325 0.65% 40.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23803917 26.34% 66.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 312236 0.35% 67.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 599559 0.66% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 810629 0.90% 68.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 333254 0.37% 69.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 522143 0.58% 69.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27377757 30.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 34483261 38.96% 38.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 569039 0.64% 39.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23712203 26.79% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 303942 0.34% 66.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 596203 0.67% 67.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 791828 0.89% 68.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 321684 0.36% 68.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 518300 0.59% 69.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27224128 30.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 90361689 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.184450 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.909383 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 11120847 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 23921754 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 35744474 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1291324 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1114642 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 279457828 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 12 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1114642 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12111653 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14421944 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4371925 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 35874443 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5298501 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278479903 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 7178 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2457632 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2167618 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 332694530 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605890178 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 372281709 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 54 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 322791874 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9902651 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 146965 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 147763 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11459312 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6166984 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3428654 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 344111 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 288647 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276817235 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 412713 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 275284943 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 59120 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6994425 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10714687 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 55194 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 90361689 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.046479 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.402703 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 88520588 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185946 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.916352 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10629848 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 22917593 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 30946726 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1286674 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1067388 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 277843876 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 5 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1067388 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11607450 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13707721 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4125990 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 31086433 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5253313 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 276918591 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6816 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2458805 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2129053 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 330941436 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 602250525 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 370032440 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321416172 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 9525262 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 139074 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 139963 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11350220 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6069912 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3334552 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 325084 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 284462 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275324678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 401766 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273874447 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 58026 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 6719880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10332541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 51920 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 88520588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.093907 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.392477 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 26846835 29.71% 29.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6154250 6.81% 36.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3929000 4.35% 40.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2711977 3.00% 43.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25114660 27.79% 71.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1340428 1.48% 73.15% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23928680 26.48% 99.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 282970 0.31% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 52889 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 25429283 28.73% 28.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6033030 6.82% 35.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3870306 4.37% 39.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2690716 3.04% 42.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25010151 28.25% 71.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1323131 1.49% 72.70% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23827077 26.92% 99.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 285216 0.32% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 51678 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 90361689 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 88520588 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 125502 33.84% 33.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 241 0.06% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 190694 51.42% 85.33% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 54418 14.67% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 120453 33.21% 33.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 124 0.03% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 190037 52.39% 85.63% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 52134 14.37% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 78208 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 265424287 96.42% 96.45% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56044 0.02% 96.47% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 46278 0.02% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6463688 2.35% 98.83% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3216438 1.17% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 69880 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264196051 96.47% 96.49% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 53857 0.02% 96.51% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 45427 0.02% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.53% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6378380 2.33% 98.86% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3130852 1.14% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 275284943 # Type of FU issued -system.cpu2.iq.rate 1.761053 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 370855 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001347 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 641401400 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284227989 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273934511 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 90 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 102 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 273874447 # Type of FU issued +system.cpu2.iq.rate 1.776371 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 362748 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001325 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 636728050 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 282449613 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272560977 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 75 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275577549 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 41 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 638960 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 274167280 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 35 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 638144 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 974310 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6664 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4257 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 503319 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 933920 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 7005 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3826 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 481474 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656257 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10390 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656274 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10618 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1114642 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9684851 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 815798 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277229948 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 71784 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6166984 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3428654 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 232570 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 630862 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4638 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4257 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 175308 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 177843 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 353151 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 274790127 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6353973 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 494815 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9024497 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 812904 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275726444 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 67814 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6069912 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3334552 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 224273 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 631637 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3885 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3826 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 167894 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 164610 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 332504 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273407129 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6276348 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 467317 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9504896 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27944071 # Number of branches executed -system.cpu2.iew.exec_stores 3150923 # Number of stores executed -system.cpu2.iew.exec_rate 1.757888 # Inst execution rate -system.cpu2.iew.wb_sent 274642284 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273934533 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213583516 # num instructions producing a value -system.cpu2.iew.wb_consumers 349233536 # num instructions consuming a value +system.cpu2.iew.exec_refs 9343774 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27815177 # Number of branches executed +system.cpu2.iew.exec_stores 3067426 # Number of stores executed +system.cpu2.iew.exec_rate 1.773340 # Inst execution rate +system.cpu2.iew.wb_sent 273265355 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272560999 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212629872 # num instructions producing a value +system.cpu2.iew.wb_consumers 347702126 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.752414 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611578 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.767852 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611529 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7294558 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357518 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 313650 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 89247046 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.024569 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.872131 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7002811 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 349846 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 295934 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 87453200 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.072767 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.870996 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 31615758 35.42% 35.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4405793 4.94% 40.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1230871 1.38% 41.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24727866 27.71% 69.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 857199 0.96% 70.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 581394 0.65% 71.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 343629 0.39% 71.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23391082 26.21% 97.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2093454 2.35% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 30168588 34.50% 34.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4310788 4.93% 39.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1198483 1.37% 40.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24616834 28.15% 68.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 847666 0.97% 69.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 576601 0.66% 70.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 339942 0.39% 70.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23302626 26.65% 97.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2091672 2.39% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 89247046 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136718686 # Number of instructions committed -system.cpu2.commit.committedOps 269933879 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 87453200 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136077774 # Number of instructions committed +system.cpu2.commit.committedOps 268723335 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8118007 # Number of memory references committed -system.cpu2.commit.loads 5192672 # Number of loads committed -system.cpu2.commit.membars 165488 # Number of memory barriers committed -system.cpu2.commit.branches 27614013 # Number of branches committed +system.cpu2.commit.refs 7989069 # Number of memory references committed +system.cpu2.commit.loads 5135991 # Number of loads committed +system.cpu2.commit.membars 163538 # Number of memory barriers committed +system.cpu2.commit.branches 27499066 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 246437097 # Number of committed integer instructions. -system.cpu2.commit.function_calls 432570 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2093454 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 245318960 # Number of committed integer instructions. +system.cpu2.commit.function_calls 428759 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2091672 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 364355237 # The number of ROB reads -system.cpu2.rob.rob_writes 555575410 # The number of ROB writes -system.cpu2.timesIdled 476451 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65956676 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4907452688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136718686 # Number of Instructions Simulated -system.cpu2.committedOps 269933879 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136718686 # Number of Instructions Simulated -system.cpu2.cpi 1.143358 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.143358 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.874617 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.874617 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 365607519 # number of integer regfile reads -system.cpu2.int_regfile_writes 219416427 # number of integer regfile writes +system.cpu2.rob.rob_reads 361063162 # The number of ROB reads +system.cpu2.rob.rob_writes 552523197 # The number of ROB writes +system.cpu2.timesIdled 466136 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65655755 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4909695924 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136077774 # Number of Instructions Simulated +system.cpu2.committedOps 268723335 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 136077774 # Number of Instructions Simulated +system.cpu2.cpi 1.133002 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.133002 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.882611 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.882611 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363659019 # number of integer regfile reads +system.cpu2.int_regfile_writes 218348978 # number of integer regfile writes system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139623375 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107543298 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89002893 # number of misc regfile reads -system.cpu2.misc_regfile_writes 130765 # number of misc regfile writes +system.cpu2.cc_regfile_reads 138971726 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107072573 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88484504 # number of misc regfile reads +system.cpu2.misc_regfile_writes 124462 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |