diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 2417 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini | 46 |
2 files changed, 1241 insertions, 1222 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 0f19127f8..fdc0fba9d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125948 # Number of seconds simulated -sim_ticks 5125948496500 # Number of ticks simulated -final_tick 5125948496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.129943 # Number of seconds simulated +sim_ticks 5129943020500 # Number of ticks simulated +final_tick 5129943020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181287 # Simulator instruction rate (inst/s) -host_op_rate 358347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2277524092 # Simulator tick rate (ticks/s) -host_mem_usage 808864 # Number of bytes of host memory used -host_seconds 2250.67 # Real time elapsed on the host -sim_insts 408017153 # Number of instructions simulated -sim_ops 806519171 # Number of ops (including micro ops) simulated +host_inst_rate 121408 # Simulator instruction rate (inst/s) +host_op_rate 239988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1526556123 # Simulator tick rate (ticks/s) +host_mem_usage 798272 # Number of bytes of host memory used +host_seconds 3360.47 # Real time elapsed on the host +sim_insts 407987808 # Number of instructions simulated +sim_ops 806471132 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1048640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10814912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1049088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10796544 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11896448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1048640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1048640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9598912 # Number of bytes written to this memory -system.physmem.bytes_written::total 9598912 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16385 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168983 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11878656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1049088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1049088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9594624 # Number of bytes written to this memory +system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 68 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16392 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168696 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185882 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149983 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149983 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2109836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2320829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1872612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1872612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1872612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2109836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4193440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185882 # Number of read requests accepted -system.physmem.writeReqs 196703 # Number of write requests accepted -system.physmem.readBursts 185882 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196703 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11884864 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue -system.physmem.bytesWritten 12459008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11896448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12588992 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2006 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1725 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11442 # Per bank write bursts -system.physmem.perBankRdBursts::1 11010 # Per bank write bursts -system.physmem.perBankRdBursts::2 11990 # Per bank write bursts -system.physmem.perBankRdBursts::3 11673 # Per bank write bursts -system.physmem.perBankRdBursts::4 12100 # Per bank write bursts -system.physmem.perBankRdBursts::5 11243 # Per bank write bursts -system.physmem.perBankRdBursts::6 11527 # Per bank write bursts -system.physmem.perBankRdBursts::7 11544 # Per bank write bursts -system.physmem.perBankRdBursts::8 11275 # Per bank write bursts -system.physmem.perBankRdBursts::9 11901 # Per bank write bursts -system.physmem.perBankRdBursts::10 11758 # Per bank write bursts -system.physmem.perBankRdBursts::11 11788 # Per bank write bursts -system.physmem.perBankRdBursts::12 11617 # Per bank write bursts -system.physmem.perBankRdBursts::13 12244 # Per bank write bursts -system.physmem.perBankRdBursts::14 11799 # Per bank write bursts -system.physmem.perBankRdBursts::15 10790 # Per bank write bursts -system.physmem.perBankWrBursts::0 14290 # Per bank write bursts -system.physmem.perBankWrBursts::1 13466 # Per bank write bursts -system.physmem.perBankWrBursts::2 12356 # Per bank write bursts -system.physmem.perBankWrBursts::3 11306 # Per bank write bursts -system.physmem.perBankWrBursts::4 11781 # Per bank write bursts -system.physmem.perBankWrBursts::5 11472 # Per bank write bursts -system.physmem.perBankWrBursts::6 11444 # Per bank write bursts -system.physmem.perBankWrBursts::7 11849 # Per bank write bursts -system.physmem.perBankWrBursts::8 11105 # Per bank write bursts -system.physmem.perBankWrBursts::9 11337 # Per bank write bursts -system.physmem.perBankWrBursts::10 12902 # Per bank write bursts -system.physmem.perBankWrBursts::11 12297 # Per bank write bursts -system.physmem.perBankWrBursts::12 12359 # Per bank write bursts -system.physmem.perBankWrBursts::13 12104 # Per bank write bursts -system.physmem.perBankWrBursts::14 12504 # Per bank write bursts -system.physmem.perBankWrBursts::15 12100 # Per bank write bursts +system.physmem.num_reads::total 185604 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149916 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 204503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2104613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2315553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 204503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 204503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1870318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1870318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1870318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 204503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2104613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4185871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185604 # Number of read requests accepted +system.physmem.writeReqs 196636 # Number of write requests accepted +system.physmem.readBursts 185604 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 196636 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11865664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12992 # Total number of bytes read from write queue +system.physmem.bytesWritten 12442240 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11878656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12584704 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 203 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2199 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1712 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11483 # Per bank write bursts +system.physmem.perBankRdBursts::1 10958 # Per bank write bursts +system.physmem.perBankRdBursts::2 11903 # Per bank write bursts +system.physmem.perBankRdBursts::3 11497 # Per bank write bursts +system.physmem.perBankRdBursts::4 11986 # Per bank write bursts +system.physmem.perBankRdBursts::5 11369 # Per bank write bursts +system.physmem.perBankRdBursts::6 11563 # Per bank write bursts +system.physmem.perBankRdBursts::7 11462 # Per bank write bursts +system.physmem.perBankRdBursts::8 11178 # Per bank write bursts +system.physmem.perBankRdBursts::9 11812 # Per bank write bursts +system.physmem.perBankRdBursts::10 11732 # Per bank write bursts +system.physmem.perBankRdBursts::11 11823 # Per bank write bursts +system.physmem.perBankRdBursts::12 11783 # Per bank write bursts +system.physmem.perBankRdBursts::13 12309 # Per bank write bursts +system.physmem.perBankRdBursts::14 11732 # Per bank write bursts +system.physmem.perBankRdBursts::15 10811 # Per bank write bursts +system.physmem.perBankWrBursts::0 14023 # Per bank write bursts +system.physmem.perBankWrBursts::1 13077 # Per bank write bursts +system.physmem.perBankWrBursts::2 12485 # Per bank write bursts +system.physmem.perBankWrBursts::3 11134 # Per bank write bursts +system.physmem.perBankWrBursts::4 11942 # Per bank write bursts +system.physmem.perBankWrBursts::5 11710 # Per bank write bursts +system.physmem.perBankWrBursts::6 11692 # Per bank write bursts +system.physmem.perBankWrBursts::7 11673 # Per bank write bursts +system.physmem.perBankWrBursts::8 11519 # Per bank write bursts +system.physmem.perBankWrBursts::9 11764 # Per bank write bursts +system.physmem.perBankWrBursts::10 12914 # Per bank write bursts +system.physmem.perBankWrBursts::11 11938 # Per bank write bursts +system.physmem.perBankWrBursts::12 12257 # Per bank write bursts +system.physmem.perBankWrBursts::13 11913 # Per bank write bursts +system.physmem.perBankWrBursts::14 12398 # Per bank write bursts +system.physmem.perBankWrBursts::15 11971 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5125948445000 # Total gap between requests +system.physmem.totGap 5129942968500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185882 # Read request sizes (log2) +system.physmem.readPktSize::6 185604 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196703 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.writePktSize::6 196636 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170730 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2018 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see @@ -156,322 +156,323 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 11014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 11539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 13007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 14095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 13776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.488559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.903299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.428888 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27891 37.06% 37.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17298 22.99% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7596 10.09% 70.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4208 5.59% 75.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3159 4.20% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2000 2.66% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1345 1.79% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1163 1.55% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10594 14.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75254 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7808 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.780866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.702276 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7807 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 75289 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.860444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.432072 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.383638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27971 37.15% 37.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17364 23.06% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7569 10.05% 70.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4193 5.57% 75.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3123 4.15% 79.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1949 2.59% 82.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1359 1.81% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1178 1.56% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10583 14.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75289 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7789 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.801643 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 545.365861 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7788 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7808 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.932377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.361157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.539970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6379 81.70% 81.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 49 0.63% 82.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 9 0.12% 82.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 259 3.32% 85.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 187 2.39% 88.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 0.68% 88.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 34 0.44% 89.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 61 0.78% 90.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 178 2.28% 92.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.24% 92.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.17% 92.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.18% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 27 0.35% 93.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.24% 93.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 50 0.64% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 97 1.24% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.10% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 20 0.26% 95.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 156 2.00% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 7 0.09% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 10 0.13% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 29 0.37% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.14% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.05% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.20% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 10 0.13% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.08% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.09% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 11 0.14% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 10 0.13% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7789 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7789 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.959558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.372117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.594707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6350 81.53% 81.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 59 0.76% 82.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 17 0.22% 82.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 286 3.67% 86.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 164 2.11% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 59 0.76% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.53% 89.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 34 0.44% 90.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 175 2.25% 92.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.21% 92.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 16 0.21% 92.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.17% 92.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 28 0.36% 93.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 16 0.21% 93.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.13% 93.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 42 0.54% 94.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 108 1.39% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.12% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 9 0.12% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 24 0.31% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 141 1.81% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 13 0.17% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.05% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 34 0.44% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 10 0.13% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.18% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.06% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.17% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 10 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.08% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 11 0.14% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.04% 99.58% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 7 0.09% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 4 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7808 # Writes before turning the bus around for reads -system.physmem.totQLat 1993300749 # Total ticks spent queuing -system.physmem.totMemAccLat 5475194499 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 928505000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10733.93 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 6 0.08% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7789 # Writes before turning the bus around for reads +system.physmem.totQLat 1998636250 # Total ticks spent queuing +system.physmem.totMemAccLat 5474905000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 927005000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10780.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29483.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29530.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.46 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.04 # Average write queue length when enqueuing -system.physmem.readRowHits 152642 # Number of row buffer hits during reads -system.physmem.writeRowHits 152476 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.31 # Row buffer hit rate for writes -system.physmem.avgGap 13398195.03 # Average gap between requests -system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 279704880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 152616750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 721718400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 634806720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129444104115 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2962019880750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3428054662095 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.765327 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4927513863750 # Time in different power states -system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.71 # Average write queue length when enqueuing +system.physmem.readRowHits 152292 # Number of row buffer hits during reads +system.physmem.writeRowHits 152229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.29 # Row buffer hit rate for writes +system.physmem.avgGap 13420738.20 # Average gap between requests +system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 279697320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 152612625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 719316000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 633329280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129572750835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2964303640500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3430724068320 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.764961 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4931314948000 # Time in different power states +system.physmem_0.memoryStateTime::REF 171299960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27267949750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27328009000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 289215360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 157806000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 726741600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 626667840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129734124390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2961765477000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3428101862670 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.774535 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4927089550750 # Time in different power states -system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem_1.actEnergy 289487520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 157954500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 726804000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 626447520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129789266760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2964113714250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3430766396310 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.773213 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4930997374750 # Time in different power states +system.physmem_1.memoryStateTime::REF 171299960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27689450500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27642592750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86963954 # Number of BP lookups -system.cpu.branchPred.condPredicted 86963954 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 905408 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80060833 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78220075 # Number of BTB hits +system.cpu.branchPred.lookups 86966196 # Number of BP lookups +system.cpu.branchPred.condPredicted 86966196 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 908530 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80060297 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78222813 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.700801 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1554669 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 179026 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.704875 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1554803 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179885 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449722784 # number of cpu cycles simulated +system.cpu.numCycles 449725865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27725020 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429300438 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86963954 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79774744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 417978242 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1899598 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 143976 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 49214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 212054 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 124897 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 365 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9198894 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 449574 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4910 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 447183567 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894463 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.051838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27729826 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429316628 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86966196 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79777616 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417943861 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1905694 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 153883 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 50061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 216755 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 126625 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 694 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9209956 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 450181 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5437 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 447174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.894587 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.051890 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281562684 62.96% 62.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2296710 0.51% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72185404 16.14% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1608090 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2152491 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2328628 0.52% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1534045 0.34% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1900420 0.42% 81.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81615095 18.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281545500 62.96% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2299594 0.51% 63.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72183543 16.14% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1609599 0.36% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2153830 0.48% 80.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2329535 0.52% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1534724 0.34% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1901427 0.43% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81616800 18.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 447183567 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193372 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954589 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23075597 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264910108 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150816162 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7431901 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 949799 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838865197 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 949799 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25926245 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223342995 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13219671 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154710115 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29034742 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 835373495 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 478818 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12412845 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 182552 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13765619 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997850152 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1814454577 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1115386152 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 142 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964539686 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33310464 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468855 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 472576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39019315 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17353635 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10197147 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1310615 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1095058 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829813890 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1210662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824509848 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 239912 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23585262 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36379120 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 154680 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 447183567 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.843784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418075 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 447174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193376 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954618 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23090202 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264882686 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150813511 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7435306 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 952847 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838903899 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 952847 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25942831 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 223326641 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13232428 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154708804 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29011001 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 835406292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 477425 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12418228 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 176585 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 13740194 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997876395 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1814508658 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1115444420 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 102 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964480017 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33396376 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469202 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 473127 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 39031385 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17359783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10198929 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1317086 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1098616 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829832373 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1210818 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824505871 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 240863 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23642425 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36460999 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 154878 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 447174552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843812 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418056 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262867260 58.78% 58.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13875410 3.10% 61.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10102524 2.26% 64.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6917845 1.55% 65.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74366987 16.63% 82.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4460507 1.00% 83.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72819289 16.28% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1200322 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 573423 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262851560 58.78% 58.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13883927 3.10% 61.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10098896 2.26% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6926055 1.55% 65.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74362880 16.63% 82.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4459374 1.00% 83.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72818710 16.28% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1199863 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 573287 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 447183567 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 447174552 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1986412 71.97% 71.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 252 0.01% 71.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1233 0.04% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 612541 22.19% 94.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159591 5.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1983031 71.93% 71.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 252 0.01% 71.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1287 0.05% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 612199 22.21% 94.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160068 5.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 292966 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796097417 96.55% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150721 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125468 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 294191 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796088573 96.55% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150664 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125614 0.02% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued @@ -498,98 +499,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18437939 2.24% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9405337 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18441786 2.24% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9405043 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824509848 # Type of FU issued -system.cpu.iq.rate 1.833374 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2760029 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003347 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2099202980 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854622338 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819935754 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826976810 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1879265 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824505871 # Type of FU issued +system.cpu.iq.rate 1.833352 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2756837 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003344 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2099183812 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854698119 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819923286 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 181 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826968435 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1878873 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3349902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15405 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14537 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1763571 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3357342 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15595 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14483 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1769318 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224753 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72078 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2224742 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 72242 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 949799 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205606066 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9444034 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831024552 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 186671 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17353635 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10197147 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 713788 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 414805 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8129418 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14537 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 518368 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 539118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1057486 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822883825 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18037381 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1492626 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 952847 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205624678 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9408932 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831043191 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 186605 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17359783 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10198929 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 713805 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 415277 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8093737 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14483 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 519848 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 541033 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1060881 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822872781 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18039155 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1498773 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27216272 # number of memory reference insts executed -system.cpu.iew.exec_branches 83330623 # Number of branches executed -system.cpu.iew.exec_stores 9178891 # Number of stores executed -system.cpu.iew.exec_rate 1.829758 # Inst execution rate -system.cpu.iew.wb_sent 822374066 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819935816 # cumulative count of insts written-back -system.cpu.iew.wb_producers 641195588 # num instructions producing a value -system.cpu.iew.wb_consumers 1050795800 # num instructions consuming a value +system.cpu.iew.exec_refs 27216659 # number of memory reference insts executed +system.cpu.iew.exec_branches 83327917 # Number of branches executed +system.cpu.iew.exec_stores 9177504 # Number of stores executed +system.cpu.iew.exec_rate 1.829721 # Inst execution rate +system.cpu.iew.wb_sent 822362005 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819923336 # cumulative count of insts written-back +system.cpu.iew.wb_producers 641186937 # num instructions producing a value +system.cpu.iew.wb_consumers 1050770759 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610200 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610206 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24410170 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1055982 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 917776 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443513895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818476 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675053 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24478012 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1055940 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 920864 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443494014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818449 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675035 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272662791 61.48% 61.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11205596 2.53% 64.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3584252 0.81% 64.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74566158 16.81% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2433850 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1609395 0.36% 82.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 952580 0.21% 82.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71045442 16.02% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5453831 1.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272650089 61.48% 61.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11209358 2.53% 64.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3583153 0.81% 64.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74560256 16.81% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2436163 0.55% 82.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1608243 0.36% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 951229 0.21% 82.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71042725 16.02% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5452798 1.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443513895 # Number of insts commited each cycle -system.cpu.commit.committedInsts 408017153 # Number of instructions committed -system.cpu.commit.committedOps 806519171 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443494014 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407987808 # Number of instructions committed +system.cpu.commit.committedOps 806471132 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22437308 # Number of memory references committed -system.cpu.commit.loads 14003732 # Number of loads committed -system.cpu.commit.membars 475345 # Number of memory barriers committed -system.cpu.commit.branches 82208289 # Number of branches committed +system.cpu.commit.refs 22432051 # Number of memory references committed +system.cpu.commit.loads 14002440 # Number of loads committed +system.cpu.commit.membars 475347 # Number of memory barriers committed +system.cpu.commit.branches 82201961 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735327062 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156001 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174296 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783640915 97.16% 97.18% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 145051 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121601 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735281139 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155976 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174273 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783598184 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 145019 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -616,167 +617,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 14003732 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8433576 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14002440 1.74% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8429611 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806519171 # Class of committed instruction -system.cpu.commit.bw_lim_events 5453831 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806471132 # Class of committed instruction +system.cpu.commit.bw_lim_events 5452798 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1268911189 # The number of ROB reads -system.cpu.rob.rob_writes 1665544826 # The number of ROB writes -system.cpu.timesIdled 297395 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2539217 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9802174458 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 408017153 # Number of Instructions Simulated -system.cpu.committedOps 806519171 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.102215 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.102215 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907264 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907264 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092796597 # number of integer regfile reads -system.cpu.int_regfile_writes 656284247 # number of integer regfile writes -system.cpu.fp_regfile_reads 62 # number of floating regfile reads -system.cpu.cc_regfile_reads 416355955 # number of cc regfile reads -system.cpu.cc_regfile_writes 322152728 # number of cc regfile writes -system.cpu.misc_regfile_reads 265715662 # number of misc regfile reads -system.cpu.misc_regfile_writes 402877 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1660514 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996956 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19150908 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1661026 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.529565 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1268912158 # The number of ROB reads +system.cpu.rob.rob_writes 1665595320 # The number of ROB writes +system.cpu.timesIdled 297665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2551313 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9810160420 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407987808 # Number of Instructions Simulated +system.cpu.committedOps 806471132 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.102302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.102302 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907192 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907192 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092777925 # number of integer regfile reads +system.cpu.int_regfile_writes 656276714 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.cc_regfile_reads 416321461 # number of cc regfile reads +system.cpu.cc_regfile_writes 322134346 # number of cc regfile writes +system.cpu.misc_regfile_reads 265712042 # number of misc regfile reads +system.cpu.misc_regfile_writes 402822 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1660901 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996168 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19148306 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1661413 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.525314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996956 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996168 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88414778 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88414778 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10992291 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10992291 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8090245 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8090245 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 65628 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 65628 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19082536 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19082536 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19148164 # number of overall hits -system.cpu.dcache.overall_hits::total 19148164 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1800200 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1800200 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 333674 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 333674 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406398 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406398 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2133874 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2133874 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2540272 # number of overall misses -system.cpu.dcache.overall_misses::total 2540272 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26575138519 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26575138519 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12884484816 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12884484816 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39459623335 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39459623335 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39459623335 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39459623335 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12792491 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12792491 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8423919 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8423919 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 472026 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 472026 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21216410 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21216410 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21688436 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21688436 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140723 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.140723 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039610 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039610 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.860965 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.860965 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100577 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100577 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117126 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117126 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14762.325585 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14762.325585 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38613.990949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38613.990949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 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-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.307314 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.384594 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1561114 # number of writebacks -system.cpu.dcache.writebacks::total 1561114 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829484 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 829484 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44098 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44098 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 873582 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 873582 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 873582 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 873582 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970716 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 970716 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289576 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402937 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402937 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1260292 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1260292 # number of demand (read+write) MSHR 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demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29068213412 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29068213412 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390347000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390347000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564142000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564142000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954489000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954489000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853633 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853633 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059402 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059402 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076687 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076687 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12628.891471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12628.891471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38737.787807 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38737.787807 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.138999 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.138999 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18627.905799 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18627.905799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17476.976058 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17476.976058 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1561149 # number of writebacks +system.cpu.dcache.writebacks::total 1561149 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829563 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 829563 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44151 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44151 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 873714 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 873714 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 873714 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 873714 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971447 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 971447 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289242 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289242 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402941 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402941 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1260689 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1260689 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1663630 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1663630 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12263679766 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12263679766 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11196249664 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11196249664 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5590634504 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5590634504 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459929430 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23459929430 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050563934 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29050563934 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390328000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390328000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564382000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564382000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954710000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954710000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034352 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034352 # mshr miss rate for WriteReq accesses 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mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13874.573459 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13874.573459 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18608.815838 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18608.815838 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17462.154406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17462.154406 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -784,58 +785,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 73235 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.785723 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 116281 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 73250 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.587454 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.replacements 74149 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.785870 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 117599 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 74165 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.585640 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.tags.warmup_cycle 219591309000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785723 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986608 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986608 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 455451 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 455451 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116283 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 116283 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116283 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 116283 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116283 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 116283 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74295 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 74295 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74295 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 74295 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74295 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 74295 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 915742192 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 915742192 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 915742192 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 915742192 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 915742192 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 915742192 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190578 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 190578 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190578 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 190578 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190578 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 190578 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389840 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389840 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389840 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389840 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389840 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389840 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12325.758019 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12325.758019 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12325.758019 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12325.758019 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12325.758019 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12325.758019 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785870 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986617 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986617 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 460921 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 460921 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 117599 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 117599 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 117599 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 117599 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 117599 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 117599 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75241 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 75241 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75241 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 75241 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75241 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 75241 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935995702 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935995702 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935995702 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 935995702 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935995702 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 935995702 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192840 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 192840 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192840 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 192840 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192840 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 192840 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.390173 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.390173 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.390173 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.390173 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.390173 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.390173 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12439.968927 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12439.968927 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12439.968927 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12439.968927 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -844,180 +845,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 20236 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 20236 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74295 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74295 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74295 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 74295 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74295 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 74295 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 767004478 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 767004478 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 767004478 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 767004478 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 767004478 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 767004478 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389840 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389840 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389840 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10323.769810 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10323.769810 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10323.769810 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 14429 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 14429 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75241 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75241 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75241 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 75241 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75241 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 75241 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 785378468 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 785378468 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 785378468 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 785378468 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 785378468 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 785378468 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.390173 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.390173 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.390173 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10438.171582 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1000725 # number of replacements -system.cpu.icache.tags.tagsinuse 510.147155 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8133580 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1001237 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.123531 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1000738 # number of replacements +system.cpu.icache.tags.tagsinuse 509.865289 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8144093 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1001250 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.133926 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 147645528250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.147155 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996381 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996381 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 509.865289 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995831 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995831 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 178 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10200177 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10200177 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8133580 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8133580 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8133580 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8133580 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8133580 # number of overall hits -system.cpu.icache.overall_hits::total 8133580 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065313 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065313 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065313 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065313 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065313 # number of overall misses -system.cpu.icache.overall_misses::total 1065313 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14771324125 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14771324125 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14771324125 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14771324125 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14771324125 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14771324125 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9198893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9198893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9198893 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9198893 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9198893 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9198893 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115809 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115809 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115809 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115809 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115809 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115809 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.712823 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13865.712823 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.712823 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13865.712823 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.712823 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13865.712823 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6681 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10211253 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10211253 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8144093 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8144093 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8144093 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8144093 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8144093 # number of overall hits +system.cpu.icache.overall_hits::total 8144093 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1065861 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065861 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1065861 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1065861 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1065861 # number of overall misses +system.cpu.icache.overall_misses::total 1065861 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14781190073 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14781190073 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14781190073 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14781190073 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14781190073 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14781190073 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9209954 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9209954 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9209954 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9209954 # number of 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13867.840247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13867.840247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13867.840247 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8856 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 268 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 270 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.929104 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 32.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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-system.cpu.icache.demand_mshr_misses::total 1001284 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1001284 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1001284 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12122903243 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12122903243 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12122903243 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12122903243 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12122903243 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12122903243 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108848 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108848 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108848 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108848 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108848 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108848 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12107.357396 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12107.357396 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12107.357396 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12107.357396 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12107.357396 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12107.357396 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 64562 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 64562 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 64562 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 64562 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 64562 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 64562 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001299 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1001299 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1001299 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1001299 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1001299 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1001299 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12129331538 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12129331538 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12129331538 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12129331538 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12129331538 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12129331538 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108719 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108719 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108719 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108719 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.595977 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.595977 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.595977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.595977 # average overall mshr miss latency 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-system.cpu.itb_walker_cache.tags.occ_percent::total 0.375988 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 16111 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.022557 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 25852 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 16125 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.603225 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5103942671000 # Cycle when the warmup percentage was hit. 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-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26674 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26674 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 102724 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 102724 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25863 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25863 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26676 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26676 # number of demand (read+write) hits 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174774993 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 174774993 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174774993 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 174774993 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41734 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41734 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25865 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25865 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25865 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25865 # number of overall hits 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-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11605.245219 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11605.245219 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11605.245219 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42863 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 42863 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42863 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 42863 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.396584 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.396584 # miss rate for ReadReq accesses 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+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11886.045299 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1026,177 +1027,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2894 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2894 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15060 # number of ReadReq MSHR misses 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-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144633033 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144633033 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.360857 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.360857 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.360840 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.360840 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.360840 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.360840 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9603.787052 # average ReadReq mshr miss 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miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 168025032 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.396584 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.396584 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.396566 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.396566 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9884.988352 # average ReadReq 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per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768821 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000273 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50388.015751 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.441797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125760 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3267.225445 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11145.935958 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768860 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000266 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of 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overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16386 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169930 # number of overall misses -system.cpu.l2cache.overall_misses::total 186387 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6099500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 482500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1248819000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2837713246 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4093114246 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17341312 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17341312 # number of UpgradeReq miss cycles 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miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93838.461538 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80416.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76212.559502 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79133.107808 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 78236.791980 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11861.362517 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11861.362517 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69747.428343 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69747.428343 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93838.461538 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80416.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76212.559502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71728.070170 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72130.309324 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93838.461538 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80416.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76212.559502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71728.070170 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72130.309324 # average overall miss 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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1049607750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10040332785 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11095861285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5576250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 344500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049607750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10040332785 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11095861285 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397352000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397352000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672948500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672948500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021290 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827982 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827982 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.465820 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.465820 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067767 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000976 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000339 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102152 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067767 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68900 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64031.707540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66559.816622 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65788.609152 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10639.489612 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10639.489612 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57203.424796 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57203.424796 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1305,55 +1306,55 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3074514 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3073974 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1584244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3078150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3077612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13891 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13891 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1577834 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287149 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6133560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30509 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162399 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8328931 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64075456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207996475 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 988736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5638656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278699323 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 58087 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4385762 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010862 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103651 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002495 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6134281 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34017 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159331 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8330124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64076544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208017731 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1089216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5381760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278565251 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 57093 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4382652 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010869 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103688 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4338126 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47636 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4335015 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47637 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4385762 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4071958893 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4382652 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4064000382 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 577500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1506070002 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1506120456 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3144166318 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3144694054 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22600980 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 25505983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 111516357 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 112929117 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 225687 # Transaction distribution -system.iobus.trans_dist::ReadResp 225687 # Transaction distribution +system.iobus.trans_dist::ReadReq 225688 # Transaction distribution +system.iobus.trans_dist::ReadResp 225688 # Transaction distribution system.iobus.trans_dist::WriteReq 57721 # Transaction distribution system.iobus.trans_dist::WriteResp 11001 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution @@ -1378,11 +1379,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95274 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95274 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 570104 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 570106 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) @@ -1402,12 +1403,12 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027880 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276506 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) +system.iobus.pkt_size::total 3276514 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3918684 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1443,54 +1444,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448361200 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448342458 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52371753 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52374503 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47581 # number of replacements -system.iocache.tags.tagsinuse 0.091546 # Cycle average of tags in use +system.iocache.tags.replacements 47582 # number of replacements +system.iocache.tags.tagsinuse 0.103930 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47597 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992992715000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091546 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005722 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005722 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992992710000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103930 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006496 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428724 # Number of tag accesses -system.iocache.tags.data_accesses 428724 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses -system.iocache.ReadReq_misses::total 916 # number of ReadReq misses +system.iocache.tags.tag_accesses 428733 # Number of tag accesses +system.iocache.tags.data_accesses 428733 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses +system.iocache.ReadReq_misses::total 917 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses -system.iocache.demand_misses::total 916 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses -system.iocache.overall_misses::total 916 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149161446 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149161446 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12345702001 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12345702001 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 149161446 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 149161446 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 149161446 # number of overall miss cycles -system.iocache.overall_miss_latency::total 149161446 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 917 # number of demand (read+write) misses +system.iocache.demand_misses::total 917 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 917 # number of overall misses +system.iocache.overall_misses::total 917 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152376946 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 152376946 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12347668009 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12347668009 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 152376946 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 152376946 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 152376946 # number of overall miss cycles +system.iocache.overall_miss_latency::total 152376946 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 917 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 917 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 917 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 917 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1499,40 +1500,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162840.006550 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264248.758583 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264248.758583 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 162840.006550 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 162840.006550 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70237 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166168.970556 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264290.839234 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264290.839234 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 166168.970556 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 166168.970556 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70541 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9120 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9150 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.701425 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.709399 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 101504946 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9916256007 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9916256007 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 101504946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 101504946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 917 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 917 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 917 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 917 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104665946 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918222015 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918222015 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 104665946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 104665946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1541,75 +1542,75 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110813.259825 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212248.630287 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212248.630287 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114139.526718 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212290.710938 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212290.710938 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 662646 # Transaction distribution -system.membus.trans_dist::ReadResp 662640 # Transaction distribution -system.membus.trans_dist::WriteReq 13889 # Transaction distribution -system.membus.trans_dist::WriteResp 13889 # Transaction distribution -system.membus.trans_dist::Writeback 149983 # Transaction distribution +system.membus.trans_dist::ReadReq 662691 # Transaction distribution +system.membus.trans_dist::ReadResp 662685 # Transaction distribution +system.membus.trans_dist::WriteReq 13891 # Transaction distribution +system.membus.trans_dist::WriteResp 13891 # Transaction distribution +system.membus.trans_dist::Writeback 149916 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2187 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1743 # Transaction distribution -system.membus.trans_dist::ReadExReq 133791 # Transaction distribution -system.membus.trans_dist::ReadExResp 133789 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2202 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1731 # Transaction distribution +system.membus.trans_dist::ReadExReq 133471 # Transaction distribution +system.membus.trans_dist::ReadExResp 133469 # Transaction distribution system.membus.trans_dist::MessageReq 1644 # Transaction distribution system.membus.trans_dist::MessageResp 1644 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478147 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1725388 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1870142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1869528 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18480320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20272507 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18458240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20250435 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26284203 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1595 # Total snoops (count) -system.membus.snoop_fanout::samples 385911 # Request fanout histogram +system.membus.pkt_size::total 26262131 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1626 # Total snoops (count) +system.membus.snoop_fanout::samples 385584 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 385911 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 385584 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 385911 # Request fanout histogram -system.membus.reqLayer0.occupancy 251714500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 385584 # Request fanout histogram +system.membus.reqLayer0.occupancy 251730500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583067000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583066500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1996777999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1995956000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3163999272 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3161502789 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54979247 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54989497 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini index c9ccea56d..2f7786e68 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini @@ -705,7 +705,7 @@ header_cycles=1 use_default_range=false width=8 default=system.pc.pciconfig.pio -master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave +master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port system.ruby.l1_cntrl1.sequencer.pio_master_port system.ruby.l1_cntrl1.sequencer.mem_master_port [system.mem_ctrls] @@ -787,7 +787,7 @@ port=system.ruby.dir_cntrl0.memory [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge eventq_index=0 intrctrl=system.intrctrl system=system @@ -808,7 +808,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[11] +pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 @@ -820,7 +820,7 @@ pio_latency=100000 platform=system.pc system=system terminal=system.pc.com_1.terminal -pio=system.iobus.master[12] +pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal @@ -846,7 +846,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[13] +pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake @@ -864,7 +864,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[14] +pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake @@ -882,7 +882,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[15] +pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake @@ -900,9 +900,9 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[16] +pio=system.iobus.master[17] -[system.pc.i_dont_exist] +[system.pc.i_dont_exist1] type=IsaFake clk_domain=system.clk_domain eventq_index=0 @@ -920,6 +920,24 @@ update_data=false warn_access= pio=system.iobus.master[10] +[system.pc.i_dont_exist2] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=9223372036854776045 +pio_latency=100000 +pio_size=1 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[11] + [system.pc.pciconfig] type=PciConfigAll bus=0 @@ -1397,7 +1415,7 @@ ruby_system=system.ruby system=system using_ruby_tester=false version=1 -slave=system.iobus.master[19] +slave=system.iobus.master[20] [system.ruby.l1_cntrl0] type=L1Cache_Controller @@ -1416,7 +1434,7 @@ number_of_TBEs=256 prefetcher=system.ruby.l1_cntrl0.prefetcher recycle_latency=10 ruby_system=system.ruby -send_evictions=false +send_evictions=true sequencer=system.ruby.l1_cntrl0.sequencer system=system to_l2_latency=1 @@ -1489,7 +1507,7 @@ version=0 master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave mem_master_port=system.iobus.slave[2] pio_master_port=system.iobus.slave[1] -pio_slave_port=system.iobus.master[17] +pio_slave_port=system.iobus.master[18] slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master [system.ruby.l1_cntrl1] @@ -1509,7 +1527,7 @@ number_of_TBEs=256 prefetcher=system.ruby.l1_cntrl1.prefetcher recycle_latency=10 ruby_system=system.ruby -send_evictions=false +send_evictions=true sequencer=system.ruby.l1_cntrl1.sequencer system=system to_l2_latency=1 @@ -1582,7 +1600,7 @@ version=1 master=system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave mem_master_port=system.iobus.slave[4] pio_master_port=system.iobus.slave[3] -pio_slave_port=system.iobus.master[18] +pio_slave_port=system.iobus.master[19] slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.interrupts.int_master [system.ruby.l2_cntrl0] |