diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
6 files changed, 998 insertions, 999 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 1c6d485f3..43a81f743 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -935,7 +935,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.pc.pciconfig.pio master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master @@ -997,7 +997,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master @@ -1477,7 +1477,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index fefd6bd25..c8a74a70a 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 29 2012 00:25:59 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 14:54:43 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5147413032500 because m5_exit instruction encountered +Exiting @ tick 5173840734500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 674b1d778..4862f54d8 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.147413 # Number of seconds simulated -sim_ticks 5147413032500 # Number of ticks simulated -final_tick 5147413032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.173841 # Number of seconds simulated +sim_ticks 5173840734500 # Number of ticks simulated +final_tick 5173840734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192321 # Simulator instruction rate (inst/s) -host_op_rate 378987 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2320932369 # Simulator tick rate (ticks/s) -host_mem_usage 367552 # Number of bytes of host memory used -host_seconds 2217.82 # Real time elapsed on the host -sim_insts 426532736 # Number of instructions simulated -sim_ops 840526050 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2503168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1073280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10624512 # Number of bytes read from this memory -system.physmem.bytes_read::total 14204736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1073280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1073280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9409088 # Number of bytes written to this memory -system.physmem.bytes_written::total 9409088 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 39112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 166008 # Number of read requests responded to by this memory -system.physmem.num_reads::total 221949 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 147017 # Number of write requests responded to by this memory -system.physmem.num_writes::total 147017 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 486296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 208509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2064049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2759587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 208509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 208509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1827926 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1827926 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1827926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 486296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 208509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2064049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4587513 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 110659 # number of replacements -system.l2c.tagsinuse 64846.009272 # Cycle average of tags in use -system.l2c.total_refs 3990913 # Total number of references to valid blocks. -system.l2c.sampled_refs 174907 # Sample count of references to valid blocks. -system.l2c.avg_refs 22.817343 # Average number of references to valid blocks. +host_inst_rate 158571 # Simulator instruction rate (inst/s) +host_op_rate 312487 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1923470418 # Simulator tick rate (ticks/s) +host_mem_usage 368528 # Number of bytes of host memory used +host_seconds 2689.85 # Real time elapsed on the host +sim_insts 426531587 # Number of instructions simulated +sim_ops 840543055 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2458496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1064640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10449152 # Number of bytes read from this memory +system.physmem.bytes_read::total 13975936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1064640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1064640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9180480 # Number of bytes written to this memory +system.physmem.bytes_written::total 9180480 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 50 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16635 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 163268 # Number of read requests responded to by this memory +system.physmem.num_reads::total 218374 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143445 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143445 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 475178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 205774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2019612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2701269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 205774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 205774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1774403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1774403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1774403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 475178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 205774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2019612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4475672 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 107079 # number of replacements +system.l2c.tagsinuse 64844.194000 # Cycle average of tags in use +system.l2c.total_refs 3995584 # Total number of references to valid blocks. +system.l2c.sampled_refs 171337 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.320030 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50048.797239 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 13.777958 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.155980 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3384.461133 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11398.816962 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.763684 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000210 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051643 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.173932 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989472 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 111705 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 9478 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1055456 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1342066 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2518705 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1610504 # number of Writeback hits -system.l2c.Writeback_hits::total 1610504 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 315 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 315 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 161822 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 161822 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 111705 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 9478 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1055456 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1503888 # number of demand (read+write) hits -system.l2c.demand_hits::total 2680527 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 111705 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 9478 # number of overall hits -system.l2c.overall_hits::cpu.inst 1055456 # number of overall hits -system.l2c.overall_hits::cpu.data 1503888 # number of overall hits -system.l2c.overall_hits::total 2680527 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16771 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 36056 # number of ReadReq misses -system.l2c.ReadReq_misses::total 52886 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1746 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1746 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 130897 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130897 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 16771 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 166953 # number of demand (read+write) misses -system.l2c.demand_misses::total 183783 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 53 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses -system.l2c.overall_misses::cpu.inst 16771 # number of overall misses -system.l2c.overall_misses::cpu.data 166953 # number of overall misses -system.l2c.overall_misses::total 183783 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2763500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 312000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 876462500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1897742000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2777280000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 38052500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 38052500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6815913500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6815913500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2763500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 312000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 876462500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8713655500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9593193500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2763500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 312000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 876462500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8713655500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9593193500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 111758 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 9484 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1072227 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1378122 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2571591 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1610504 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1610504 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2061 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2061 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 292719 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292719 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 111758 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 9484 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1072227 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1670841 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2864310 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 111758 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 9484 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1072227 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1670841 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2864310 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000474 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.015641 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.026163 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020565 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.847162 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.847162 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.447176 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.447176 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000474 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000633 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.015641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.099922 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.064163 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000474 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000633 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.015641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.099922 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.064163 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52141.509434 # average ReadReq miss latency +system.l2c.occ_blocks::writebacks 50153.806815 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 12.883885 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.168545 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3383.279361 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11294.055394 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.765286 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000197 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.051625 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.172334 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989444 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 110015 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 8879 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1055721 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1346083 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2520698 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1613450 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025340 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020094 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.821487 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.821487 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.440965 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.440965 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.098089 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063134 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.098089 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063134 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40046.779964 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40397.892109 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40286.126239 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40213.058419 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40213.058419 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40009.102577 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40009.102577 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40891.313496 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41029.716804 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40984.435741 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40269.154557 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40269.154557 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40096.474875 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40096.474875 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40046.779964 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40093.065672 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40088.817669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40046.779964 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40093.065672 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40088.817669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47569 # number of replacements -system.iocache.tagsinuse 0.147452 # Cycle average of tags in use +system.iocache.replacements 47568 # number of replacements +system.iocache.tagsinuse 0.202980 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996357767000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.147452 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.009216 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.009216 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.warmup_cycle 5000598826000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.202980 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.012686 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.012686 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses +system.iocache.ReadReq_misses::total 903 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses -system.iocache.demand_misses::total 47624 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses -system.iocache.overall_misses::total 47624 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 113343932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 113343932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6309295160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6309295160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6422639092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6422639092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6422639092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6422639092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses +system.iocache.demand_misses::total 47623 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses +system.iocache.overall_misses::total 47623 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135810932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 135810932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6905757160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6905757160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7041568092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7041568092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 7041568092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7041568092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +330,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125380.455752 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125380.455752 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 135044.845034 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 135044.845034 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134861.395347 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 134861.395347 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134861.395347 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 134861.395347 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 66555216 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150399.703212 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 150399.703212 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147811.583048 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 147811.583048 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 147860.657497 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 147860.657497 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11227 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5928.138951 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 903 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 903 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47624 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47624 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47624 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47624 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66312982 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 66312982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3879551568 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3879551568 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3945864550 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3945864550 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3945864550 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3945864550 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47623 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47623 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47623 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47623 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88823000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88823000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4476002926 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4476002926 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4564825926 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4564825926 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4564825926 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4564825926 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73355.068584 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73355.068584 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 83038.346918 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 83038.346918 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82854.538678 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82854.538678 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98364.341085 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 98364.341085 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95804.857149 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 95804.857149 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,413 +393,413 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 459902894 # number of cpu cycles simulated +system.cpu.numCycles 473010428 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90033870 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90033870 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1172024 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84304215 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81702749 # Number of BTB hits +system.cpu.BPredUnit.lookups 90027775 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90027775 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1176793 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84224638 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81706962 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29359737 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 447000113 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90033870 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81702749 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 169792580 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5290860 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 149776 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 97806900 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37530 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 36600 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 214 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9375679 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 523969 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5232 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 301265833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.919513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.390338 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31360026 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 446936699 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90027775 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81706962 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169789390 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5321789 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 167863 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 104601282 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 44086 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9371006 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 537925 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5262 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 310106612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.836098 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376721 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131910949 43.79% 43.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1767278 0.59% 44.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72780383 24.16% 68.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 988082 0.33% 68.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1637864 0.54% 69.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3667894 1.22% 70.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1147346 0.38% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1446143 0.48% 71.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85919894 28.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140752877 45.39% 45.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1771842 0.57% 45.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72784841 23.47% 69.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 985545 0.32% 69.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1639332 0.53% 70.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3672529 1.18% 71.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1138013 0.37% 71.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1446532 0.47% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85915101 27.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 301265833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.195767 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.971945 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34474494 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93907388 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 163990791 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4810664 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4082496 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 876264710 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4082496 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38727929 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39278399 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10114969 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 164053704 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45008336 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 872424503 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9763 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 34576608 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3790570 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31863881 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1394114241 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2488384373 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2488383477 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1347565425 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46548809 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 469868 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476809 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46309775 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 18907776 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10445518 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1298255 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1025454 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 865635268 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1719822 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 864337626 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112774 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25913081 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 53108345 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 204185 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 301265833 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.869020 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.387854 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 310106612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.190329 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.944877 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36504487 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100689087 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164100014 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4706777 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4106247 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876222772 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 974 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4106247 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 40918052 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 44290154 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10988643 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 163783570 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46019946 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872439032 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9880 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 35250675 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3950071 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31995010 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1394183444 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2488413838 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2488413278 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1347594272 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 46589165 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 477213 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48119615 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18916713 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10445823 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1292985 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1005726 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865744936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1721292 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864337925 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 123293 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26001434 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 53514506 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 205573 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 310106612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.787228 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.396179 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 94932773 31.51% 31.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22142074 7.35% 38.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 18888671 6.27% 45.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7860945 2.61% 47.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 80656411 26.77% 74.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3302785 1.10% 75.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72810465 24.17% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 540656 0.18% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 131053 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 102391332 33.02% 33.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23760486 7.66% 40.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 19024925 6.13% 46.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7818761 2.52% 49.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 80618326 26.00% 75.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3106091 1.00% 76.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72752494 23.46% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 520993 0.17% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 113204 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 301265833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 310106612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 170381 8.07% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1776523 84.09% 92.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 165648 7.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 162823 7.80% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1765220 84.55% 92.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159742 7.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 297256 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 829421724 95.96% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25169917 2.91% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9448729 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 296671 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829442170 95.96% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25162510 2.91% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9436574 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 864337626 # Type of FU issued -system.cpu.iq.rate 1.879392 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2112552 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002444 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2032304206 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 893278706 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 853918308 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 381 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 418 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 98 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 866152744 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 178 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1572054 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 864337925 # Type of FU issued +system.cpu.iq.rate 1.827313 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2087785 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002415 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2041131934 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893478671 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 853934886 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866128931 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1577690 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3603717 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21501 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11898 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2033136 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3621025 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20103 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12189 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2042088 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821637 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2389 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821421 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4286 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4082496 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25489851 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1396862 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 867355090 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 297196 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 18907776 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10445518 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 881207 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 698514 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12367 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11898 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 698869 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 624345 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1323214 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 862415633 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24733940 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1921992 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4106247 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27916479 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1927801 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867466228 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 303428 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18916713 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10445834 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 882766 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 975199 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12189 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 699297 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 625213 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1324510 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862446659 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24735217 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1891265 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 33937040 # number of memory reference insts executed -system.cpu.iew.exec_branches 86496224 # Number of branches executed -system.cpu.iew.exec_stores 9203100 # Number of stores executed -system.cpu.iew.exec_rate 1.875212 # Inst execution rate -system.cpu.iew.wb_sent 861954133 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 853918406 # cumulative count of insts written-back -system.cpu.iew.wb_producers 669978264 # num instructions producing a value -system.cpu.iew.wb_consumers 1919317191 # num instructions consuming a value +system.cpu.iew.exec_refs 33929559 # number of memory reference insts executed +system.cpu.iew.exec_branches 86496146 # Number of branches executed +system.cpu.iew.exec_stores 9194342 # Number of stores executed +system.cpu.iew.exec_rate 1.823314 # Inst execution rate +system.cpu.iew.wb_sent 861961974 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 853934949 # cumulative count of insts written-back +system.cpu.iew.wb_producers 669649521 # num instructions producing a value +system.cpu.iew.wb_consumers 1918783501 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.856736 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.349071 # average fanout of values written-back +system.cpu.iew.wb_rate 1.805319 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.348997 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426532736 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840526050 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26723975 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1515635 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1176103 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 297198870 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.828160 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.864352 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426531587 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840543055 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26818803 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1515717 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1181719 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 306015924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.746730 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.861261 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 116541377 39.21% 39.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14339767 4.82% 44.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4295097 1.45% 45.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76671720 25.80% 71.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3910835 1.32% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1786901 0.60% 73.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1117084 0.38% 73.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71988132 24.22% 97.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6547957 2.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 125070317 40.87% 40.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14726015 4.81% 45.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4257326 1.39% 47.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76646045 25.05% 72.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3895754 1.27% 73.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1793252 0.59% 73.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1102852 0.36% 74.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71997039 23.53% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6527324 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 297198870 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426532736 # Number of instructions committed -system.cpu.commit.committedOps 840526050 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 306015924 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426531587 # Number of instructions committed +system.cpu.commit.committedOps 840543055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23716438 # Number of memory references committed -system.cpu.commit.loads 15304056 # Number of loads committed -system.cpu.commit.membars 781569 # Number of memory barriers committed -system.cpu.commit.branches 85505804 # Number of branches committed +system.cpu.commit.refs 23699431 # Number of memory references committed +system.cpu.commit.loads 15295685 # Number of loads committed +system.cpu.commit.membars 781577 # Number of memory barriers committed +system.cpu.commit.branches 85508404 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768351683 # Number of committed integer instructions. +system.cpu.commit.int_insts 768361520 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6547957 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6527324 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1157821631 # The number of ROB reads -system.cpu.rob.rob_writes 1738597524 # The number of ROB writes -system.cpu.timesIdled 2901104 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 158637061 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9834920608 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426532736 # Number of Instructions Simulated -system.cpu.committedOps 840526050 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426532736 # Number of Instructions Simulated -system.cpu.cpi 1.078236 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.078236 # CPI: Total CPI of All Threads -system.cpu.ipc 0.927441 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.927441 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2163268420 # number of integer regfile reads -system.cpu.int_regfile_writes 1362711366 # number of integer regfile writes -system.cpu.fp_regfile_reads 98 # number of floating regfile reads -system.cpu.misc_regfile_reads 281060274 # number of misc regfile reads -system.cpu.misc_regfile_writes 403581 # number of misc regfile writes -system.cpu.icache.replacements 1071746 # number of replacements -system.cpu.icache.tagsinuse 509.688073 # Cycle average of tags in use -system.cpu.icache.total_refs 8235470 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1072258 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.680493 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56594855000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.688073 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995485 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995485 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8235470 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8235470 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8235470 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8235470 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8235470 # number of overall hits -system.cpu.icache.overall_hits::total 8235470 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1140205 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1140205 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1140205 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1140205 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1140205 # number of overall misses -system.cpu.icache.overall_misses::total 1140205 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16916733991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16916733991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16916733991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16916733991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16916733991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16916733991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9375675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9375675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9375675 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9375675 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9375675 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9375675 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121613 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121613 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121613 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121613 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121613 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121613 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14836.572363 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14836.572363 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14836.572363 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14836.572363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14836.572363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14836.572363 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2216492 # number of cycles access was blocked +system.cpu.rob.rob_reads 1166770942 # The number of ROB reads +system.cpu.rob.rob_writes 1738844954 # The number of ROB writes +system.cpu.timesIdled 2997386 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 162903816 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9874668492 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426531587 # Number of Instructions Simulated +system.cpu.committedOps 840543055 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426531587 # Number of Instructions Simulated +system.cpu.cpi 1.108969 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108969 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901738 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.901738 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2163215430 # number of integer regfile reads +system.cpu.int_regfile_writes 1362691420 # number of integer regfile writes +system.cpu.fp_regfile_reads 63 # number of floating regfile reads +system.cpu.misc_regfile_reads 281069935 # number of misc regfile reads +system.cpu.misc_regfile_writes 403791 # number of misc regfile writes +system.cpu.icache.replacements 1071897 # number of replacements +system.cpu.icache.tagsinuse 510.429584 # Cycle average of tags in use +system.cpu.icache.total_refs 8228054 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1072409 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.672496 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56932855000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.429584 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996933 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996933 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8228054 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8228054 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8228054 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8228054 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8228054 # number of overall hits +system.cpu.icache.overall_hits::total 8228054 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1142948 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9371002 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9371002 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9371002 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9371002 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9371002 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121966 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121966 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121966 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.121966 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.121966 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.121966 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16505.732096 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16505.732096 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16505.732096 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16505.732096 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3301994 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 399 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9197.062241 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8275.674185 # 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number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1072591 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1072591 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1072591 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1072591 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12848213492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12848213492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12848213492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12848213492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12848213492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12848213492 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11978.669868 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11978.669868 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1600 # number of writebacks +system.cpu.icache.writebacks::total 1600 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70415 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70415 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70415 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70415 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70415 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70415 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072533 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1072533 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1072533 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1072533 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1072533 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1072533 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14734319994 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14734319994 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14734319994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14734319994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14734319994 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14734319994 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114452 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114452 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114452 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13737.870997 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13737.870997 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 12981 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.013322 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25373 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 12993 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 1.952821 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5123561713000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.013322 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375833 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375833 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25418 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25418 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 11177 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.030365 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 31227 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 11191 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.790367 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5136145388000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.030365 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376898 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376898 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31228 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 31228 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25421 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25421 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25421 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25421 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 13864 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 13864 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 13864 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 13864 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 13864 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 13864 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 165480500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 165480500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 165480500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 165480500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 165480500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 165480500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39282 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 39282 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31231 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 31231 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31231 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 31231 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12057 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 12057 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12057 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 12057 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12057 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 12057 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 192652500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 192652500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 192652500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 192652500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 192652500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 192652500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43285 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 43285 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # 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number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.278549 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.278549 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.278530 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.278530 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.278530 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.278530 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 15978.477233 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 15978.477233 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 15978.477233 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 15978.477233 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,78 +808,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1460 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1460 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 13864 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 13864 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 13864 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 13864 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 13864 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 13864 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 123445500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 123445500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 123445500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 123445500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 123445500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 123445500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352935 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352935 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352908 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352908 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352908 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352908 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8904.032025 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8904.032025 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8904.032025 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8904.032025 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1620 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1620 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12057 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12057 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12057 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 12057 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12057 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 12057 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155859527 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155859527 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155859527 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155859527 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155859527 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155859527 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.278549 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.278549 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.278530 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.278530 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12926.891184 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 120380 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.933344 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 133363 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 120396 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.107703 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5104613509000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.933344 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808334 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.808334 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 133363 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 133363 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 133363 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 133363 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 133363 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 133363 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 121457 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 121457 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 121457 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 121457 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 121457 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 121457 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1679660000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1679660000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1679660000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1679660000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1679660000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1679660000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 254820 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 254820 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 254820 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 254820 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 254820 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 254820 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.476638 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.476638 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.476638 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.476638 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.476638 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.476638 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13829.256445 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13829.256445 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13829.256445 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13829.256445 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13829.256445 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13829.256445 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 116226 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.942586 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 138119 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 116242 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.188202 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5112881220000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.942586 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808912 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.808912 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138119 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 138119 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138119 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 138119 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138119 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 138119 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117277 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 117277 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117277 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 117277 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117277 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 117277 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2115105000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2115105000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2115105000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2115105000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2115105000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2115105000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255396 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 255396 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255396 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 255396 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255396 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 255396 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.459197 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.459197 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.459197 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.459197 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.459197 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.459197 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18035.121976 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18035.121976 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18035.121976 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18035.121976 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,146 +888,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 37082 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 37082 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 121457 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 121457 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 121457 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 121457 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 121457 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 121457 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1312360500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1312360500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1312360500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1312360500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.476638 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.476638 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.476638 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.476638 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10805.145031 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10805.145031 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10805.145031 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 36600 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 36600 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117277 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117277 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117277 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 117277 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117277 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 117277 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1760668506 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1760668506 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1760668506 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.459197 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.459197 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.459197 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15012.905395 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1670972 # number of replacements -system.cpu.dcache.tagsinuse 511.998179 # Cycle average of tags in use -system.cpu.dcache.total_refs 19056575 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1671484 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.400992 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998179 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10967822 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10967822 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8085914 # 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number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86593459000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103393 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103393 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035120 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035120 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077059 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077059 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16864.059085 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16864.059085 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31758.576700 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31758.576700 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini index c9fc9d3a5..d219b0faf 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini @@ -1190,7 +1190,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.pc.pciconfig.pio master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index d6cb455f2..9c27e2eb7 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:12 -gem5 started Jun 4 2012 17:11:29 +gem5 compiled Jul 2 2012 09:03:01 +gem5 started Jul 2 2012 15:09:17 gem5 executing on zizzer -command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory +command line: build/X86_MESI_CMP_directory/gem5.fast -d build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5304689685500 because m5_exit instruction encountered +Exiting @ tick 5305568291500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index b7d143468..b9331fa8f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.304690 # Number of seconds simulated -sim_ticks 5304689685500 # Number of ticks simulated -final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.305568 # Number of seconds simulated +sim_ticks 5305568291500 # Number of ticks simulated +final_tick 5305568291500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163049 # Simulator instruction rate (inst/s) -host_op_rate 333085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6301127704 # Simulator tick rate (ticks/s) -host_mem_usage 481488 # Number of bytes of host memory used -host_seconds 841.86 # Real time elapsed on the host -sim_insts 137264752 # Number of instructions simulated -sim_ops 280412254 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory -system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory +host_inst_rate 254586 # Simulator instruction rate (inst/s) +host_op_rate 522269 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9722568027 # Simulator tick rate (ticks/s) +host_mem_usage 466304 # Number of bytes of host memory used +host_seconds 545.70 # Real time elapsed on the host +sim_insts 138926459 # Number of instructions simulated +sim_ops 285000258 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 131880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 65368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 843624624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 40107648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 91872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 42696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 468878472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 53485285 # Number of bytes read from this memory +system.physmem.bytes_read::total 1406463005 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 843624624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 468878472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1312503096 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory -system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 32434308 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 35512736 # Number of bytes written to this memory +system.physmem.bytes_written::total 70938164 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 16485 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 105453078 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6721984 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58609809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8980290 # Number of read requests responded to by this memory +system.physmem.num_reads::total 179807449 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 4872641 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4951979 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9871358 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 24857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 12321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 159007401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7559539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 17316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8047 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 88374788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10080972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 265091867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 159007401 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 88374788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247382189 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563767 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6113258 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6693484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13370512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 24857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 12324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 159007401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13672797 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 17316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8047 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 88374788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16774456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 278462379 # Total bandwidth to/from this memory (bytes/s) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -84,52 +84,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10608177450 # number of cpu cycles simulated +system.cpu0.numCycles 10611136583 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 88690468 # Number of instructions committed -system.cpu0.committedOps 187060545 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 168469813 # Number of integer alu accesses +system.cpu0.committedInsts 90467543 # Number of instructions committed +system.cpu0.committedOps 191745753 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 172320951 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls -system.cpu0.num_int_insts 168469813 # number of integer instructions +system.cpu0.num_conditional_control_insts 18433460 # number of instructions that are conditional controls +system.cpu0.num_int_insts 172320951 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read -system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written +system.cpu0.num_int_register_reads 529440727 # number of times the integer registers were read +system.cpu0.num_int_register_writes 286411795 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 19132508 # number of memory refs -system.cpu0.num_load_insts 14284566 # Number of load instructions -system.cpu0.num_store_insts 4847942 # Number of store instructions -system.cpu0.num_idle_cycles 10086452980.871330 # Number of idle cycles -system.cpu0.num_busy_cycles 521724469.128670 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049181 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950819 # Percentage of idle cycles +system.cpu0.num_mem_refs 19683524 # number of memory refs +system.cpu0.num_load_insts 14800104 # Number of load instructions +system.cpu0.num_store_insts 4883420 # Number of store instructions +system.cpu0.num_idle_cycles 10087380547.886099 # Number of idle cycles +system.cpu0.num_busy_cycles 523756035.113901 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049359 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950641 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10609379371 # number of cpu cycles simulated +system.cpu1.numCycles 10608184508 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48574284 # Number of instructions committed -system.cpu1.committedOps 93351709 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 89110416 # Number of integer alu accesses +system.cpu1.committedInsts 48458916 # Number of instructions committed +system.cpu1.committedOps 93254505 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88898001 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls -system.cpu1.num_int_insts 89110416 # number of integer instructions +system.cpu1.num_conditional_control_insts 8156206 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88898001 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read -system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written +system.cpu1.num_int_register_reads 272266493 # number of times the integer registers were read +system.cpu1.num_int_register_writes 138281277 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 14426742 # number of memory refs -system.cpu1.num_load_insts 9181010 # Number of load instructions -system.cpu1.num_store_insts 5245732 # Number of store instructions -system.cpu1.num_idle_cycles 10273661233.326063 # Number of idle cycles -system.cpu1.num_busy_cycles 335718137.673937 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031644 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968356 # Percentage of idle cycles +system.cpu1.num_mem_refs 14383510 # number of memory refs +system.cpu1.num_load_insts 9129721 # Number of load instructions +system.cpu1.num_store_insts 5253789 # Number of store instructions +system.cpu1.num_idle_cycles 10274260882.632458 # Number of idle cycles +system.cpu1.num_busy_cycles 333923625.367543 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031478 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968522 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |