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-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt2533
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt330
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt3257
3 files changed, 3076 insertions, 3044 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 0e907e72d..7ec12ef0d 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,133 +1,133 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.144275 # Number of seconds simulated
-sim_ticks 5144274809000 # Number of ticks simulated
-final_tick 5144274809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.144266 # Number of seconds simulated
+sim_ticks 5144266112000 # Number of ticks simulated
+final_tick 5144266112000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 169693 # Simulator instruction rate (inst/s)
-host_op_rate 335427 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2145113000 # Simulator tick rate (ticks/s)
-host_mem_usage 770200 # Number of bytes of host memory used
-host_seconds 2398.14 # Real time elapsed on the host
-sim_insts 406947274 # Number of instructions simulated
-sim_ops 804399711 # Number of ops (including micro ops) simulated
+host_inst_rate 171088 # Simulator instruction rate (inst/s)
+host_op_rate 338186 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2162643270 # Simulator tick rate (ticks/s)
+host_mem_usage 817576 # Number of bytes of host memory used
+host_seconds 2378.69 # Real time elapsed on the host
+sim_insts 406967147 # Number of instructions simulated
+sim_ops 804441344 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1034048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10709312 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1037760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10694784 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11775872 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1034048 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1034048 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9547776 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9547776 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16157 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 167333 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 11765248 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1037760 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1037760 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9531136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9531136 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 16215 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 167106 # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 183998 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149184 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149184 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 746 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 201009 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2081792 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total 183832 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 148924 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 148924 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 201731 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2078972 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2289122 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 201009 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 201009 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1856000 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1856000 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1856000 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 746 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 201009 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2081792 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 2287061 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 201731 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 201731 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1852769 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1852769 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1852769 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 201731 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2078972 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4145122 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 183998 # Number of read requests accepted
-system.physmem.writeReqs 149184 # Number of write requests accepted
-system.physmem.readBursts 183998 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 149184 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11761088 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 14784 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9546240 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11775872 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 9547776 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 231 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 4139829 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 183832 # Number of read requests accepted
+system.physmem.writeReqs 148924 # Number of write requests accepted
+system.physmem.readBursts 183832 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 148924 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11753920 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 11328 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9529408 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11765248 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9531136 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 177 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 58239 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11315 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10581 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12129 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11752 # Per bank write bursts
-system.physmem.perBankRdBursts::4 11319 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10663 # Per bank write bursts
-system.physmem.perBankRdBursts::6 10930 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11239 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10920 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11403 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11471 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11421 # Per bank write bursts
-system.physmem.perBankRdBursts::12 12415 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12512 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11823 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11874 # Per bank write bursts
-system.physmem.perBankWrBursts::0 9756 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9158 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9767 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9469 # Per bank write bursts
-system.physmem.perBankWrBursts::4 9300 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9148 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8815 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8963 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8876 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9249 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9141 # Per bank write bursts
-system.physmem.perBankWrBursts::11 9048 # Per bank write bursts
-system.physmem.perBankWrBursts::12 9841 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9699 # Per bank write bursts
-system.physmem.perBankWrBursts::14 9635 # Per bank write bursts
-system.physmem.perBankWrBursts::15 9295 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 11604 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10712 # Per bank write bursts
+system.physmem.perBankRdBursts::2 11807 # Per bank write bursts
+system.physmem.perBankRdBursts::3 11944 # Per bank write bursts
+system.physmem.perBankRdBursts::4 11505 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10649 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11472 # Per bank write bursts
+system.physmem.perBankRdBursts::7 11273 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10779 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10837 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10616 # Per bank write bursts
+system.physmem.perBankRdBursts::11 10970 # Per bank write bursts
+system.physmem.perBankRdBursts::12 12334 # Per bank write bursts
+system.physmem.perBankRdBursts::13 12596 # Per bank write bursts
+system.physmem.perBankRdBursts::14 12433 # Per bank write bursts
+system.physmem.perBankRdBursts::15 12124 # Per bank write bursts
+system.physmem.perBankWrBursts::0 10095 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9143 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9309 # Per bank write bursts
+system.physmem.perBankWrBursts::3 9560 # Per bank write bursts
+system.physmem.perBankWrBursts::4 9320 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8650 # Per bank write bursts
+system.physmem.perBankWrBursts::6 9309 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8633 # Per bank write bursts
+system.physmem.perBankWrBursts::8 9264 # Per bank write bursts
+system.physmem.perBankWrBursts::9 9181 # Per bank write bursts
+system.physmem.perBankWrBursts::10 8947 # Per bank write bursts
+system.physmem.perBankWrBursts::11 9087 # Per bank write bursts
+system.physmem.perBankWrBursts::12 9676 # Per bank write bursts
+system.physmem.perBankWrBursts::13 9763 # Per bank write bursts
+system.physmem.perBankWrBursts::14 9717 # Per bank write bursts
+system.physmem.perBankWrBursts::15 9243 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 5144274759500 # Total gap between requests
+system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
+system.physmem.totGap 5144265940500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 183998 # Read request sizes (log2)
+system.physmem.readPktSize::6 183832 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 149184 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 169620 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 11412 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 148924 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 169282 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 11661 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1942 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 450 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 36 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 38 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 435 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
@@ -156,300 +156,300 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2916 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 7399 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 7449 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 8122 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 8310 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 9443 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 8747 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 9907 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 10037 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 9884 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 11487 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 9002 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8428 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8054 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7610 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 7540 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 380 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 268 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 294 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 146 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 158 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 126 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 170 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 93 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 70 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 50 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 41 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 72943 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 292.108413 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.353373 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 313.792232 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 28114 38.54% 38.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17711 24.28% 62.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7670 10.52% 73.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4213 5.78% 79.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2951 4.05% 83.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2449 3.36% 86.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1349 1.85% 88.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1138 1.56% 89.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7348 10.07% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 72943 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 7277 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.251615 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 563.083563 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 7276 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 2119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3421 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 8552 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 7509 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 8532 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7671 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7567 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 8001 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 8525 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 8626 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 8882 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 9922 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 8766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 9409 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 10681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8761 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 8326 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 8337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1369 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 261 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 143 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 193 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 203 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 151 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 125 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 107 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 71 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 104 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 57 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 49 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 72695 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 292.774799 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 175.092405 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 313.788617 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 27722 38.13% 38.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17851 24.56% 62.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7685 10.57% 73.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4254 5.85% 79.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2907 4.00% 83.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2448 3.37% 86.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1364 1.88% 88.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1142 1.57% 89.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7322 10.07% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 72695 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 7110 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 25.828551 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 569.649701 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 7109 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 7277 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 7277 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.497458 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.666266 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.148532 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 6223 85.52% 85.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 179 2.46% 87.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 37 0.51% 88.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 181 2.49% 90.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 17 0.23% 91.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 151 2.08% 93.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 102 1.40% 94.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 5 0.07% 94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 29 0.40% 95.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 31 0.43% 95.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 5 0.07% 95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 9 0.12% 95.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 222 3.05% 98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 6 0.08% 98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 6 0.08% 98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 40 0.55% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 1 0.01% 99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.01% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 5 0.07% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.01% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.01% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 17 0.23% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 7277 # Writes before turning the bus around for reads
-system.physmem.totQLat 2097648589 # Total ticks spent queuing
-system.physmem.totMemAccLat 5543279839 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 918835000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11414.72 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 7110 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 7110 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.941913 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.730767 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 15.006357 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 6192 87.09% 87.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 167 2.35% 89.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 37 0.52% 89.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 45 0.63% 90.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 23 0.32% 90.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 21 0.30% 91.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 97 1.36% 92.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 9 0.13% 92.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 166 2.33% 95.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 18 0.25% 95.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 7 0.10% 95.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 16 0.23% 95.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 121 1.70% 97.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 8 0.11% 97.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.06% 97.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 38 0.53% 98.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 106 1.49% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.01% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 17 0.24% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 3 0.04% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 5 0.07% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 2 0.03% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191 2 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 7110 # Writes before turning the bus around for reads
+system.physmem.totQLat 2119857534 # Total ticks spent queuing
+system.physmem.totMemAccLat 5563388784 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 918275000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11542.61 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30164.72 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30292.61 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.26 # Average write queue length when enqueuing
-system.physmem.readRowHits 150147 # Number of row buffer hits during reads
-system.physmem.writeRowHits 109836 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.71 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.62 # Row buffer hit rate for writes
-system.physmem.avgGap 15439833.96 # Average gap between requests
-system.physmem.pageHitRate 78.08 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 269030160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 146792250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 701430600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 481956480 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 132992885070 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2969904214500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 3440495289780 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.800889 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 4940616567724 # Time in different power states
-system.physmem_0.memoryStateTime::REF 171778620000 # Time in different power states
+system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing
+system.physmem.readRowHits 149881 # Number of row buffer hits during reads
+system.physmem.writeRowHits 109975 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes
+system.physmem.avgGap 15459573.80 # Average gap between requests
+system.physmem.pageHitRate 78.13 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 270058320 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 147353250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 709527000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 479643120 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 132965716590 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2969918703000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3440488964880 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.801684 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 4940650410974 # Time in different power states
+system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 31879461276 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 31837441026 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 282418920 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 154097625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 731944200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 484600320 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 133085381535 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2969823077250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 3440560500570 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.813565 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 4940481114488 # Time in different power states
-system.physmem_1.memoryStateTime::REF 171778620000 # Time in different power states
+system.physmem_1.actEnergy 279515880 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 152513625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 722974200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 485209440 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 132979028940 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2969907025500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 3440524231185 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.808539 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 4940617535740 # Time in different power states
+system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 32014679262 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 31863205510 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 86341843 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86341843 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 843606 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 79482226 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 77803537 # Number of BTB hits
+system.cpu.branchPred.lookups 86364991 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86364991 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 844127 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 79785258 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 77812669 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.887969 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1532975 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 177711 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.527627 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1536742 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 177773 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 465489033 # number of cpu cycles simulated
+system.cpu.numCycles 465360105 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27349012 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 426558725 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86341843 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79336512 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 433328456 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1773234 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 140367 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 61411 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 195746 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 62 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 949 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8924695 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 425342 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4681 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 461962620 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.822369 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.015343 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27264808 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 426684669 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86364991 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79349411 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 433306610 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1772802 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 134530 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 64125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 192382 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 876 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8941256 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 423617 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 4382 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 461849793 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.823288 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.015889 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 297385469 64.37% 64.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2141918 0.46% 64.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 72009169 15.59% 80.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1542851 0.33% 80.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2093373 0.45% 81.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2277762 0.49% 81.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1468275 0.32% 82.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1844826 0.40% 82.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81198977 17.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 297255411 64.36% 64.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2121995 0.46% 64.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72014573 15.59% 80.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1541910 0.33% 80.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2093291 0.45% 81.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2283864 0.49% 81.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1472775 0.32% 82.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1848688 0.40% 82.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 81217286 17.59% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 461962620 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.185486 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.916367 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 23051751 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 281963390 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 147749616 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 8311246 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 886617 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 834090099 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 886617 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 26334343 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 229948938 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 14545958 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 152100341 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 38146423 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 830806639 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 454355 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 12555277 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 214921 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 22219847 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 992487524 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1803840100 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1108929979 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 295 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 961885153 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 30602369 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 460175 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 463946 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 42648824 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17020536 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10013615 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1265948 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1065839 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 825617137 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1152647 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 820744592 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 214843 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 22370068 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33775079 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 142908 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 461962620 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.776647 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.400230 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 461849793 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.185587 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.916891 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 22977374 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 281921600 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 147739670 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 8324748 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 886401 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 834278152 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 886401 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 26267496 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 229970737 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 14504506 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 152095213 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 38125440 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 830978624 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 455578 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 12565136 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 219239 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 22179017 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 992691182 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1804301856 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1109183623 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 961933159 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 30758021 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 459775 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 462810 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 42714636 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17039027 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10018616 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1305141 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1111349 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 825753425 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1154163 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 820868911 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 214819 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 22466239 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33875924 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 142660 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 461849793 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.777350 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.400586 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 278779319 60.35% 60.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13677385 2.96% 63.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 9694463 2.10% 65.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7479161 1.62% 67.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 73155086 15.84% 82.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4780135 1.03% 83.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72637826 15.72% 99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1181137 0.26% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 578108 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 278664222 60.34% 60.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13660041 2.96% 63.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 9686600 2.10% 65.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7488458 1.62% 67.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 73146885 15.84% 82.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4790867 1.04% 83.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72643551 15.73% 99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1186237 0.26% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 582932 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 461962620 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 461849793 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2412123 76.39% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 586072 18.56% 94.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 159607 5.05% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2421761 76.44% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 586525 18.51% 94.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 160044 5.05% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 284241 0.03% 0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 792878234 96.60% 96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 149840 0.02% 96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 126459 0.02% 96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 284830 0.03% 0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 792980272 96.60% 96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 149980 0.02% 96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 126454 0.02% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 91 0.00% 96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 89 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.67% # Type of FU issued
@@ -473,96 +473,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18033989 2.20% 98.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9271738 1.13% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 18050334 2.20% 98.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9276952 1.13% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 820744592 # Type of FU issued
-system.cpu.iq.rate 1.763188 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3157802 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.003847 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2106824012 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 849151947 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 816471101 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 436 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 823617942 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 211 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1861954 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 820868911 # Type of FU issued
+system.cpu.iq.rate 1.763943 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3168330 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.003860 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2106970311 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 849385719 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 816582122 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 452 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 530 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 823752187 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 224 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1863434 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3065804 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 14153 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14111 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1593948 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3081685 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14588 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 13991 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1596193 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2095806 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 68873 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2095838 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 68033 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 886617 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 206103955 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 15659492 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 826769784 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 162986 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17020536 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10013615 # Number of dispatched store instructions
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-system.cpu.iew.iewIQFullEvents 383471 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 14451239 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14111 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 476576 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 506351 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 982927 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 819239221 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17663851 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1381012 # Number of squashed instructions skipped in execute
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+system.cpu.iew.iewBlockCycles 206156511 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 15627383 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 826907588 # Number of instructions dispatched to IQ
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26724913 # number of memory reference insts executed
-system.cpu.iew.exec_branches 82983667 # Number of branches executed
-system.cpu.iew.exec_stores 9061062 # Number of stores executed
-system.cpu.iew.exec_rate 1.759954 # Inst execution rate
-system.cpu.iew.wb_sent 818769187 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 816471257 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 638649867 # num instructions producing a value
-system.cpu.iew.wb_consumers 1046653125 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.754008 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.610183 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 22245724 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1009739 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 854697 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::mean 1.754004 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.647518 # Number of insts commited each cycle
+system.cpu.iew.exec_refs 26746540 # number of memory reference insts executed
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+system.cpu.iew.exec_rate 1.760691 # Inst execution rate
+system.cpu.iew.wb_sent 818880550 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 816582286 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 638742122 # num instructions producing a value
+system.cpu.iew.wb_consumers 1046798890 # num instructions consuming a value
+system.cpu.iew.wb_rate 1.754732 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.610186 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 22341740 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1011503 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 854574 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 1.754577 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 288145143 62.83% 62.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11087272 2.42% 65.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3640468 0.79% 66.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74478879 16.24% 82.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2430107 0.53% 82.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1625402 0.35% 83.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1001040 0.22% 83.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70854372 15.45% 98.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5345073 1.17% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 288021226 62.82% 62.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11081670 2.42% 65.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3642063 0.79% 66.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74473498 16.24% 82.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2428435 0.53% 82.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1625237 0.35% 83.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1003852 0.22% 83.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70853239 15.45% 98.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5352418 1.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 458607756 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 406947274 # Number of instructions committed
-system.cpu.commit.committedOps 804399711 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 458481638 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 406967147 # Number of instructions committed
+system.cpu.commit.committedOps 804441344 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22374398 # Number of memory references committed
-system.cpu.commit.loads 13954731 # Number of loads committed
-system.cpu.commit.membars 448033 # Number of memory barriers committed
-system.cpu.commit.branches 81999646 # Number of branches committed
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+system.cpu.commit.membars 448127 # Number of memory barriers committed
+system.cpu.commit.branches 82004213 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 733379682 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1155571 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 171831 0.02% 0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 781589650 97.16% 97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 144528 0.02% 97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 121874 0.02% 97.22% # Class of committed instruction
+system.cpu.commit.int_insts 733419549 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1155856 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 171897 0.02% 0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 781625831 97.16% 97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 144579 0.02% 97.20% # Class of committed instruction
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system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction
@@ -589,231 +589,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% #
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
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-system.cpu.commit.op_class_0::MemWrite 8419667 1.05% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 804399711 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5345073 # number cycles where commit BW limit reached
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-system.cpu.rob.rob_writes 1656663443 # The number of ROB writes
-system.cpu.timesIdled 287506 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 3526413 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9823058000 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 406947274 # Number of Instructions Simulated
-system.cpu.committedOps 804399711 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.143856 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.143856 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.874236 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.874236 # IPC: Total IPC of All Threads
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-system.cpu.int_regfile_writes 653481018 # number of integer regfile writes
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-system.cpu.misc_regfile_writes 400173 # number of misc regfile writes
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-system.cpu.dcache.tags.avg_refs 11.437466 # Average number of references to valid blocks.
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+system.cpu.cpi_total 1.143483 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 0.874521 # IPC: Total IPC of All Threads
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system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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+system.cpu.dcache.demand_accesses::total 21035025 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 21504425 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142671 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.142671 # miss rate for ReadReq accesses
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+system.cpu.dcache.WriteReq_miss_rate::total 0.039796 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865631 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.865631 # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.101527 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.101527 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.118206 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.118206 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16700.626265 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16700.626265 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62910.075243 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62910.075243 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23944.693009 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23944.693009 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20117.179296 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20117.179296 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 547266 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 52454 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 52094 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.607923 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.505356 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1558074 # number of writebacks
-system.cpu.dcache.writebacks::total 1558074 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 834885 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 834885 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44903 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 44903 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 879788 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 879788 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 879788 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 879788 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 965811 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 965811 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290088 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 290088 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402915 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 402915 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1255899 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1255899 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1658814 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1658814 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13899 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total 13899 # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587359 # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total 587359 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14288232000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 14288232000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19138141242 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 19138141242 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6806565500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6806565500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33426373242 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 33426373242 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40232938742 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 40232938742 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98114325000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98114325000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2778681500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2778681500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100893006500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100893006500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076612 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076612 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034493 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034493 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858618 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858618 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059758 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.059758 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077205 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.077205 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14794.024918 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14794.024918 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65973.570923 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65973.570923 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16893.303799 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16893.303799 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26615.494751 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26615.494751 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24254.038573 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24254.038573 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.837269 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.837269 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199919.526585 # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199919.526585 # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171774.002782 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171774.002782 # average overall mshr uncacheable latency
+system.cpu.dcache.writebacks::writebacks 1558302 # number of writebacks
+system.cpu.dcache.writebacks::total 1558302 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 835082 # number of ReadReq MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 880000 # number of overall MSHR hits
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+system.cpu.dcache.SoftPFReq_mshr_misses::total 402839 # number of SoftPFReq MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 1658469 # number of overall MSHR misses
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+system.cpu.dcache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
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+system.cpu.dcache.WriteReq_mshr_uncacheable::total 13931 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587407 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 587407 # number of overall MSHR uncacheable misses
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total 19116755234 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6811295000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6811295000 # number of SoftPFReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 33410496734 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 40221791734 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98116957000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98116957000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2783856500 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::total 100900813500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076512 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076512 # mshr miss rate for ReadReq accesses
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+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858200 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858200 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059692 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.059692 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077122 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.077122 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14800.602949 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14800.602949 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65948.044109 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65948.044109 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16908.231328 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.231328 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26608.552467 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26608.552467 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24252.362712 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24252.362712 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.653356 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.653356 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199831.778049 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199831.778049 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171773.256873 # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171773.256873 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements 76780 # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse 15.821773 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 101894 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs 76796 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 1.326814 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 199830391500 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821773 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988861 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988861 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses 437119 # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses 437119 # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 101894 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 101894 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 101894 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 101894 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 101894 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 101894 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77777 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 77777 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77777 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 77777 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77777 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 77777 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 965958500 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 965958500 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 965958500 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total 965958500 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 965958500 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total 965958500 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 179671 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 179671 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 179671 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 179671 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 179671 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 179671 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.432886 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.432886 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.432886 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.432886 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.432886 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.432886 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12419.590624 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12419.590624 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12419.590624 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12419.590624 # average overall miss latency
+system.cpu.dtb_walker_cache.tags.replacements 70584 # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse 15.821836 # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs 110496 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs 70598 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs 1.565143 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 199830439500 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821836 # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988865 # Average percentage of cache occupancy
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@@ -822,182 +822,182 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1006,187 +1006,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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@@ -1195,188 +1195,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188413.986618 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188413.986618 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159297.440747 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159297.440747 # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823594 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823594 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459919 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459919 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016613 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000548 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026094 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024783 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000548 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101497 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.068097 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000548 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101497 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.068097 # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68715.194110 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68715.194110 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117815.636570 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117815.636570 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124044.989639 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124044.989639 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125505.771474 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125523.726497 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124044.989639 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119449.087781 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119859.101022 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124044.989639 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119449.087781 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119859.101022 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.566168 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.566168 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188326.250808 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188326.250808 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159296.756763 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159296.756763 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5460741 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2718937 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 72407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 1221 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1221 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 5434918 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2706203 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 65803 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1240 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 573460 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3016607 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13899 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13899 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 1731587 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 980190 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 117679 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2259 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2259 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 287973 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 287973 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 981903 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1461779 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3003914 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 13931 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 13931 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 1730558 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 975620 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 168030 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2247 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2247 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 287779 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 287779 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 976205 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1454773 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq 1647 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2943868 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6146532 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31429 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 174582 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 9296411 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125565760 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207412623 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 951488 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5659456 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 339589327 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 223808 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3529303 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.021448 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.165576 # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2927884 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6146809 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 37703 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 206355 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 9318751 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 124907456 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207405643 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 858816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5441920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 338613835 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 220482 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3516168 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.019658 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.160049 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 3464951 98.18% 98.18% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 53009 1.50% 99.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 11343 0.32% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 3458199 98.35% 98.35% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 46816 1.33% 99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 11153 0.32% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3529303 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5594725985 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3516168 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5575385475 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 671790 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 661286 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1474740212 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1466090916 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3066745270 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3066273273 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 21763478 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 20730469 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 116728873 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 107476352 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 212016 # Transaction distribution
-system.iobus.trans_dist::ReadResp 212016 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57726 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1645 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1645 # Transaction distribution
+system.iobus.trans_dist::ReadReq 212032 # Transaction distribution
+system.iobus.trans_dist::ReadResp 212032 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57756 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57756 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1647 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1647 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
@@ -1391,15 +1391,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 444236 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 542774 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 542870 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
@@ -1414,37 +1414,37 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 228398 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3262754 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 3980596 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6588 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6588 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3262814 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3982096 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 42500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 10514500 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 10538500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 1031500 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 1023500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy 92500 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 59500 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 32500 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 300003000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 1175500 # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy 1174500 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 24561500 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 24563000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
@@ -1452,27 +1452,27 @@ system.iobus.reqLayer15.occupancy 10000 # La
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 12500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 241121329 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 242078063 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 1231500 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 1233000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 433230000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 50160000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1647000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 47569 # number of replacements
-system.iocache.tags.tagsinuse 0.116025 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 0.116006 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4999365177000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116025 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007252 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.007252 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 4999354367000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116006 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007250 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.007250 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
@@ -1486,14 +1486,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 904
system.iocache.demand_misses::total 904 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses
system.iocache.overall_misses::total 904 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 145501183 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 145501183 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6077027146 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 6077027146 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 145501183 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 145501183 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 145501183 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 145501183 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149927198 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 149927198 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867794865 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 5867794865 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 149927198 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 149927198 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 149927198 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 149927198 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
@@ -1510,19 +1510,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 160952.636062 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 130073.355009 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130073.355009 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 160952.636062 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 160952.636062 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 1232 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 165848.670354 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125594.924336 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125594.924336 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 165848.670354 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 165848.670354 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 254 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 114 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 23 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.807018 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 11.043478 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -1536,14 +1536,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 904
system.iocache.demand_mshr_misses::total 904 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 904 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 904 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 100301183 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3741027146 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 3741027146 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 100301183 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 100301183 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 104727198 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3529874733 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 3529874733 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 104727198 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 104727198 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
@@ -1552,81 +1552,80 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 110952.636062 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80073.355009 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80073.355009 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115848.670354 # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75553.825621 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.825621 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115848.670354 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115848.670354 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 573460 # Transaction distribution
-system.membus.trans_dist::ReadResp 626337 # Transaction distribution
-system.membus.trans_dist::WriteReq 13899 # Transaction distribution
-system.membus.trans_dist::WriteResp 13899 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 149184 # Transaction distribution
-system.membus.trans_dist::CleanEvict 9829 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1709 # Transaction distribution
-system.membus.trans_dist::ReadExReq 132252 # Transaction distribution
-system.membus.trans_dist::ReadExResp 132250 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 52886 # Transaction distribution
-system.membus.trans_dist::MessageReq 1645 # Transaction distribution
-system.membus.trans_dist::MessageResp 1645 # Transaction distribution
-system.membus.trans_dist::BadAddressError 9 # Transaction distribution
+system.membus.trans_dist::ReadReq 573476 # Transaction distribution
+system.membus.trans_dist::ReadResp 626351 # Transaction distribution
+system.membus.trans_dist::WriteReq 13931 # Transaction distribution
+system.membus.trans_dist::WriteResp 13931 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 148924 # Transaction distribution
+system.membus.trans_dist::CleanEvict 10358 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2192 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 19 # Transaction distribution
+system.membus.trans_dist::ReadExReq 132088 # Transaction distribution
+system.membus.trans_dist::ReadExResp 132085 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 52881 # Transaction distribution
+system.membus.trans_dist::MessageReq 1647 # Transaction distribution
+system.membus.trans_dist::MessageResp 1647 # Transaction distribution
+system.membus.trans_dist::BadAddressError 6 # Transaction distribution
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444236 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730482 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 483648 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658384 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141810 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 141810 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1803484 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228398 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460961 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18308608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19997967 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3294 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3294 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730486 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 481353 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1656179 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95636 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 95636 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1755109 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6588 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6588 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460969 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18281344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19970763 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 23019587 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 1629 # Total snoops (count)
-system.membus.snoop_fanout::samples 982619 # Request fanout histogram
-system.membus.snoop_fanout::mean 1.001674 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.040881 # Request fanout histogram
+system.membus.pkt_size::total 22992391 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1583 # Total snoops (count)
+system.membus.snoop_fanout::samples 982226 # Request fanout histogram
+system.membus.snoop_fanout::mean 1.001677 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.040914 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 980974 99.83% 99.83% # Request fanout histogram
-system.membus.snoop_fanout::2 1645 0.17% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 980579 99.83% 99.83% # Request fanout histogram
+system.membus.snoop_fanout::2 1647 0.17% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
-system.membus.snoop_fanout::total 982619 # Request fanout histogram
-system.membus.reqLayer0.occupancy 339006500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 982226 # Request fanout histogram
+system.membus.reqLayer0.occupancy 339026000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 369115500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 369109500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3980404 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3981904 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1013900787 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1012407982 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 12000 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 2335404 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 2334904 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2139201818 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 2135091502 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 85763851 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 4662400 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
index fd3501a6f..c56d79e86 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 5.221334 # Nu
sim_ticks 5221333868500 # Number of ticks simulated
final_tick 5221333868500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 155160 # Simulator instruction rate (inst/s)
-host_op_rate 301283 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5363173075 # Simulator tick rate (ticks/s)
-host_mem_usage 777200 # Number of bytes of host memory used
-host_seconds 973.55 # Real time elapsed on the host
+host_inst_rate 231127 # Simulator instruction rate (inst/s)
+host_op_rate 448792 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7989012150 # Simulator tick rate (ticks/s)
+host_mem_usage 840496 # Number of bytes of host memory used
+host_seconds 653.56 # Real time elapsed on the host
sim_insts 151056351 # Number of instructions simulated
sim_ops 293314763 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -568,37 +568,37 @@ system.ruby.delayHist::mean 0.431734 # de
system.ruby.delayHist::stdev 1.809496 # delay histogram for all message
system.ruby.delayHist | 10578004 94.61% 94.61% | 2065 0.02% 94.63% | 600258 5.37% 99.99% | 191 0.00% 100.00% | 301 0.00% 100.00% | 12 0.00% 100.00% | 64 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 11180898 # delay histogram for all message
-system.ruby.outstanding_req_hist::bucket_size 1
-system.ruby.outstanding_req_hist::max_bucket 9
-system.ruby.outstanding_req_hist::samples 197955008
-system.ruby.outstanding_req_hist::mean 1.000129
-system.ruby.outstanding_req_hist::gmean 1.000089
-system.ruby.outstanding_req_hist::stdev 0.011356
-system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 197929478 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 197955008
-system.ruby.latency_hist::bucket_size 128
-system.ruby.latency_hist::max_bucket 1279
-system.ruby.latency_hist::samples 197955007
-system.ruby.latency_hist::mean 1.340882
-system.ruby.latency_hist::gmean 1.042158
-system.ruby.latency_hist::stdev 5.088799
-system.ruby.latency_hist | 197919440 99.98% 99.98% | 26716 0.01% 100.00% | 2921 0.00% 100.00% | 3323 0.00% 100.00% | 1640 0.00% 100.00% | 892 0.00% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00%
-system.ruby.latency_hist::total 197955007
-system.ruby.hit_latency_hist::bucket_size 1
-system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 195243038
-system.ruby.hit_latency_hist::mean 1
-system.ruby.hit_latency_hist::gmean 1
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 195243038 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 195243038
-system.ruby.miss_latency_hist::bucket_size 128
-system.ruby.miss_latency_hist::max_bucket 1279
-system.ruby.miss_latency_hist::samples 2711969
-system.ruby.miss_latency_hist::mean 25.882013
-system.ruby.miss_latency_hist::gmean 20.371762
-system.ruby.miss_latency_hist::stdev 35.771321
-system.ruby.miss_latency_hist | 2676402 98.69% 98.69% | 26716 0.99% 99.67% | 2921 0.11% 99.78% | 3323 0.12% 99.90% | 1640 0.06% 99.96% | 892 0.03% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00%
-system.ruby.miss_latency_hist::total 2711969
+system.ruby.outstanding_req_hist_seqr::bucket_size 1
+system.ruby.outstanding_req_hist_seqr::max_bucket 9
+system.ruby.outstanding_req_hist_seqr::samples 197955008
+system.ruby.outstanding_req_hist_seqr::mean 1.000129
+system.ruby.outstanding_req_hist_seqr::gmean 1.000089
+system.ruby.outstanding_req_hist_seqr::stdev 0.011356
+system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 197929478 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 197955008
+system.ruby.latency_hist_seqr::bucket_size 128
+system.ruby.latency_hist_seqr::max_bucket 1279
+system.ruby.latency_hist_seqr::samples 197955007
+system.ruby.latency_hist_seqr::mean 1.340882
+system.ruby.latency_hist_seqr::gmean 1.042158
+system.ruby.latency_hist_seqr::stdev 5.088799
+system.ruby.latency_hist_seqr | 197919440 99.98% 99.98% | 26716 0.01% 100.00% | 2921 0.00% 100.00% | 3323 0.00% 100.00% | 1640 0.00% 100.00% | 892 0.00% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00%
+system.ruby.latency_hist_seqr::total 197955007
+system.ruby.hit_latency_hist_seqr::bucket_size 1
+system.ruby.hit_latency_hist_seqr::max_bucket 9
+system.ruby.hit_latency_hist_seqr::samples 195243038
+system.ruby.hit_latency_hist_seqr::mean 1
+system.ruby.hit_latency_hist_seqr::gmean 1
+system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 195243038 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist_seqr::total 195243038
+system.ruby.miss_latency_hist_seqr::bucket_size 128
+system.ruby.miss_latency_hist_seqr::max_bucket 1279
+system.ruby.miss_latency_hist_seqr::samples 2711969
+system.ruby.miss_latency_hist_seqr::mean 25.882013
+system.ruby.miss_latency_hist_seqr::gmean 20.371762
+system.ruby.miss_latency_hist_seqr::stdev 35.771321
+system.ruby.miss_latency_hist_seqr | 2676402 98.69% 98.69% | 26716 0.99% 99.67% | 2921 0.11% 99.78% | 3323 0.12% 99.90% | 1640 0.06% 99.96% | 892 0.03% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::total 2711969
system.ruby.l1_cntrl0.L1Dcache.demand_hits 16386626 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 1208734 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17595360 # Number of cache demand accesses
@@ -895,135 +895,135 @@ system.ruby.delayVCHist.vnet_2::mean 0.000069 # de
system.ruby.delayVCHist.vnet_2::stdev 0.011745 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 86983 100.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 86986 # delay histogram for vnet_2
-system.ruby.LD.latency_hist::bucket_size 128
-system.ruby.LD.latency_hist::max_bucket 1279
-system.ruby.LD.latency_hist::samples 15432045
-system.ruby.LD.latency_hist::mean 2.853347
-system.ruby.LD.latency_hist::gmean 1.313273
-system.ruby.LD.latency_hist::stdev 9.004183
-system.ruby.LD.latency_hist | 15417229 99.90% 99.90% | 12840 0.08% 99.99% | 810 0.01% 99.99% | 753 0.00% 100.00% | 313 0.00% 100.00% | 86 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00%
-system.ruby.LD.latency_hist::total 15432045
-system.ruby.LD.hit_latency_hist::bucket_size 1
-system.ruby.LD.hit_latency_hist::max_bucket 9
-system.ruby.LD.hit_latency_hist::samples 13998259
-system.ruby.LD.hit_latency_hist::mean 1
-system.ruby.LD.hit_latency_hist::gmean 1
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 13998259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 13998259
-system.ruby.LD.miss_latency_hist::bucket_size 128
-system.ruby.LD.miss_latency_hist::max_bucket 1279
-system.ruby.LD.miss_latency_hist::samples 1433786
-system.ruby.LD.miss_latency_hist::mean 20.947839
-system.ruby.LD.miss_latency_hist::gmean 18.787632
-system.ruby.LD.miss_latency_hist::stdev 22.620333
-system.ruby.LD.miss_latency_hist | 1418970 98.97% 98.97% | 12840 0.90% 99.86% | 810 0.06% 99.92% | 753 0.05% 99.97% | 313 0.02% 99.99% | 86 0.01% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 1433786
-system.ruby.ST.latency_hist::bucket_size 128
-system.ruby.ST.latency_hist::max_bucket 1279
-system.ruby.ST.latency_hist::samples 9612989
-system.ruby.ST.latency_hist::mean 3.237898
-system.ruby.ST.latency_hist::gmean 1.143931
-system.ruby.ST.latency_hist::stdev 17.979843
-system.ruby.ST.latency_hist | 9598427 99.85% 99.85% | 8665 0.09% 99.94% | 1602 0.02% 99.96% | 2295 0.02% 99.98% | 1192 0.01% 99.99% | 757 0.01% 100.00% | 4 0.00% 100.00% | 23 0.00% 100.00% | 18 0.00% 100.00% | 6 0.00% 100.00%
-system.ruby.ST.latency_hist::total 9612989
-system.ruby.ST.hit_latency_hist::bucket_size 1
-system.ruby.ST.hit_latency_hist::max_bucket 9
-system.ruby.ST.hit_latency_hist::samples 9259401
-system.ruby.ST.hit_latency_hist::mean 1
-system.ruby.ST.hit_latency_hist::gmean 1
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 9259401 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 9259401
-system.ruby.ST.miss_latency_hist::bucket_size 128
-system.ruby.ST.miss_latency_hist::max_bucket 1279
-system.ruby.ST.miss_latency_hist::samples 353588
-system.ruby.ST.miss_latency_hist::mean 61.841694
-system.ruby.ST.miss_latency_hist::gmean 38.700068
-system.ruby.ST.miss_latency_hist::stdev 72.272561
-system.ruby.ST.miss_latency_hist | 339026 95.88% 95.88% | 8665 2.45% 98.33% | 1602 0.45% 98.79% | 2295 0.65% 99.43% | 1192 0.34% 99.77% | 757 0.21% 99.99% | 4 0.00% 99.99% | 23 0.01% 99.99% | 18 0.01% 100.00% | 6 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 353588
-system.ruby.IFETCH.latency_hist::bucket_size 128
-system.ruby.IFETCH.latency_hist::max_bucket 1279
-system.ruby.IFETCH.latency_hist::samples 171728771
-system.ruby.IFETCH.latency_hist::mean 1.087728
-system.ruby.IFETCH.latency_hist::gmean 1.013814
-system.ruby.IFETCH.latency_hist::stdev 1.877484
-system.ruby.IFETCH.latency_hist | 171723029 100.00% 100.00% | 4832 0.00% 100.00% | 479 0.00% 100.00% | 259 0.00% 100.00% | 120 0.00% 100.00% | 42 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 171728771
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-system.ruby.IFETCH.hit_latency_hist::max_bucket 9
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-system.ruby.IFETCH.hit_latency_hist::mean 1
-system.ruby.IFETCH.hit_latency_hist::gmean 1
-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 170908500 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.IFETCH.miss_latency_hist::max_bucket 1279
-system.ruby.IFETCH.miss_latency_hist::samples 820271
-system.ruby.IFETCH.miss_latency_hist::mean 19.366341
-system.ruby.IFETCH.miss_latency_hist::gmean 17.675078
-system.ruby.IFETCH.miss_latency_hist::stdev 20.056386
-system.ruby.IFETCH.miss_latency_hist | 814529 99.30% 99.30% | 4832 0.59% 99.89% | 479 0.06% 99.95% | 259 0.03% 99.98% | 120 0.01% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.RMW_Read.latency_hist::bucket_size 128
-system.ruby.RMW_Read.latency_hist::max_bucket 1279
-system.ruby.RMW_Read.latency_hist::samples 500824
-system.ruby.RMW_Read.latency_hist::mean 4.015135
-system.ruby.RMW_Read.latency_hist::gmean 1.504010
-system.ruby.RMW_Read.latency_hist::stdev 10.229460
-system.ruby.RMW_Read.latency_hist | 500636 99.96% 99.96% | 143 0.03% 99.99% | 19 0.00% 99.99% | 10 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.RMW_Read.hit_latency_hist::max_bucket 9
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-system.ruby.RMW_Read.hit_latency_hist::mean 1
-system.ruby.RMW_Read.hit_latency_hist::gmean 1
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-system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279
-system.ruby.RMW_Read.miss_latency_hist::samples 66002
-system.ruby.RMW_Read.miss_latency_hist::mean 23.878882
-system.ruby.RMW_Read.miss_latency_hist::gmean 22.130008
-system.ruby.RMW_Read.miss_latency_hist::stdev 18.427339
-system.ruby.RMW_Read.miss_latency_hist | 65814 99.72% 99.72% | 143 0.22% 99.93% | 19 0.03% 99.96% | 10 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.miss_latency_hist::total 66002
-system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64
-system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639
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-system.ruby.Locked_RMW_Read.latency_hist::stdev 8.368395
-system.ruby.Locked_RMW_Read.latency_hist | 339841 99.90% 99.90% | 89 0.03% 99.92% | 235 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00%
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-system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301867
-system.ruby.Locked_RMW_Read.hit_latency_hist::mean 1
-system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 1
-system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639
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-system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.638998
-system.ruby.Locked_RMW_Read.miss_latency_hist | 37974 99.09% 99.09% | 89 0.23% 99.32% | 235 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00%
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-system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.LD.latency_hist_seqr::stdev 9.004183
+system.ruby.LD.latency_hist_seqr | 15417229 99.90% 99.90% | 12840 0.08% 99.99% | 810 0.01% 99.99% | 753 0.00% 100.00% | 313 0.00% 100.00% | 86 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00%
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+system.ruby.LD.hit_latency_hist_seqr::gmean 1
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+system.ruby.LD.miss_latency_hist_seqr::bucket_size 128
+system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279
+system.ruby.LD.miss_latency_hist_seqr::samples 1433786
+system.ruby.LD.miss_latency_hist_seqr::mean 20.947839
+system.ruby.LD.miss_latency_hist_seqr::gmean 18.787632
+system.ruby.LD.miss_latency_hist_seqr::stdev 22.620333
+system.ruby.LD.miss_latency_hist_seqr | 1418970 98.97% 98.97% | 12840 0.90% 99.86% | 810 0.06% 99.92% | 753 0.05% 99.97% | 313 0.02% 99.99% | 86 0.01% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::total 1433786
+system.ruby.ST.latency_hist_seqr::bucket_size 128
+system.ruby.ST.latency_hist_seqr::max_bucket 1279
+system.ruby.ST.latency_hist_seqr::samples 9612989
+system.ruby.ST.latency_hist_seqr::mean 3.237898
+system.ruby.ST.latency_hist_seqr::gmean 1.143931
+system.ruby.ST.latency_hist_seqr::stdev 17.979843
+system.ruby.ST.latency_hist_seqr | 9598427 99.85% 99.85% | 8665 0.09% 99.94% | 1602 0.02% 99.96% | 2295 0.02% 99.98% | 1192 0.01% 99.99% | 757 0.01% 100.00% | 4 0.00% 100.00% | 23 0.00% 100.00% | 18 0.00% 100.00% | 6 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::total 9612989
+system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
+system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
+system.ruby.ST.hit_latency_hist_seqr::samples 9259401
+system.ruby.ST.hit_latency_hist_seqr::mean 1
+system.ruby.ST.hit_latency_hist_seqr::gmean 1
+system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9259401 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist_seqr::total 9259401
+system.ruby.ST.miss_latency_hist_seqr::bucket_size 128
+system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279
+system.ruby.ST.miss_latency_hist_seqr::samples 353588
+system.ruby.ST.miss_latency_hist_seqr::mean 61.841694
+system.ruby.ST.miss_latency_hist_seqr::gmean 38.700068
+system.ruby.ST.miss_latency_hist_seqr::stdev 72.272561
+system.ruby.ST.miss_latency_hist_seqr | 339026 95.88% 95.88% | 8665 2.45% 98.33% | 1602 0.45% 98.79% | 2295 0.65% 99.43% | 1192 0.34% 99.77% | 757 0.21% 99.99% | 4 0.00% 99.99% | 23 0.01% 99.99% | 18 0.01% 100.00% | 6 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::total 353588
+system.ruby.IFETCH.latency_hist_seqr::bucket_size 128
+system.ruby.IFETCH.latency_hist_seqr::max_bucket 1279
+system.ruby.IFETCH.latency_hist_seqr::samples 171728771
+system.ruby.IFETCH.latency_hist_seqr::mean 1.087728
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.013814
+system.ruby.IFETCH.latency_hist_seqr::stdev 1.877484
+system.ruby.IFETCH.latency_hist_seqr | 171723029 100.00% 100.00% | 4832 0.00% 100.00% | 479 0.00% 100.00% | 259 0.00% 100.00% | 120 0.00% 100.00% | 42 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::total 171728771
+system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
+system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
+system.ruby.IFETCH.hit_latency_hist_seqr::samples 170908500
+system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
+system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
+system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 170908500 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total 170908500
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128
+system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 1279
+system.ruby.IFETCH.miss_latency_hist_seqr::samples 820271
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 19.366341
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 17.675078
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 20.056386
+system.ruby.IFETCH.miss_latency_hist_seqr | 814529 99.30% 99.30% | 4832 0.59% 99.89% | 479 0.06% 99.95% | 259 0.03% 99.98% | 120 0.01% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::total 820271
+system.ruby.RMW_Read.latency_hist_seqr::bucket_size 128
+system.ruby.RMW_Read.latency_hist_seqr::max_bucket 1279
+system.ruby.RMW_Read.latency_hist_seqr::samples 500824
+system.ruby.RMW_Read.latency_hist_seqr::mean 4.015135
+system.ruby.RMW_Read.latency_hist_seqr::gmean 1.504010
+system.ruby.RMW_Read.latency_hist_seqr::stdev 10.229460
+system.ruby.RMW_Read.latency_hist_seqr | 500636 99.96% 99.96% | 143 0.03% 99.99% | 19 0.00% 99.99% | 10 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.RMW_Read.latency_hist_seqr::total 500824
+system.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 1
+system.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 9
+system.ruby.RMW_Read.hit_latency_hist_seqr::samples 434822
+system.ruby.RMW_Read.hit_latency_hist_seqr::mean 1
+system.ruby.RMW_Read.hit_latency_hist_seqr::gmean 1
+system.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 434822 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.RMW_Read.hit_latency_hist_seqr::total 434822
+system.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 128
+system.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 1279
+system.ruby.RMW_Read.miss_latency_hist_seqr::samples 66002
+system.ruby.RMW_Read.miss_latency_hist_seqr::mean 23.878882
+system.ruby.RMW_Read.miss_latency_hist_seqr::gmean 22.130008
+system.ruby.RMW_Read.miss_latency_hist_seqr::stdev 18.427339
+system.ruby.RMW_Read.miss_latency_hist_seqr | 65814 99.72% 99.72% | 143 0.22% 99.93% | 19 0.03% 99.96% | 10 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.RMW_Read.miss_latency_hist_seqr::total 66002
+system.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 64
+system.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 639
+system.ruby.Locked_RMW_Read.latency_hist_seqr::samples 340189
+system.ruby.Locked_RMW_Read.latency_hist_seqr::mean 3.322221
+system.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 1.405053
+system.ruby.Locked_RMW_Read.latency_hist_seqr::stdev 8.368395
+system.ruby.Locked_RMW_Read.latency_hist_seqr | 339841 99.90% 99.90% | 89 0.03% 99.92% | 235 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00%
+system.ruby.Locked_RMW_Read.latency_hist_seqr::total 340189
+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::bucket_size 1
+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::max_bucket 9
+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::samples 301867
+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::mean 1
+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::gmean 1
+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::total 301867
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 64
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 639
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 38322
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 21.614634
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 20.468455
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::stdev 15.638998
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 37974 99.09% 99.09% | 89 0.23% 99.32% | 235 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00%
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 38322
+system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1
+system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9
+system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 340189
+system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 1
+system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 1
+system.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Locked_RMW_Write.latency_hist_seqr::total 340189
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::bucket_size 1
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::max_bucket 9
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::samples 340189
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::mean 1
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::gmean 1
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::total 340189
system.ruby.Directory_Controller.Fetch 181234 0.00% 0.00%
system.ruby.Directory_Controller.Data 103288 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 181708 0.00% 0.00%
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index df59304a0..e92014927 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,152 +1,156 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.142345 # Number of seconds simulated
-sim_ticks 5142345332000 # Number of ticks simulated
-final_tick 5142345332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.145152 # Number of seconds simulated
+sim_ticks 5145151650500 # Number of ticks simulated
+final_tick 5145151650500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 328643 # Simulator instruction rate (inst/s)
-host_op_rate 653294 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6944434004 # Simulator tick rate (ticks/s)
-host_mem_usage 993680 # Number of bytes of host memory used
-host_seconds 740.50 # Real time elapsed on the host
-sim_insts 243359937 # Number of instructions simulated
-sim_ops 483763631 # Number of ops (including micro ops) simulated
+host_inst_rate 272385 # Simulator instruction rate (inst/s)
+host_op_rate 541465 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5759353840 # Simulator tick rate (ticks/s)
+host_mem_usage 1031560 # Number of bytes of host memory used
+host_seconds 893.36 # Real time elapsed on the host
+sim_insts 243336751 # Number of instructions simulated
+sim_ops 483720414 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 463872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5043712 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 148160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2254656 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 338432 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 3039936 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 460480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5461312 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 120640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2033024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 2048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 372928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2832128 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11319616 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 463872 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 148160 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 338432 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 950464 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9139904 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9139904 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7248 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 78808 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2315 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 35229 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 5288 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 47499 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 11311232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 460480 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 120640 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 372928 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 954048 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9134592 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9134592 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 7195 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 85333 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1885 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 31766 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 32 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 5827 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 44252 # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 176869 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 142811 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 142811 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 90206 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 980819 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 28812 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 438449 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 423 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 65813 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 591157 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5513 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2201256 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 90206 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 28812 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 65813 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 184831 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1777380 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1777380 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1777380 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 90206 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 980819 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 28812 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 438449 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 423 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 65813 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 591157 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5513 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3978636 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 90808 # Number of read requests accepted
-system.physmem.writeReqs 80864 # Number of write requests accepted
-system.physmem.readBursts 90808 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 80864 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 5799936 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11776 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5173504 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 5811712 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 5175296 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 184 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total 176738 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 142728 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 142728 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 89498 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1061448 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 23447 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 395134 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 398 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 72481 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 550446 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide 5510 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2198425 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 89498 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 23447 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 72481 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 185427 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1775379 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1775379 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1775379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 89498 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1061448 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 23447 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 395134 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.writeBursts 79488 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 5382080 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
+system.physmem.bytesWritten 5087168 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 5389184 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 5087232 # Total written bytes from the system interface side
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 28946 # Number of requests that are neither read nor write
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
-system.physmem.totGap 5141345197000 # Total gap between requests
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+system.physmem.totGap 5144151504000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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@@ -161,1038 +165,1041 @@ system.physmem.rdQLenPdf::28 0 # Wh
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-system.physmem.bytesPerActivate::1024-1151 3343 8.32% 100.00% # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::12-15 5 0.12% 1.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 3465 84.59% 86.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 91 2.22% 88.70% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::28-31 114 2.78% 92.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 13 0.32% 92.58% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::64-67 111 2.71% 99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 4 0.10% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 2 0.05% 99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 16 0.39% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 1 0.02% 99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 3 0.07% 99.76% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::124-127 1 0.02% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 6 0.15% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 4096 # Writes before turning the bus around for reads
-system.physmem.totQLat 1084591495 # Total ticks spent queuing
-system.physmem.totMemAccLat 2783791495 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 453120000 # Total ticks spent in databus transfers
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+system.physmem.wrQLenPdf::41 127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 95 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 114 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 71 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 38528 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 271.729236 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 163.741988 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 299.469956 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 15728 40.82% 40.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 9476 24.60% 65.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4018 10.43% 75.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2235 5.80% 81.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1484 3.85% 85.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1040 2.70% 88.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 621 1.61% 89.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 586 1.52% 91.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 3340 8.67% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 38528 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3767 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.323865 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 241.560167 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 3765 99.95% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047 1 0.03% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-14847 1 0.03% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 3767 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3767 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 21.100876 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.013157 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 16.139837 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 73 1.94% 1.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 5 0.13% 2.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 2 0.05% 2.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 10 0.27% 2.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 3150 83.62% 86.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 90 2.39% 88.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 37 0.98% 89.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 29 0.77% 90.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 11 0.29% 90.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 15 0.40% 90.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 49 1.30% 92.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 5 0.13% 92.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 97 2.57% 94.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 5 0.13% 94.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 5 0.13% 95.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 6 0.16% 95.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 56 1.49% 96.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 2 0.05% 96.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.11% 96.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 26 0.69% 97.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 71 1.88% 99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.03% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 9 0.24% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.03% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 2 0.05% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.03% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 4 0.11% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191 1 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 3767 # Writes before turning the bus around for reads
+system.physmem.totQLat 976693078 # Total ticks spent queuing
+system.physmem.totMemAccLat 2553474328 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 420475000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11614.16 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30718.04 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.13 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.01 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.13 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.01 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30364.16 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.99 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 7.79 # Average write queue length when enqueuing
-system.physmem.readRowHits 72353 # Number of row buffer hits during reads
-system.physmem.writeRowHits 58932 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 72.88 # Row buffer hit rate for writes
-system.physmem.avgGap 29948653.23 # Average gap between requests
-system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 144214560 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 78573000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 335010000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 259511040 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 250484108160 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 96378538635 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2237986517250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 2585666472645 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.978665 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 3687486057488 # Time in different power states
-system.physmem_0.memoryStateTime::REF 128059360000 # Time in different power states
+system.physmem.avgWrQLen 6.49 # Average write queue length when enqueuing
+system.physmem.readRowHits 66583 # Number of row buffer hits during reads
+system.physmem.writeRowHits 58470 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 79.18 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.56 # Row buffer hit rate for writes
+system.physmem.avgGap 31425412.68 # Average gap between requests
+system.physmem.pageHitRate 76.45 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 137463480 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 74835750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 309129600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 254612160 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 250601076960 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 95881334760 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2241313470000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 2588571922710 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.897936 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 3690036314984 # Time in different power states
+system.physmem_0.memoryStateTime::REF 128119160000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 19884905262 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 19076389516 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 159500880 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 86876625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 371841600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 264306240 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 250484108160 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 97163933940 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2232534954750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 2581065522195 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.160201 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 3686335779224 # Time in different power states
-system.physmem_1.memoryStateTime::REF 128059360000 # Time in different power states
+system.physmem_1.actEnergy 153808200 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 83729250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 346803600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 260463600 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 250601076960 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 96592845240 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2234121702750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 2582160429600 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.130643 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 3689011276980 # Time in different power states
+system.physmem_1.memoryStateTime::REF 128119160000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 21009267026 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 20078331770 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 1088115959 # number of cpu cycles simulated
+system.cpu0.numCycles 1088692410 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.committedInsts 71651877 # Number of instructions committed
-system.cpu0.committedOps 146177129 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 134125177 # Number of integer alu accesses
+system.cpu0.committedInsts 72035509 # Number of instructions committed
+system.cpu0.committedOps 146805199 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 134737053 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 958449 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 14231951 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 134125177 # number of integer instructions
+system.cpu0.num_func_calls 969730 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 14267962 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 134737053 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 245781224 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 115362346 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 247210570 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 115779061 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 83627387 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 55829285 # number of times the CC registers were written
-system.cpu0.num_mem_refs 13623500 # number of memory refs
-system.cpu0.num_load_insts 10168797 # Number of load instructions
-system.cpu0.num_store_insts 3454703 # Number of store instructions
-system.cpu0.num_idle_cycles 1031530406.657702 # Number of idle cycles
-system.cpu0.num_busy_cycles 56585552.342298 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.052003 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.947997 # Percentage of idle cycles
-system.cpu0.Branches 15545637 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 91075 0.06% 0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu 132356346 90.54% 90.61% # Class of executed instruction
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-system.cpu0.op_class::IntDiv 49650 0.03% 90.68% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.68% # Class of executed instruction
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-system.cpu0.op_class::SimdMisc 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 90.68% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.68% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.68% # Class of executed instruction
-system.cpu0.op_class::MemRead 10166974 6.96% 97.64% # Class of executed instruction
-system.cpu0.op_class::MemWrite 3454703 2.36% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 83908421 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 55985088 # number of times the CC registers were written
+system.cpu0.num_mem_refs 13846193 # number of memory refs
+system.cpu0.num_load_insts 10242461 # Number of load instructions
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+system.cpu0.num_busy_cycles 56410521.327765 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.051815 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.948185 # Percentage of idle cycles
+system.cpu0.Branches 15596726 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 94997 0.06% 0.06% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 146177571 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 1639042 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.999458 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 19611882 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1639554 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 11.961718 # Average number of references to valid blocks.
+system.cpu0.op_class::total 146805721 # Class of executed instruction
+system.cpu0.dcache.tags.replacements 1638200 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999475 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 19659628 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1638712 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 11.997000 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 186.987910 # Average occupied blocks per requestor
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172565.280011 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 863213 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.772348 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 129563028 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 863725 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 150.004953 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 149035233500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 148.852314 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 120.504208 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 241.415826 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.290727 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.235360 # Average percentage of cache occupancy
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-system.cpu0.icache.tags.occ_percent::total 0.997602 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 861781 # number of replacements
+system.cpu0.icache.tags.tagsinuse 510.773422 # Cycle average of tags in use
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+system.cpu0.icache.demand_mshr_miss_rate::total 0.004163 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004258 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.112313 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.004163 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.646267 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14031.977197 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13824.083625 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.646267 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 14031.977197 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13824.083625 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.646267 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 14031.977197 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13824.083625 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 2608019031 # number of cpu cycles simulated
+system.cpu1.numCycles 2608700985 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.committedInsts 35872545 # Number of instructions committed
-system.cpu1.committedOps 69699402 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 64677814 # Number of integer alu accesses
+system.cpu1.committedInsts 35853190 # Number of instructions committed
+system.cpu1.committedOps 69637325 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 64624192 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 478121 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 6602854 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 64677814 # number of integer instructions
+system.cpu1.num_func_calls 480821 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 6584072 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 64624192 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 119785728 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 55703367 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 119734930 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 55665261 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 36592003 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 27221835 # number of times the CC registers were written
-system.cpu1.num_mem_refs 4725252 # number of memory refs
-system.cpu1.num_load_insts 2891470 # Number of load instructions
-system.cpu1.num_store_insts 1833782 # Number of store instructions
-system.cpu1.num_idle_cycles 2475574417.457654 # Number of idle cycles
-system.cpu1.num_busy_cycles 132444613.542345 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.050784 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.949216 # Percentage of idle cycles
-system.cpu1.Branches 7256649 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 36799 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 64882747 93.09% 93.14% # Class of executed instruction
-system.cpu1.op_class::IntMult 30615 0.04% 93.19% # Class of executed instruction
-system.cpu1.op_class::IntDiv 25662 0.04% 93.22% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.22% # Class of executed instruction
-system.cpu1.op_class::MemRead 2890134 4.15% 97.37% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1833782 2.63% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 36441615 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 27163948 # number of times the CC registers were written
+system.cpu1.num_mem_refs 4762653 # number of memory refs
+system.cpu1.num_load_insts 2934148 # Number of load instructions
+system.cpu1.num_store_insts 1828505 # Number of store instructions
+system.cpu1.num_idle_cycles 2477829433.289960 # Number of idle cycles
+system.cpu1.num_busy_cycles 130871551.710040 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.050167 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.949833 # Percentage of idle cycles
+system.cpu1.Branches 7242423 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 33618 0.05% 0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu 64788264 93.04% 93.08% # Class of executed instruction
+system.cpu1.op_class::IntMult 30568 0.04% 93.13% # Class of executed instruction
+system.cpu1.op_class::IntDiv 23981 0.03% 93.16% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.16% # Class of executed instruction
+system.cpu1.op_class::MemRead 2932794 4.21% 97.37% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1828505 2.63% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 69699739 # Class of executed instruction
-system.cpu2.branchPred.lookups 28904699 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 28904699 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 301799 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 26182960 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 25618019 # Number of BTB hits
+system.cpu1.op_class::total 69637730 # Class of executed instruction
+system.cpu2.branchPred.lookups 28889322 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 28889322 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 295969 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 26161863 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 25623496 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 97.842333 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 577766 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 65377 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 157028917 # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct 97.942169 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 568311 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 63642 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 155802495 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 10756065 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 142934226 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 28904699 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 26195785 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 144559167 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 634442 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 102497 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 11445 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 9293 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 61170 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 12 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 1572 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 3392030 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 159049 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 2822 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 155817791 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.805701 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 3.007704 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 10515897 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 142640150 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 28889322 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 26191807 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 143559452 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 620364 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 87827 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 9842 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 11126 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 54390 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 17 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 1387 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3356023 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 154184 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 2703 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 154549468 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.817375 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 3.013614 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 100969926 64.80% 64.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 864181 0.55% 65.35% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 23515186 15.09% 80.45% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 574321 0.37% 80.81% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 784323 0.50% 81.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 832797 0.53% 81.85% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 526849 0.34% 82.19% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 721182 0.46% 82.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 27029026 17.35% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 99785668 64.57% 64.57% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 851405 0.55% 65.12% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 23501964 15.21% 80.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 570178 0.37% 80.69% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 787471 0.51% 81.20% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 829399 0.54% 81.74% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 530756 0.34% 82.08% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 713885 0.46% 82.54% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 26978742 17.46% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 155817791 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.184072 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.910241 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 9372643 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 95636804 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 20963245 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 4000269 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 317872 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 278646605 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 317872 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 10991831 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 77276692 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 5181011 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 23079329 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 13444163 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 277492076 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 194116 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 5314185 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 68849 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 6513408 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 331462631 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 605120715 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 371802312 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 234 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 320362920 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 11099709 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 163935 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 165202 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 19836823 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6505105 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3734190 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 446981 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 391369 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 275686580 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 411981 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 273842853 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 94839 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 8211456 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 12322633 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 64605 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 155817791 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.757456 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 2.386043 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 154549468 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.185423 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.915519 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 9161947 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 94660451 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 22362416 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 3983614 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 310834 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 278186393 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 310834 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 10773754 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 76930615 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 4967111 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 24468455 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 13028558 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 277047338 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 190678 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 5336222 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 56223 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 6096944 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 331227284 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 604004541 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 370955338 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 211 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 319831441 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 11395843 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 155918 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 157041 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 19693984 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6408841 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3580904 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 429275 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 378401 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 275247067 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 403961 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 273265487 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 91844 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 8373138 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 12782922 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 62096 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 154549468 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.768143 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 2.389638 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 93841974 60.23% 60.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 5140662 3.30% 63.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 3701702 2.38% 65.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 3241767 2.08% 67.98% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 23231728 14.91% 82.89% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 2206356 1.42% 84.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 23779364 15.26% 99.57% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 455294 0.29% 99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 218944 0.14% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 92779587 60.03% 60.03% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 5028830 3.25% 63.29% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 3690380 2.39% 65.67% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 3236781 2.09% 67.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 23211705 15.02% 82.79% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 2188888 1.42% 84.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 23752986 15.37% 99.57% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 446110 0.29% 99.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 214201 0.14% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 155817791 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 154549468 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 1209883 81.76% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 208644 14.10% 95.86% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 61248 4.14% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 1203384 82.42% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 82.42% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 197980 13.56% 95.97% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 58776 4.03% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 74059 0.03% 0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 263387979 96.18% 96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 56208 0.02% 96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 48343 0.02% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 104 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 6817856 2.49% 98.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3458304 1.26% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 71495 0.03% 0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 263081199 96.27% 96.30% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 54839 0.02% 96.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 49922 0.02% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 90 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 6697042 2.45% 98.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3310900 1.21% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 273842853 # Type of FU issued
-system.cpu2.iq.rate 1.743901 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 1479775 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.005404 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 705077754 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 284314372 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 272343231 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 356 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 332 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 275248392 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 177 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 717023 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 273265487 # Type of FU issued
+system.cpu2.iq.rate 1.753922 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 1460140 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.005343 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 702632101 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 284028018 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 271786365 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 325 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 130 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 274653974 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 158 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 690819 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1119882 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 5658 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 5248 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 603569 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1132838 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 5529 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 4669 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 589748 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 712184 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 25029 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 711826 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 19138 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 317872 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 69999671 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 4334406 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 276098561 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 36227 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6505105 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3734190 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 245180 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 161697 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 3862519 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 5248 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 168896 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 180792 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 349688 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 273296807 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 6682967 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 496833 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 310834 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 69908252 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 4108684 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 275651028 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 34465 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6408841 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3580904 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 237862 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 162562 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 3635003 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 4669 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 168040 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 174694 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 342734 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 272728091 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 6566445 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 490893 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
-system.cpu2.iew.exec_refs 10058933 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 27720177 # Number of branches executed
-system.cpu2.iew.exec_stores 3375966 # Number of stores executed
-system.cpu2.iew.exec_rate 1.740423 # Inst execution rate
-system.cpu2.iew.wb_sent 273120714 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 272343375 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 212424693 # num instructions producing a value
-system.cpu2.iew.wb_consumers 348436865 # num instructions consuming a value
-system.cpu2.iew.wb_rate 1.734352 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.609650 # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts 8207919 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 347376 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 304652 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 154587808 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.732912 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.636931 # Number of insts commited each cycle
+system.cpu2.iew.exec_refs 9797112 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 27676327 # Number of branches executed
+system.cpu2.iew.exec_stores 3230667 # Number of stores executed
+system.cpu2.iew.exec_rate 1.750473 # Inst execution rate
+system.cpu2.iew.wb_sent 272561668 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 271786495 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 212223501 # num instructions producing a value
+system.cpu2.iew.wb_consumers 348135650 # num instructions consuming a value
+system.cpu2.iew.wb_rate 1.744430 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.609600 # average fanout of values written-back
+system.cpu2.commit.commitSquashedInsts 8370841 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 341865 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 298631 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 153304959 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.743439 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.641523 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 97422616 63.02% 63.02% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4263028 2.76% 65.78% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1258481 0.81% 66.59% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 24441508 15.81% 82.40% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 948995 0.61% 83.02% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 702646 0.45% 83.47% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 422583 0.27% 83.75% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 23085730 14.93% 98.68% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 2042221 1.32% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 96327195 62.83% 62.83% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4172265 2.72% 65.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1243558 0.81% 66.37% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 24424351 15.93% 82.30% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 933210 0.61% 82.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 700271 0.46% 83.36% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 423861 0.28% 83.64% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 23073889 15.05% 98.69% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 2006359 1.31% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 154587808 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 135835515 # Number of instructions committed
-system.cpu2.commit.committedOps 267887100 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 153304959 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 135448052 # Number of instructions committed
+system.cpu2.commit.committedOps 267277890 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8515843 # Number of memory references committed
-system.cpu2.commit.loads 5385222 # Number of loads committed
-system.cpu2.commit.membars 151391 # Number of memory barriers committed
-system.cpu2.commit.branches 27354284 # Number of branches committed
+system.cpu2.commit.refs 8267159 # Number of memory references committed
+system.cpu2.commit.loads 5276003 # Number of loads committed
+system.cpu2.commit.membars 150855 # Number of memory barriers committed
+system.cpu2.commit.branches 27313126 # Number of branches committed
system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 244770291 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 437535 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 44208 0.02% 0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 259226210 96.77% 96.78% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 54262 0.02% 96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 46624 0.02% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 5385159 2.01% 98.83% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 3130621 1.17% 100.00% # Class of committed instruction
+system.cpu2.commit.int_insts 244177571 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 431165 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 43823 0.02% 0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 258865945 96.85% 96.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 52891 0.02% 96.89% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 48103 0.02% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 5275956 1.97% 98.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 2991156 1.12% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 267887100 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 2042221 # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads 428611967 # The number of ROB reads
-system.cpu2.rob.rob_writes 553425779 # The number of ROB writes
-system.cpu2.timesIdled 117856 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1211126 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 4911627157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 135835515 # Number of Instructions Simulated
-system.cpu2.committedOps 267887100 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.156023 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.156023 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.865035 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.865035 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 364164831 # number of integer regfile reads
-system.cpu2.int_regfile_writes 218212592 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 73112 # number of floating regfile reads
+system.cpu2.commit.op_class_0::total 267277890 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 2006359 # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads 426921144 # The number of ROB reads
+system.cpu2.rob.rob_writes 552547339 # The number of ROB writes
+system.cpu2.timesIdled 113614 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1253027 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 4915786083 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 135448052 # Number of Instructions Simulated
+system.cpu2.committedOps 267277890 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.150275 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.150275 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.869357 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.869357 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 363036550 # number of integer regfile reads
+system.cpu2.int_regfile_writes 217868300 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 73154 # number of floating regfile reads
system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 138818129 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 106823368 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 88818544 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 142989 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 3545369 # Transaction distribution
-system.iobus.trans_dist::ReadResp 3545369 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57733 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57733 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1667 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1667 # Transaction distribution
+system.cpu2.cc_regfile_reads 138663599 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 106715601 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 88486209 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 136274 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 3545384 # Transaction distribution
+system.iobus.trans_dist::ReadResp 3545384 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57740 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57740 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1683 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1683 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066646 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1182 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27866 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27896 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 7110938 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95266 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95266 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3334 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3334 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 7209538 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 7110986 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3366 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3366 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 7209614 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533323 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2364 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13933 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13948 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 3561710 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027848 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027848 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6668 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6668 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 6596226 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 2386632 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 3561695 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes)
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@@ -1202,68 +1209,68 @@ system.iobus.reqLayer7.occupancy 21000 # La
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@@ -1601,208 +1622,220 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.428290 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.375181 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.213812 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011220 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.015459 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total 0.008944 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021789 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.016437 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.010920 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011220 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.111962 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000593 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000083 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015459 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.064279 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.032235 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011220 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.111962 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000593 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000083 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015459 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.064279 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.032235 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 139718.750000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 137000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 139636.363636 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67978.005865 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68098.611111 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68039.942939 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116754.770149 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119097.797610 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 118069.914193 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120466.843501 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 125488.074138 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124260.763485 # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122832.817337 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124750.430074 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124119.859034 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120466.843501 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117675.225831 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 139718.750000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 137000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 125488.074138 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 120350.461702 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 119700.925903 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120466.843501 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117675.225831 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 139718.750000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 137000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 125488.074138 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 120350.461702 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 119700.925903 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161432.375792 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157860.902663 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159561.252826 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183818.831375 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 195407.934132 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189783.942056 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161825.707909 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158497.163876 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 160082.384907 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 5063475 # Transaction distribution
-system.membus.trans_dist::ReadResp 5112044 # Transaction distribution
-system.membus.trans_dist::WriteReq 13928 # Transaction distribution
-system.membus.trans_dist::WriteResp 13928 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 142811 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8387 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 1702 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1702 # Transaction distribution
-system.membus.trans_dist::ReadExReq 129429 # Transaction distribution
-system.membus.trans_dist::ReadExResp 129429 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 48569 # Transaction distribution
-system.membus.trans_dist::MessageReq 1667 # Transaction distribution
-system.membus.trans_dist::MessageResp 1667 # Transaction distribution
+system.membus.trans_dist::ReadReq 5063492 # Transaction distribution
+system.membus.trans_dist::ReadResp 5112114 # Transaction distribution
+system.membus.trans_dist::WriteReq 13953 # Transaction distribution
+system.membus.trans_dist::WriteResp 13953 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 142728 # Transaction distribution
+system.membus.trans_dist::CleanEvict 8956 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 1657 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 756 # Transaction distribution
+system.membus.trans_dist::ReadExReq 129246 # Transaction distribution
+system.membus.trans_dist::ReadExResp 129246 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 48622 # Transaction distribution
+system.membus.trans_dist::MessageReq 1683 # Transaction distribution
+system.membus.trans_dist::MessageResp 1683 # Transaction distribution
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3334 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3334 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110938 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3043868 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 461232 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 10616038 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141982 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 141982 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10761354 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6668 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6668 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561710 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6087733 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17454144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 27103587 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 3025152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30135407 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 824 # Total snoops (count)
-system.membus.snoop_fanout::samples 5457240 # Request fanout histogram
-system.membus.snoop_fanout::mean 1.000305 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.017475 # Request fanout histogram
+system.membus.trans_dist::InvalidateResp 20624 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3366 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3366 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110986 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3043904 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 460036 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 10614926 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 116428 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 116428 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 10734720 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6732 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6732 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561695 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6087805 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17447936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 27097436 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3024896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3024896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30129064 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 713 # Total snoops (count)
+system.membus.snoop_fanout::samples 5457064 # Request fanout histogram
+system.membus.snoop_fanout::mean 1.000308 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.017559 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 5455573 99.97% 99.97% # Request fanout histogram
-system.membus.snoop_fanout::2 1667 0.03% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 5455381 99.97% 99.97% # Request fanout histogram
+system.membus.snoop_fanout::2 1683 0.03% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
-system.membus.snoop_fanout::total 5457240 # Request fanout histogram
-system.membus.reqLayer0.occupancy 220305500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 5457064 # Request fanout histogram
+system.membus.reqLayer0.occupancy 219508500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 286836500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 286793500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 2385368 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 2349452 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 534782231 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 523492338 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1398368 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1380452 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1230215238 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1192096252 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 43264654 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 3875571 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
@@ -1812,60 +1845,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.toL2Bus.snoop_filter.tot_requests 5045999 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 2542699 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 716 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 1209 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 1209 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 5037396 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 2536385 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 720 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 1161 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 1161 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 5211020 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 7425092 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 13930 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 13930 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 1629876 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 862717 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 95523 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 1686 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1686 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 289480 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 289480 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 863740 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 1350844 # Transaction distribution
-system.toL2Bus.trans_dist::MessageReq 987 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 22656 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2590172 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15076396 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 68863 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 204307 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 17939738 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110491648 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213734051 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 254408 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 750576 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 325230683 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 223463 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 8879878 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.004588 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.067577 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 5204527 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 7416348 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 13955 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 13955 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 1627719 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 861781 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 95177 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 1648 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1648 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 289427 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 289427 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 862301 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 1350048 # Transaction distribution
+system.toL2Bus.trans_dist::MessageReq 969 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 26096 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586381 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15074051 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 68680 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 194868 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 17923980 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110341120 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213628444 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 723128 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 324949652 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 219979 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 8897461 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.004125 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.064090 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 8839140 99.54% 99.54% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 40738 0.46% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 8860763 99.59% 99.59% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 36698 0.41% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 8879878 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 3300004999 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 8897461 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 3238433000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 437354 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 410366 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 839896281 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 817982794 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1865125250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1843572784 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 24363482 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 22804980 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 87735122 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 80183573 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed