diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 2543 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 2944 |
2 files changed, 2757 insertions, 2730 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 369e97796..da1db81af 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125717 # Number of seconds simulated -sim_ticks 5125716951000 # Number of ticks simulated -final_tick 5125716951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133763 # Number of seconds simulated +sim_ticks 5133762710000 # Number of ticks simulated +final_tick 5133762710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 203249 # Simulator instruction rate (inst/s) -host_op_rate 401765 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2555120499 # Simulator tick rate (ticks/s) -host_mem_usage 728844 # Number of bytes of host memory used -host_seconds 2006.06 # Real time elapsed on the host -sim_insts 407728401 # Number of instructions simulated -sim_ops 805963181 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2441920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1027200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10734912 # Number of bytes read from this memory -system.physmem.bytes_read::total 14208320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1027200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1027200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9480000 # Number of bytes written to this memory -system.physmem.bytes_written::total 9480000 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38155 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167733 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222005 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148125 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148125 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 200401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2094324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2771967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 200401 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 200401 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1849497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1849497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1849497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 200401 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2094324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4621465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222005 # Total number of read requests seen -system.physmem.writeReqs 148125 # Total number of write requests seen -system.physmem.cpureqs 371863 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14208320 # Total number of bytes read from memory -system.physmem.bytesWritten 9480000 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14208320 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9480000 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 92 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 14596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 13757 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13920 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14183 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 13262 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9305 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 9392 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 9725 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 9208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 9142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8580 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8586 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 10150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9429 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 9215 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8819 # Track writes on a per bank basis +host_inst_rate 199223 # Simulator instruction rate (inst/s) +host_op_rate 393808 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2508257843 # Simulator tick rate (ticks/s) +host_mem_usage 730904 # Number of bytes of host memory used +host_seconds 2046.74 # Real time elapsed on the host +sim_insts 407759186 # Number of instructions simulated +sim_ops 806023868 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2444032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1025408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10767936 # Number of bytes read from this memory +system.physmem.bytes_read::total 14241664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1025408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1025408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9508160 # Number of bytes written to this memory +system.physmem.bytes_written::total 9508160 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16022 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168249 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222526 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148565 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148565 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2097474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2774118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2097474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4626202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222526 # Total number of read requests seen +system.physmem.writeReqs 148565 # Total number of write requests seen +system.physmem.cpureqs 372829 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14241664 # Total number of bytes read from memory +system.physmem.bytesWritten 9508160 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14241664 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9508160 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1733 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14338 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13735 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 14393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 13573 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13175 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 13794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13620 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13949 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13975 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 14441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14348 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 14346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 13392 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9773 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 9207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 9622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 9014 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 9405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 9183 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8703 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 9240 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 9684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9527 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 9658 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8799 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 5125716897500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry +system.physmem.totGap 5133762656000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 222005 # Categorize read packet sizes +system.physmem.readPktSize::6 222526 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 148125 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 174153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 864 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148565 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 174531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 849 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see @@ -136,247 +136,244 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 754 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.447836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.150732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1279.689060 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 27741 44.45% 44.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 9677 15.51% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 5899 9.45% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 3942 6.32% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2509 4.02% 79.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 2016 3.23% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1522 2.44% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1230 1.97% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 938 1.50% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 940 1.51% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 553 0.89% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 567 0.91% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 409 0.66% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 381 0.61% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 350 0.56% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 427 0.68% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 299 0.48% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 221 0.35% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 165 0.26% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 170 0.27% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 190 0.30% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 458 0.73% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 188 0.30% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 102 0.16% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 75 0.12% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 65 0.10% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 60 0.10% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 37 0.06% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 23 0.04% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 21 0.03% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 32 0.05% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 22 0.04% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 13 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 21 0.03% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 12 0.02% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 13 0.02% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 12 0.02% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 9 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 7 0.01% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 4 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 9 0.01% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 9 0.01% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 9 0.01% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 2 0.00% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 3 0.00% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 13 0.02% 98.70% # Bytes accessed per row activation +system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 377.966975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.936826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1272.632195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 27908 44.44% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 9784 15.58% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5938 9.46% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3957 6.30% 75.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2545 4.05% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2018 3.21% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1524 2.43% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1187 1.89% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1022 1.63% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 897 1.43% 90.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 594 0.95% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 559 0.89% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 423 0.67% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 383 0.61% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 375 0.60% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 421 0.67% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 292 0.46% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 205 0.33% 95.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 163 0.26% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 146 0.23% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 144 0.23% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 476 0.76% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 183 0.29% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 124 0.20% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 88 0.14% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 60 0.10% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 51 0.08% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 42 0.07% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 29 0.05% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 32 0.05% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 30 0.05% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 17 0.03% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 11 0.02% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 16 0.03% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 10 0.02% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 13 0.02% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 7 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 8 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 3 0.00% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 6 0.01% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 6 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 8 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 4 0.01% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 8 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 4 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.00% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 3 0.00% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 8 0.01% 98.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 5 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 4 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.00% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 22 0.04% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 5 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.00% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 5 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 3 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 3 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 6 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 5 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 3 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 7 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 4 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 4 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 3 0.00% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 4 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 27 0.04% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 3 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 4 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 3 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 3 0.00% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 8 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 3 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 2 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 2 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 4 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 3 0.00% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 3 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 3 0.00% 98.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.00% 98.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 4 0.01% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 7 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 10 0.02% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 3 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12995 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 3 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 34 0.05% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 5 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 3 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 7 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 7 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 6 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 11 0.02% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 13 0.02% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 65 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62409 # Bytes accessed per row activation -system.physmem.totQLat 4001177249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8265005999 # Sum of mem lat for all requests -system.physmem.totBusLat 1109565000 # Total cycles spent in databus access -system.physmem.totBankLat 3154263750 # Total cycles spent in bank access -system.physmem.avgQLat 18030.39 # Average queueing delay per request -system.physmem.avgBankLat 14213.97 # Average bank access latency per request +system.physmem.bytesPerActivate::14464-14467 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 3 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 33 0.05% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 11 0.02% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 12 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 9 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 5 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 3 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 7 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 3 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 10 0.02% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 5 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 6 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 10 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 63 0.10% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18371 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62801 # Bytes accessed per row activation +system.physmem.totQLat 4020206249 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8301079999 # Sum of mem lat for all requests +system.physmem.totBusLat 1112255000 # Total cycles spent in databus access +system.physmem.totBankLat 3168618750 # Total cycles spent in bank access +system.physmem.avgQLat 18072.32 # Average queueing delay per request +system.physmem.avgBankLat 14244.12 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37244.35 # Average memory access latency +system.physmem.avgMemAccLat 37316.44 # Average memory access latency system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s @@ -384,99 +381,99 @@ system.physmem.avgConsumedWrBW 1.85 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.40 # Average write queue length over time -system.physmem.readRowHits 198637 # Number of row buffer hits during reads -system.physmem.writeRowHits 108987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads +system.physmem.avgWrQLen 13.16 # Average write queue length over time +system.physmem.readRowHits 198897 # Number of row buffer hits during reads +system.physmem.writeRowHits 109310 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes -system.physmem.avgGap 13848423.25 # Average gap between requests -system.membus.throughput 5098961 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662131 # Transaction distribution -system.membus.trans_dist::ReadResp 662131 # Transaction distribution -system.membus.trans_dist::WriteReq 13694 # Transaction distribution -system.membus.trans_dist::WriteResp 13694 # Transaction distribution -system.membus.trans_dist::Writeback 148125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1745 # Transaction distribution -system.membus.trans_dist::ReadExReq 179249 # Transaction distribution -system.membus.trans_dist::ReadExResp 179246 # Transaction distribution -system.membus.trans_dist::MessageReq 1640 # Transaction distribution -system.membus.trans_dist::MessageResp 1640 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473788 # Packet count per connected master and slave (bytes) +system.physmem.avgGap 13834241.89 # Average gap between requests +system.membus.throughput 5102506 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662304 # Transaction distribution +system.membus.trans_dist::ReadResp 662304 # Transaction distribution +system.membus.trans_dist::WriteReq 13698 # Transaction distribution +system.membus.trans_dist::WriteResp 13698 # Transaction distribution +system.membus.trans_dist::Writeback 148565 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2229 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1751 # Transaction distribution +system.membus.trans_dist::ReadExReq 179560 # Transaction distribution +system.membus.trans_dist::ReadExResp 179558 # Transaction distribution +system.membus.trans_dist::MessageReq 1642 # Transaction distribution +system.membus.trans_dist::MessageResp 1642 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719634 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 606242 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 607688 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1855368 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18259712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1856826 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20051511 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5428608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5428608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 23688320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20110919 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5430720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5430720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 23749824 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25486679 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25486679 # Total data (bytes) -system.membus.snoop_data_through_bus 649152 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1603689497 # Layer occupancy (ticks) +system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25548207 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25548207 # Total data (bytes) +system.membus.snoop_data_through_bus 646848 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1608355497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 250319000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 250293000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 583198000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 583289000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3280000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3284000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1640000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3152452403 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3156883661 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429424246 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429399995 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 47577 # number of replacements -system.iocache.tagsinuse 0.079131 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4992752531000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.079131 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.004946 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.004946 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses -system.iocache.ReadReq_misses::total 912 # number of ReadReq misses +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103958 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006497 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses -system.iocache.demand_misses::total 47632 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses -system.iocache.overall_misses::total 47632 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152414185 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152414185 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10346136346 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10346136346 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10498550531 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10498550531 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10498550531 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10498550531 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151796185 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151796185 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10322328602 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10322328602 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10474124787 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10474124787 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10474124787 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10474124787 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -485,40 +482,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167120.816886 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167120.816886 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221449.836173 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 221449.836173 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220409.609737 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220409.609737 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 148997 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166992.502750 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166992.502750 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 220940.252611 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 220940.252611 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 219910.659199 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 219910.659199 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 148616 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13662 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13635 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.905943 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.899597 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104973685 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104973685 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7915976600 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7915976600 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8020950285 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8020950285 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104494685 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104494685 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7891444112 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7891444112 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7995938797 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7995938797 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -527,14 +524,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115102.724781 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115102.724781 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169434.430651 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 169434.430651 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114955.649065 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114955.649065 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 168909.334589 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 168909.334589 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -548,13 +545,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 639145 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225496 # Transaction distribution -system.iobus.trans_dist::ReadResp 225496 # Transaction distribution +system.iobus.throughput 638140 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225493 # Transaction distribution +system.iobus.trans_dist::ReadResp 225493 # Transaction distribution system.iobus.trans_dist::WriteReq 57527 # Transaction distribution system.iobus.trans_dist::WriteResp 57527 # Transaction distribution -system.iobus.trans_dist::MessageReq 1640 # Transaction distribution -system.iobus.trans_dist::MessageResp 1640 # Transaction distribution +system.iobus.trans_dist::MessageReq 1642 # Transaction distribution +system.iobus.trans_dist::MessageResp 1642 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -574,11 +571,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3280 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -596,9 +593,9 @@ system.iobus.pkt_count::system.pc.fake_com_2.pio 12 system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569326 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569324 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -618,11 +615,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -640,11 +637,11 @@ system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276074 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3909656 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 3276058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276058 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3920600 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -680,154 +677,154 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424474531 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424430792 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52352000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53423005 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1640000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85601186 # Number of BP lookups -system.cpu.branchPred.condPredicted 85601186 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 878782 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79197718 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77534768 # Number of BTB hits +system.cpu.branchPred.lookups 85618831 # Number of BP lookups +system.cpu.branchPred.condPredicted 85618831 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 881906 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79126559 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77540225 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.900255 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440711 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 178764 # Number of incorrect RAS predictions. -system.cpu.numCycles 453375451 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.995194 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1441540 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180626 # Number of incorrect RAS predictions. +system.cpu.numCycles 453839632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25513858 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422800544 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85601186 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78975479 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162663365 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3996734 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 101966 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 70853615 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89309 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8479708 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 381834 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2341 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262338796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.182647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25514423 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422776164 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85618831 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78981765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162666633 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3997481 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 100403 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71304729 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 44393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94570 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 219 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8483452 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 380361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2201 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262796476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.177336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411374 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100089762 38.15% 38.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1543248 0.59% 38.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71824716 27.38% 66.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 898472 0.34% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1568808 0.60% 67.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2394853 0.91% 67.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1014354 0.39% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1328708 0.51% 68.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81675875 31.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100544783 38.26% 38.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1535684 0.58% 38.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71830288 27.33% 66.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 894888 0.34% 66.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1570094 0.60% 67.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2394528 0.91% 68.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1014297 0.39% 68.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1322217 0.50% 68.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81689697 31.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262338796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188809 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.932562 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29417456 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68001358 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158506679 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3339559 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3073744 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832592947 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 926 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3073744 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32109829 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42827309 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12461023 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158801746 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13065145 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829696742 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21430 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6044181 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5137835 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 10653 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 991365298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800497636 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1800497180 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963871300 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27493996 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 453983 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 458205 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29510312 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16729516 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9820056 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1138043 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 956999 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824928716 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1184630 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820966425 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 150849 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19304203 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29360127 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 130755 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262338796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.129413 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.399539 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262796476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188654 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931554 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29415381 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68460720 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158509709 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3339560 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3071106 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832655242 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 935 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3071106 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32114015 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43120028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12611794 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158799152 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13080381 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829727330 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21673 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6047730 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5146675 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 9377 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 991375726 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800594508 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1800594068 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 440 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963942859 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27432865 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 453030 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459006 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29568179 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16736842 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9827220 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1098890 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921986 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824947174 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1184809 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820992991 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 145624 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19292542 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29357019 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 130694 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262796476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.124064 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.400943 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75996420 28.97% 28.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15740261 6.00% 34.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10531012 4.01% 38.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7367834 2.81% 41.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75736075 28.87% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3750663 1.43% 72.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72297854 27.56% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 773517 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 145160 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76438982 29.09% 29.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15751400 5.99% 35.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10538627 4.01% 39.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7358771 2.80% 41.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75737390 28.82% 70.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3750331 1.43% 72.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72306613 27.51% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 767765 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 146597 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262338796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262796476 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 351269 33.33% 33.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 200 0.02% 33.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1810 0.17% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547247 51.93% 85.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153387 14.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 351017 33.38% 33.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 33.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 348 0.03% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547344 52.04% 85.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152992 14.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 304863 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793498796 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149830 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124227 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308184 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793508376 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149615 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124401 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -854,280 +851,280 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17669358 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9219351 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17677574 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9224841 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820966425 # Type of FU issued -system.cpu.iq.rate 1.810787 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1053913 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905583532 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845427964 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817056658 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821715388 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1694689 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820992991 # Type of FU issued +system.cpu.iq.rate 1.808994 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1051702 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001281 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906088677 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845434927 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817071068 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 189 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821736420 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 89 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694381 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2746767 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18051 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1403061 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2750139 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17720 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12102 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1408836 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931249 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12313 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931381 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3073744 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30976434 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2152665 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826113346 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242094 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16729516 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9820056 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 689859 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1619870 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14784 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 494405 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508019 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1002424 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819559028 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17368747 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1407396 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3071106 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31257120 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2152669 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826131983 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 242676 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16736842 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9827220 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 690491 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620064 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13028 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12102 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 497258 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506632 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1003890 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819577252 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17369785 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1415738 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26403485 # number of memory reference insts executed -system.cpu.iew.exec_branches 83095032 # Number of branches executed -system.cpu.iew.exec_stores 9034738 # Number of stores executed -system.cpu.iew.exec_rate 1.807683 # Inst execution rate -system.cpu.iew.wb_sent 819157526 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817056708 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638600685 # num instructions producing a value -system.cpu.iew.wb_consumers 1043925557 # num instructions consuming a value +system.cpu.iew.exec_refs 26409608 # number of memory reference insts executed +system.cpu.iew.exec_branches 83098710 # Number of branches executed +system.cpu.iew.exec_stores 9039823 # Number of stores executed +system.cpu.iew.exec_rate 1.805874 # Inst execution rate +system.cpu.iew.wb_sent 819172462 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817071124 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638600161 # num instructions producing a value +system.cpu.iew.wb_consumers 1043929120 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.802164 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800352 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 20041054 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1053875 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 888667 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259265052 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.108646 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863485 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19998846 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054115 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892238 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259725370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.103370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863932 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87759364 33.85% 33.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11842879 4.57% 38.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3826328 1.48% 39.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74742270 28.83% 68.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2381968 0.92% 69.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1473831 0.57% 70.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 858574 0.33% 70.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70846339 27.33% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5533499 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88203628 33.96% 33.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11848657 4.56% 38.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3832219 1.48% 40.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74739253 28.78% 68.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2381920 0.92% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1474779 0.57% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 859132 0.33% 70.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70849609 27.28% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5536173 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259265052 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407728401 # Number of instructions committed -system.cpu.commit.committedOps 805963181 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259725370 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407759186 # Number of instructions committed +system.cpu.commit.committedOps 806023868 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22399743 # Number of memory references committed -system.cpu.commit.loads 13982748 # Number of loads committed -system.cpu.commit.membars 474399 # Number of memory barriers committed -system.cpu.commit.branches 82153759 # Number of branches committed +system.cpu.commit.refs 22405086 # Number of memory references committed +system.cpu.commit.loads 13986702 # Number of loads committed +system.cpu.commit.membars 474409 # Number of memory barriers committed +system.cpu.commit.branches 82159690 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734952654 # Number of committed integer instructions. -system.cpu.commit.function_calls 1154691 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5533499 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 735008844 # Number of committed integer instructions. +system.cpu.commit.function_calls 1154896 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5536173 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079657633 # The number of ROB reads -system.cpu.rob.rob_writes 1655096826 # The number of ROB writes -system.cpu.timesIdled 1258785 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 191036655 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9798064041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407728401 # Number of Instructions Simulated -system.cpu.committedOps 805963181 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407728401 # Number of Instructions Simulated -system.cpu.cpi 1.111955 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.111955 # CPI: Total CPI of All Threads -system.cpu.ipc 0.899317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.899317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1504349061 # number of integer regfile reads -system.cpu.int_regfile_writes 975319683 # number of integer regfile writes -system.cpu.fp_regfile_reads 50 # number of floating regfile reads -system.cpu.misc_regfile_reads 264080509 # number of misc regfile reads -system.cpu.misc_regfile_writes 401987 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53625221 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3010668 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3010129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1578360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334262 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287551 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1907708 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6121795 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 17377 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 150658 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 8197538 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61043136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207549047 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 553408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5256448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 274402039 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274377591 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 490112 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4031070918 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1080133651 # The number of ROB reads +system.cpu.rob.rob_writes 1655131261 # The number of ROB writes +system.cpu.timesIdled 1259877 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 191043156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9813691352 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407759186 # Number of Instructions Simulated +system.cpu.committedOps 806023868 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407759186 # Number of Instructions Simulated +system.cpu.cpi 1.113009 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.113009 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898465 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898465 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1504423855 # number of integer regfile reads +system.cpu.int_regfile_writes 975340027 # number of integer regfile writes +system.cpu.fp_regfile_reads 56 # number of floating regfile reads +system.cpu.misc_regfile_reads 264091330 # number of misc regfile reads +system.cpu.misc_regfile_writes 402284 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53596956 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3010019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3009469 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1583020 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288025 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1906694 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6122854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 16266 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 154977 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 8200791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61010496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207591623 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 510912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5512832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 274625863 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274602311 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 551744 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4037956918 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 552000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1431698822 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1434043234 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3102593965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3142652791 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 13102485 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 12430241 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 102839393 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 103328135 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 953322 # number of replacements -system.cpu.icache.tagsinuse 510.127378 # Cycle average of tags in use -system.cpu.icache.total_refs 7473092 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 953834 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.834793 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 147390294000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.127378 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996343 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996343 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7473092 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7473092 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7473092 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7473092 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7473092 # number of overall hits -system.cpu.icache.overall_hits::total 7473092 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1006614 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1006614 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1006614 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1006614 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1006614 # number of overall misses -system.cpu.icache.overall_misses::total 1006614 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14222924496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14222924496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14222924496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14222924496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14222924496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14222924496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8479706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8479706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8479706 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8479706 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8479706 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8479706 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118709 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118709 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118709 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118709 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118709 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118709 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14129.472167 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14129.472167 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14129.472167 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14129.472167 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8172 # number of cycles access was blocked +system.cpu.icache.tags.replacements 952820 # number of replacements +system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7477461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7477461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7477461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7477461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7477461 # number of overall hits +system.cpu.icache.overall_hits::total 7477461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005989 # number of overall misses +system.cpu.icache.overall_misses::total 1005989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232079935 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14232079935 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14232079935 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14232079935 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14232079935 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14232079935 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8483450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8483450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8483450 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8483450 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8483450 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8483450 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118583 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118583 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118583 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.118583 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.118583 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.118583 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14147.351447 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14147.351447 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14147.351447 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14147.351447 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 174 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.238095 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35.580460 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52705 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52705 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52705 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52705 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52705 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52705 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953909 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 953909 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 953909 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 953909 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 953909 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 953909 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11745970674 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11745970674 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11745970674 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11745970674 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11745970674 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11745970674 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112493 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112493 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112493 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12313.512792 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12313.512792 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52584 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 52584 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 52584 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 52584 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 52584 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 52584 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953405 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 953405 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 953405 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 953405 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 953405 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 953405 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11737352011 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11737352011 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11737352011 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11737352011 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11737352011 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11737352011 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112384 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112384 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112384 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12310.982228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12310.982228 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 7857 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.317656 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 21864 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 7868 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.778851 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5104284128000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.317656 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.394853 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.394853 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21875 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 21875 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 7402 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 7416 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5104253177000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006857 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375429 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.375429 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21911 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21911 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21877 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 21877 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21877 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 21877 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8730 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 8730 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8730 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 8730 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8730 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 8730 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 99800500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 99800500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 99800500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 99800500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 99800500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 99800500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30605 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30605 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21913 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21913 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21913 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21913 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8283 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8283 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8283 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8283 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8283 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8283 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 92582993 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 92582993 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 92582993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 92582993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 92582993 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 92582993 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30194 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30194 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30607 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30607 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30607 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30607 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285248 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285248 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285229 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.285229 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285229 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.285229 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11431.901489 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11431.901489 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11431.901489 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11431.901489 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30196 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30196 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30196 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30196 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.274326 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.274326 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.274308 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.274308 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.274308 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.274308 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11177.471085 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11177.471085 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11177.471085 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1136,78 +1133,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1569 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1569 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8730 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8730 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8730 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 8730 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8730 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 8730 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 82333015 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 82333015 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 82333015 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 82333015 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 82333015 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 82333015 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285248 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285248 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9431.044101 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1499 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1499 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8283 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8283 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8283 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8283 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8283 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8283 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 76005511 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 76005511 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 76005511 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 76005511 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 76005511 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 76005511 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.274326 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.274326 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.274308 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.274308 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.274308 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.274308 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9176.084873 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 67431 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 14.830291 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 90986 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 67447 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.349000 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 4994048518000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.830291 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.926893 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.926893 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90986 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 90986 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90986 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 90986 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90986 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 90986 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68526 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 68526 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68526 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 68526 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68526 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 68526 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854232500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854232500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854232500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 854232500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854232500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 854232500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 159512 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 159512 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 159512 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 159512 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 159512 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 159512 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429598 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429598 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429598 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429598 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429598 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429598 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.815895 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.815895 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.815895 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.815895 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 67804 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 67819 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101460528500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.886481 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.867905 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.867905 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92498 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92498 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92498 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92498 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92498 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92498 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68839 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 68839 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68839 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 68839 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68839 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 68839 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 851625712 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 851625712 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 851625712 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 851625712 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 851625712 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 851625712 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161337 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 161337 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161337 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 161337 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161337 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 161337 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426678 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426678 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426678 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426678 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426678 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426678 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12371.267915 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12371.267915 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12371.267915 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1216,146 +1213,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 18479 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 18479 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68526 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68526 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68526 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 68526 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68526 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 68526 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 717130107 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 717130107 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 717130107 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 717130107 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 717130107 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 717130107 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429598 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429598 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429598 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.080510 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 23017 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 23017 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68839 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68839 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68839 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 68839 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68839 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 68839 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 713808442 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 713808442 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 713808442 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 713808442 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 713808442 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 713808442 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426678 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426678 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426678 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10369.244789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1656381 # number of replacements -system.cpu.dcache.tagsinuse 511.996762 # Cycle average of tags in use -system.cpu.dcache.total_refs 18981789 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1656893 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.456255 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 37864000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.996762 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10887156 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10887156 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8091896 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8091896 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18979052 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18979052 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18979052 # number of overall hits -system.cpu.dcache.overall_hits::total 18979052 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2237799 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2237799 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315625 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315625 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2553424 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2553424 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2553424 # number of overall misses -system.cpu.dcache.overall_misses::total 2553424 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33108471000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33108471000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12021128996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12021128996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45129599996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45129599996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45129599996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45129599996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13124955 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13124955 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8407521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8407521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21532476 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21532476 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21532476 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21532476 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170500 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170500 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037541 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037541 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118585 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118585 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118585 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118585 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14795.104922 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14795.104922 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38086.745334 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38086.745334 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17674.150472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17674.150472 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 405217 # number of cycles access was blocked +system.cpu.dcache.tags.replacements 1656828 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10890330 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10890330 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8092849 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8092849 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18983179 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18983179 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18983179 # number of overall hits +system.cpu.dcache.overall_hits::total 18983179 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2236067 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2236067 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316060 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316060 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2552127 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2552127 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2552127 # number of overall misses +system.cpu.dcache.overall_misses::total 2552127 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33180539725 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33180539725 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12164482246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12164482246 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45345021971 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45345021971 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45345021971 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45345021971 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13126397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13126397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8408909 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8408909 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21535306 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21535306 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21535306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21535306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170349 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037586 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037586 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118509 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118509 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118509 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118509 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.794958 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.794958 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38487.889154 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38487.889154 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17767.541337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17767.541337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17767.541337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17767.541337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 401774 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42719 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42434 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.485639 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.468209 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558312 # number of writebacks -system.cpu.dcache.writebacks::total 1558312 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868331 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 868331 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25900 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25900 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 894231 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 894231 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 894231 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 894231 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289725 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289725 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1659193 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1659193 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1659193 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1659193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17883109030 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17883109030 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11189452001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11189452001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29072561031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29072561031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29072561031 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29072561031 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349104500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349104500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2521383000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2521383000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99870487500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99870487500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104341 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104341 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034460 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034460 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077055 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077055 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13058.435122 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13058.435122 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38620.940551 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38620.940551 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1558504 # number of writebacks +system.cpu.dcache.writebacks::total 1558504 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866614 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 866614 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25901 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25901 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 892515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 892515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 892515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 892515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369453 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1369453 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290159 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290159 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1659612 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1659612 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1659612 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1659612 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17930492982 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17930492982 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11266233199 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11266233199 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29196726181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29196726181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29196726181 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29196726181 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349090500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349090500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2521949000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2521949000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99871039500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99871039500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104328 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104328 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077065 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077065 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077065 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077065 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13093.178796 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13093.178796 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38827.791656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38827.791656 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17592.501248 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17592.501248 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17592.501248 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17592.501248 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1363,141 +1360,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 110887 # number of replacements -system.cpu.l2cache.tagsinuse 64831.056251 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3780740 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 175156 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.584987 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50733.546083 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 16.870188 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.435873 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3102.105896 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10978.098210 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.774132 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000257 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.047334 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.167512 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989243 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63592 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7072 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 937746 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1332853 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2341263 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1578360 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1578360 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154746 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154746 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 63592 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 7072 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 937746 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1487599 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2496009 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 63592 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 7072 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 937746 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1487599 # number of overall hits -system.cpu.l2cache.overall_hits::total 2496009 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 51995 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1482 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1482 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132789 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132789 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16053 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 168664 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 184784 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16053 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 168664 # number of overall misses -system.cpu.l2cache.overall_misses::total 184784 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6023000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 505500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1392940500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2991754000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4391223000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17604000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17604000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9307246499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9307246499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6023000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 505500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1392940500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12299000499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13698469499 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6023000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 505500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1392940500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12299000499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13698469499 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63653 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7078 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 953799 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1368728 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2393258 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1578360 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1578360 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1799 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1799 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287535 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287535 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63653 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 7078 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 953799 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1656263 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2680793 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63653 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 7078 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 953799 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1656263 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2680793 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000848 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016831 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823791 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823791 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461819 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461819 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000958 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000848 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016831 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.101834 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.068929 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000958 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000848 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016831 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.101834 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.068929 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 98737.704918 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86771.351149 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83393.839721 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84454.716800 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11878.542510 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11878.542510 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70090.493181 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70090.493181 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 98737.704918 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86771.351149 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72920.128178 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74132.335586 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 98737.704918 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86771.351149 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72920.128178 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74132.335586 # average overall miss latency +system.cpu.l2cache.tags.replacements 111287 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64824.187334 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3785036 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175649 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.548862 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 50594.922506 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.467907 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125935 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3127.998862 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11091.672124 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.772017 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000144 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.169245 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989139 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63059 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6479 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 937263 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1332664 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2339465 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1583020 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1583020 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 302 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 154882 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154882 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 63059 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 6479 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 937263 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1487546 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2494347 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 63059 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 6479 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 937263 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1487546 # number of overall hits +system.cpu.l2cache.overall_hits::total 2494347 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 62 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16026 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 36078 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 52171 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1463 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1463 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133126 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133126 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16026 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169204 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185297 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16026 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169204 # number of overall misses +system.cpu.l2cache.overall_misses::total 185297 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6809750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 417750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1389559236 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3040297215 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4437083951 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17341812 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 17341812 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9382369904 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9382369904 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6809750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 417750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1389559236 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12422667119 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13819453855 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6809750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 417750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1389559236 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12422667119 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13819453855 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63121 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 6484 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 953289 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1368742 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2391636 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1583020 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1583020 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1765 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1765 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 288008 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 288008 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63121 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 6484 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 953289 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1656750 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2679644 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63121 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 6484 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 953289 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1656750 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2679644 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000771 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016811 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026359 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021814 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.828895 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.828895 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.462230 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.462230 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000771 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016811 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102130 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.069150 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000771 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016811 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102130 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.069150 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 109834.677419 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83550 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86706.554100 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84270.115167 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 85048.857622 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11853.596719 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11853.596719 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70477.366585 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70477.366585 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 109834.677419 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86706.554100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73418.282777 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74580.019401 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 109834.677419 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86706.554100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73418.282777 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74580.019401 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1506,99 +1503,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101458 # number of writebacks -system.cpu.l2cache.writebacks::total 101458 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks +system.cpu.l2cache.writebacks::total 101898 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16050 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35873 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 51990 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1482 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1482 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132789 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 132789 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16050 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 168662 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 184779 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16050 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 168662 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 184779 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5260750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 430000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1193323263 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545977303 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3744991316 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15894959 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15894959 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7671814321 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7671814321 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5260750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1193323263 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10217791624 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11416805637 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5260750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 430000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1193323263 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10217791624 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11416805637 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236814500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236814500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2356578000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2356578000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91593392500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91593392500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026209 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823791 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823791 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461819 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461819 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068927 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.068927 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74350.359065 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70971.965071 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72032.916253 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10725.343455 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10725.343455 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57774.471688 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57774.471688 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 62 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16022 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36077 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 52166 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1463 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1463 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133126 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133126 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 62 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16022 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169203 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185292 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 62 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16022 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169203 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185292 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6018750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 353750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1186972764 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2585018535 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3778363799 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15641444 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15641444 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7710305096 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7710305096 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6018750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 353750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1186972764 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10295323631 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11488668895 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6018750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 353750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1186972764 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10295323631 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11488668895 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236799000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236799000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2357013000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2357013000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91593812000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91593812000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000771 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016807 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026358 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.828895 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.828895 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.462230 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.462230 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000771 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016807 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102129 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069148 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000771 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016807 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102129 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.069148 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74083.932343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71652.813011 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72429.624641 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.349282 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.349282 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57917.349699 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57917.349699 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74083.932343 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60845.987548 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62003.048675 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74083.932343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60845.987548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62003.048675 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 0632af65b..551b52f89 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,150 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.143601 # Number of seconds simulated -sim_ticks 5143601047500 # Number of ticks simulated -final_tick 5143601047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.139589 # Number of seconds simulated +sim_ticks 5139589353000 # Number of ticks simulated +final_tick 5139589353000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 255414 # Simulator instruction rate (inst/s) -host_op_rate 507504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5398723492 # Simulator tick rate (ticks/s) -host_mem_usage 908456 # Number of bytes of host memory used -host_seconds 952.74 # Real time elapsed on the host -sim_insts 243343656 # Number of instructions simulated -sim_ops 483521256 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2435392 # Number of bytes read from this memory +host_inst_rate 286755 # Simulator instruction rate (inst/s) +host_op_rate 569759 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6048900638 # Simulator tick rate (ticks/s) +host_mem_usage 936564 # Number of bytes of host memory used +host_seconds 849.67 # Real time elapsed on the host +sim_insts 243647713 # Number of instructions simulated +sim_ops 484108731 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2450688 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6105280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 134592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1637632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 319296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2611264 # Number of bytes read from this memory -system.physmem.bytes_read::total 13733504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 134592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 319296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 942336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9060160 # Number of bytes written to this memory -system.physmem.bytes_written::total 9060160 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38053 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 424832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5722240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 151040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1810944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 372032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2837824 # Number of bytes read from this memory +system.physmem.bytes_read::total 13771904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 424832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 372032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 947904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9105344 # Number of bytes written to this memory +system.physmem.bytes_written::total 9105344 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38292 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 95395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2103 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 25588 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 40801 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214586 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141565 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141565 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 473480 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6638 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 89410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 28296 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 30 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5813 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 44341 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215186 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142271 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142271 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476826 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 94962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1186966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 318382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 62076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 507672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2670017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 94962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 62076 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 183205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1761443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1761443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1761443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 473480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1113365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 352352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 72386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 552150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2679573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82659 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29388 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 72386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 184432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1771609 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1771609 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1771609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476826 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 94962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1186966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 318382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 62076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 507672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4431460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 90446 # Total number of read requests seen -system.physmem.writeReqs 70433 # Total number of write requests seen -system.physmem.cpureqs 161351 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 5788544 # Total number of bytes read from memory -system.physmem.bytesWritten 4507712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 5788544 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4507712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 472 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 5853 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 5374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 5163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 5410 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 5951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6069 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 4925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 4669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 5184 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 5694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 5914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 5934 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4493 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4309 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4025 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4752 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4893 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3464 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 3572 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4337 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4609 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4582 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4499 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 82659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1113365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 352352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 72386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 552150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4451182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 96603 # Total number of read requests seen +system.physmem.writeReqs 74912 # Total number of write requests seen +system.physmem.cpureqs 172248 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6182592 # Total number of bytes read from memory +system.physmem.bytesWritten 4794368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6182592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 4794368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 732 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 5743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 5750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 5839 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6289 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 5688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 5956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 5856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 5878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6204 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 5996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6119 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4526 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4556 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4674 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4937 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4457 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4557 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4265 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4556 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5050 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4641 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4582 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4382 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 5140092000000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136024228000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 90446 # Categorize read packet sizes +system.physmem.readPktSize::6 96603 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 70433 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 74912 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 77105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,522 +160,533 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 30233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.294645 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.805560 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1124.042449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13536 44.77% 44.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 4627 15.30% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 2854 9.44% 69.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 1864 6.17% 75.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1230 4.07% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1007 3.33% 83.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 772 2.55% 85.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 598 1.98% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 458 1.51% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 438 1.45% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 281 0.93% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 279 0.92% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 209 0.69% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 207 0.68% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 177 0.59% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 236 0.78% 95.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 132 0.44% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 98 0.32% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 103 0.34% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 81 0.27% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 87 0.29% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 80 0.26% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 236 0.78% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 88 0.29% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 47 0.16% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 40 0.13% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 31 0.10% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 30 0.10% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 19 0.06% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 8 0.03% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 13 0.04% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 8 0.03% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 4 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 5 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.03% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 4 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 4 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 2 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 4 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 5 0.02% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 2 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 5 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 12 0.04% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 3 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 4 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 2 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 29 0.10% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 3 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 2 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 2 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 15 0.05% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 11 0.04% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 6 0.02% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 3 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 33252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.902562 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.864384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1038.972369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14693 44.19% 44.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5121 15.40% 59.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3144 9.46% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2114 6.36% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1414 4.25% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1109 3.34% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 834 2.51% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 672 2.02% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 527 1.58% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 500 1.50% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 311 0.94% 91.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 308 0.93% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 231 0.69% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 204 0.61% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 157 0.47% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 279 0.84% 95.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 147 0.44% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 117 0.35% 95.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 74 0.22% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 80 0.24% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 100 0.30% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 111 0.33% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 291 0.88% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 116 0.35% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 63 0.19% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 43 0.13% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 35 0.11% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 34 0.10% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 18 0.05% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 13 0.04% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 14 0.04% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 17 0.05% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 9 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 4 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 7 0.02% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 10 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 7 0.02% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.02% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 8 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 9 0.03% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 6 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 2 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 2 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 6 0.02% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 5 0.02% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 2 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 3 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 3 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 5 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 5 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 4 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 2 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 3 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 29 0.09% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 2 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 2 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 2 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 2 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 2 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 11 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 4 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 2 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 2 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 5 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 2 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 5 0.02% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 2 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 3 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 21 0.07% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 30233 # Bytes accessed per row activation -system.physmem.totQLat 1718746250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3502520000 # Sum of mem lat for all requests -system.physmem.totBusLat 452100000 # Total cycles spent in databus access -system.physmem.totBankLat 1331673750 # Total cycles spent in bank access -system.physmem.avgQLat 19008.47 # Average queueing delay per request -system.physmem.avgBankLat 14727.65 # Average bank access latency per request +system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 2 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 5 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 2 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 5 0.02% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 2 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 27 0.08% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 33252 # Bytes accessed per row activation +system.physmem.totQLat 1788062000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3723402000 # Sum of mem lat for all requests +system.physmem.totBusLat 482955000 # Total cycles spent in databus access +system.physmem.totBankLat 1452385000 # Total cycles spent in bank access +system.physmem.avgQLat 18511.68 # Average queueing delay per request +system.physmem.avgBankLat 15036.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38736.12 # Average memory access latency -system.physmem.avgRdBW 1.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.88 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.88 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38548.13 # Average memory access latency +system.physmem.avgRdBW 1.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.93 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.11 # Average write queue length over time -system.physmem.readRowHits 78857 # Number of row buffer hits during reads -system.physmem.writeRowHits 51763 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.49 # Row buffer hit rate for writes -system.physmem.avgGap 31950049.42 # Average gap between requests -system.membus.throughput 6398386 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 425816 # Transaction distribution -system.membus.trans_dist::ReadResp 425816 # Transaction distribution -system.membus.trans_dist::WriteReq 5631 # Transaction distribution -system.membus.trans_dist::WriteResp 5631 # Transaction distribution -system.membus.trans_dist::Writeback 70433 # Transaction distribution -system.membus.trans_dist::UpgradeReq 476 # Transaction distribution -system.membus.trans_dist::UpgradeResp 476 # Transaction distribution -system.membus.trans_dist::ReadExReq 69519 # Transaction distribution -system.membus.trans_dist::ReadExResp 69519 # Transaction distribution -system.membus.trans_dist::MessageReq 269 # Transaction distribution -system.membus.trans_dist::MessageResp 269 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 197349 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1007895 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 60171 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 60171 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 257520 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 312424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1068604 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 1076 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7851072 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9006954 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2445184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2445184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 10296256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 11453214 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32574935 # Total data (bytes) -system.membus.snoop_data_through_bus 335808 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 770602000 # Layer occupancy (ticks) +system.physmem.readRowHits 84146 # Number of row buffer hits during reads +system.physmem.writeRowHits 54105 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.22 # Row buffer hit rate for writes +system.physmem.avgGap 29945044.04 # Average gap between requests +system.membus.throughput 6414834 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 427545 # Transaction distribution +system.membus.trans_dist::ReadResp 427545 # Transaction distribution +system.membus.trans_dist::WriteReq 5661 # Transaction distribution +system.membus.trans_dist::WriteResp 5661 # Transaction distribution +system.membus.trans_dist::Writeback 74912 # Transaction distribution +system.membus.trans_dist::UpgradeReq 735 # Transaction distribution +system.membus.trans_dist::UpgradeResp 735 # Transaction distribution +system.membus.trans_dist::ReadExReq 72970 # Transaction distribution +system.membus.trans_dist::ReadExResp 72970 # Transaction distribution +system.membus.trans_dist::MessageReq 216 # Transaction distribution +system.membus.trans_dist::MessageResp 216 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 219090 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1030222 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 54502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 54502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 273592 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 312952 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu0.interrupts.pio 498180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu0.interrupts.int_slave 432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1085156 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8733312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9889556 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2243648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2243648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 10976960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 159887 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996357 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12134068 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32713165 # Total data (bytes) +system.membus.snoop_data_through_bus 256448 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 793885999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 164025500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 164366000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 314786000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 314753000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 538000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 432000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 269000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 216000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1575668988 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1632166487 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 198012000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 175306750 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.replacements 103562 # number of replacements -system.l2c.tagsinuse 64796.800964 # Cycle average of tags in use -system.l2c.total_refs 3619781 # Total number of references to valid blocks. -system.l2c.sampled_refs 167743 # Sample count of references to valid blocks. -system.l2c.avg_refs 21.579327 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 51276.359665 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.126176 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 1273.083994 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4560.482374 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 265.925814 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 1312.167499 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 5.741812 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1370.746219 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 4732.167410 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.782415 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.019426 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.069587 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.004058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.020022 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000088 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.020916 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.072207 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.988721 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 380736 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 540863 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5306 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 154822 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 225347 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 39624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 7543 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 294341 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 531967 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2216094 # number of ReadReq hits +system.l2c.tags.replacements 104154 # number of replacements +system.l2c.tags.tagsinuse 64818.882502 # Cycle average of tags in use +system.l2c.tags.total_refs 3632248 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168346 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.576087 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 51171.986670 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125486 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1262.785068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4574.642727 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 231.301246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1356.639626 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.163681 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.039070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1464.364249 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4745.834679 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.780823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.019269 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.069804 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.020701 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.022344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.072416 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989058 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 20178 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11162 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 357762 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 528228 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4903 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 153273 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 226490 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 46782 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 8793 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 321700 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 546165 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2227865 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1541993 # number of Writeback hits -system.l2c.Writeback_hits::total 1541993 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 185 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 34 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 34 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 253 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 81134 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 39930 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 50435 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171499 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11249 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 380736 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 621997 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5306 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2771 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 154822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 265277 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 39624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 7543 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 294341 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 582402 # number of demand (read+write) hits -system.l2c.demand_hits::total 2387595 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21527 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11249 # number of overall hits -system.l2c.overall_hits::cpu0.inst 380736 # number of overall hits -system.l2c.overall_hits::cpu0.data 621997 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5306 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2771 # number of overall hits -system.l2c.overall_hits::cpu1.inst 154822 # number of overall hits -system.l2c.overall_hits::cpu1.data 265277 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 39624 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 7543 # number of overall hits -system.l2c.overall_hits::cpu2.inst 294341 # number of overall hits -system.l2c.overall_hits::cpu2.data 582402 # number of overall hits -system.l2c.overall_hits::total 2387595 # number of overall hits +system.l2c.Writeback_hits::writebacks 1544497 # number of Writeback hits +system.l2c.Writeback_hits::total 1544497 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 143 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 76 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 255 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 71037 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 43117 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 57018 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 171172 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 20178 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 11164 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 357762 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 599265 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4903 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 153273 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 269607 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 46782 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 8793 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 321700 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 603183 # number of demand (read+write) hits +system.l2c.demand_hits::total 2399039 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 20178 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 11164 # number of overall hits +system.l2c.overall_hits::cpu0.inst 357762 # number of overall hits +system.l2c.overall_hits::cpu0.data 599265 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4903 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits +system.l2c.overall_hits::cpu1.inst 153273 # number of overall hits +system.l2c.overall_hits::cpu1.data 269607 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 46782 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 8793 # number of overall hits +system.l2c.overall_hits::cpu2.inst 321700 # number of overall hits +system.l2c.overall_hits::cpu2.data 603183 # number of overall hits +system.l2c.overall_hits::total 2399039 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7632 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 14556 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2103 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4151 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 20 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4990 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 14210 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47667 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 996 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 152 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 164 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1312 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 81386 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21703 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 26712 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 129801 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 6638 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 13571 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2360 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4761 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 5815 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 14526 # number of ReadReq misses +system.l2c.ReadReq_misses::total 47708 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 712 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 243 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 390 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1345 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 76337 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 23772 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 30004 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130113 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7632 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 95942 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2103 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 25854 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4990 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 40922 # number of demand (read+write) misses -system.l2c.demand_misses::total 177468 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6638 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 89908 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2360 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 28533 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 31 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 5815 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 44530 # number of demand (read+write) misses +system.l2c.demand_misses::total 177821 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7632 # number of overall misses -system.l2c.overall_misses::cpu0.data 95942 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2103 # number of overall misses -system.l2c.overall_misses::cpu1.data 25854 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4990 # number of overall misses -system.l2c.overall_misses::cpu2.data 40922 # number of overall misses -system.l2c.overall_misses::total 177468 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 168360000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 318876500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 1858500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 450433500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1172801993 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2112330493 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1963500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 2169000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 4132500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1523449000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1983970000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 3507419000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 168360000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1842325500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 1858500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 450433500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3156771993 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 5619749493 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 168360000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1842325500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 1858500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 450433500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3156771993 # number of overall miss cycles -system.l2c.overall_miss_latency::total 5619749493 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 21527 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 11252 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 388368 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 555419 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5306 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2771 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 156925 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 229498 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 39644 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 7543 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 299331 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 546177 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2263761 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 6638 # number of overall misses +system.l2c.overall_misses::cpu0.data 89908 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2360 # number of overall misses +system.l2c.overall_misses::cpu1.data 28533 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 31 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 5815 # number of overall misses +system.l2c.overall_misses::cpu2.data 44530 # number of overall misses +system.l2c.overall_misses::total 177821 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 185186500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 369106743 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3097499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 524253495 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1205998231 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2287731218 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2444401 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 4607806 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 7052207 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1673798209 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2232599179 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3906397388 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 185186500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2042904952 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 3097499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 524253495 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3438597410 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6194128606 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 185186500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2042904952 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 3097499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 524253495 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3438597410 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6194128606 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 20178 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 11167 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 364400 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 541799 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4903 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 155633 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 231251 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 46813 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 8794 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 327515 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 560691 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2275573 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1541993 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1541993 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1181 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 186 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 198 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1565 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 162520 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 61633 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 77147 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 301300 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 21527 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 11254 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 388368 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 717939 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5306 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2771 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 156925 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 291131 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 39644 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 7543 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 299331 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 623324 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2565063 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 21527 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 11254 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 388368 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 717939 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5306 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2771 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 156925 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 291131 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 39644 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 7543 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 299331 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 623324 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2565063 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000444 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.019651 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.026207 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.013401 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.018087 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000504 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.016671 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.026017 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.021057 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.843353 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.817204 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.828283 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.838339 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.500775 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.352133 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.346248 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.430803 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000444 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019651 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.133635 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.013401 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.088805 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000504 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.016671 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.065651 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.069187 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000444 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019651 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.133635 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.013401 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.088805 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000504 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.016671 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.065651 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.069187 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80057.061341 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76819.200193 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 92925 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 90267.234469 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 82533.567417 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 44314.315837 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12917.763158 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 13225.609756 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3149.771341 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70195.318620 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74272.611560 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 27021.509850 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80057.061341 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71258.818751 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 92925 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 90267.234469 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 77141.195274 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 31666.269373 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80057.061341 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71258.818751 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 92925 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 90267.234469 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 77141.195274 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 31666.269373 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1544497 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1544497 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 855 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 279 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 466 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1600 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 147374 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 66889 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 87022 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 301285 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 20178 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 11169 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 364400 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 689173 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4903 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 155633 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 298140 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 46813 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 8794 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 327515 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 647713 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2576860 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 20178 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 11169 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 364400 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 689173 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4903 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 155633 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 298140 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 46813 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 8794 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 327515 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 647713 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2576860 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000448 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018216 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.025048 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.015164 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020588 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000662 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000114 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.017755 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.025907 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020965 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.832749 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870968 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.836910 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.840625 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.517981 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.355395 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.344786 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.431860 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000448 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018216 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.130458 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.015164 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.095703 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000662 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000114 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.017755 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.068750 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.069007 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000448 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018216 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.130458 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.015164 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.095703 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000662 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000114 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.017755 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.068750 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.069007 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78468.855932 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77527.146188 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 99919.322581 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 90155.373173 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 83023.422208 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 47952.779785 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10059.263374 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11814.887179 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5243.276580 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70410.491713 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74410.051293 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 30023.113663 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 78468.855932 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71597.972593 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 99919.322581 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 90155.373173 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 77219.793622 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 34833.504513 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 78468.855932 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71597.972593 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 99919.322581 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 90155.373173 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 77219.793622 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 34833.504513 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,119 +695,134 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 94898 # number of writebacks -system.l2c.writebacks::total 94898 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.inst 2103 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4151 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 20 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4989 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 14210 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25473 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 152 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 164 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 316 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 21703 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 26712 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 48415 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2103 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 25854 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4989 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 40922 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 73888 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2103 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 25854 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4989 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 40922 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 73888 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 141927001 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 266998007 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1609750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 388375752 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 995867746 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1794778256 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1620150 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 1740662 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3360812 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1250022394 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1647192543 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2897214937 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 141927001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1517020401 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1609750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 388375752 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2643060289 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4691993193 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 141927001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1517020401 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1609750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 388375752 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2643060289 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4691993193 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28533740000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30392173500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58925913500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 434854000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 626965000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1061819000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28968594000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31019138500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59987732500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.013401 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018087 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.016667 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.026017 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.011253 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817204 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.828283 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.201917 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.352133 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.346248 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.160687 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.013401 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.088805 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000504 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.016667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.065651 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.028806 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.013401 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.088805 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000504 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.016667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.065651 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.028806 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67487.874941 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64321.370031 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 80487.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77846.412508 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70082.177762 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 70458.063675 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10658.881579 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10613.792683 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10635.481013 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57596.755932 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61664.890049 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 59841.266901 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67487.874941 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58676.429218 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 80487.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77846.412508 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64587.759371 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63501.423682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67487.874941 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58676.429218 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 80487.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77846.412508 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64587.759371 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63501.423682 # average overall mshr miss latency +system.l2c.writebacks::writebacks 95604 # number of writebacks +system.l2c.writebacks::total 95604 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.dtb.walker 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.dtb.walker 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.inst 2360 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4761 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 30 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 5813 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 14526 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 27491 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 243 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 390 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 633 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 23772 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 30004 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 53776 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2360 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 28533 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 30 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5813 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 44530 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 81267 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2360 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 28533 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 30 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5813 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 44530 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 81267 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 155365000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 308892757 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2656751 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 450701255 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1022394749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1940086762 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2530241 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3952388 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 6482629 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1375043791 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1855159821 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3230203612 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 155365000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1683936548 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2656751 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 450701255 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2877554570 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5170290374 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 155365000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1683936548 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2656751 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 450701255 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2877554570 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5170290374 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28552490000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30418768500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58971258500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 380243500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 689742500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1069986000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28932733500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31108511000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60041244500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015164 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020588 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000641 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000114 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017749 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.025907 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.012081 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870968 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.836910 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.395625 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.355395 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344786 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.178489 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.095703 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000114 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017749 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.068750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.031537 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.095703 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000114 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017749 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.068750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.031537 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65832.627119 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64879.806133 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 88558.366667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77533.331326 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70383.777296 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 70571.705722 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10412.514403 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10134.328205 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10241.120063 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57842.999790 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61830.416644 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60067.755356 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65832.627119 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59017.157257 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 88558.366667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77533.331326 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64620.583202 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63621.031587 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65832.627119 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59017.157257 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 88558.366667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77533.331326 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64620.583202 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63621.031587 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -803,39 +833,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47575 # number of replacements -system.iocache.tagsinuse 0.112740 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47591 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4999844175559 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.112740 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007046 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007046 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.replacements 47579 # number of replacements +system.iocache.tags.tagsinuse 0.100447 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4999807573509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.100447 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006278 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006278 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses +system.iocache.ReadReq_misses::total 914 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132357305 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 132357305 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 4636265535 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4636265535 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 4768622840 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4768622840 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 4768622840 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4768622840 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47634 # number of demand (read+write) misses +system.iocache.demand_misses::total 47634 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47634 # number of overall misses +system.iocache.overall_misses::total 47634 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 16928907 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 16928907 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 4287176010 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4287176010 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 4304104917 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4304104917 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 4304104917 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4304104917 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47634 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47634 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47634 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47634 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -844,60 +874,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145447.587912 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145447.587912 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 99235.135595 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 99235.135595 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 100118.052488 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 100118.052488 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 100118.052488 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 100118.052488 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 62980 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 18521.780088 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 18521.780088 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 91763.185146 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 91763.185146 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 90357.830898 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 90357.830898 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 90357.830898 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 90357.830898 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 61504 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5996 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5648 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.503669 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.889518 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 701 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 21264 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 21264 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 21965 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 21965 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 21965 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 21965 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95889055 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 95889055 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3530226785 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3530226785 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3626115840 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3626115840 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.770330 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.770330 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.455137 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.455137 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.461159 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.461159 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 136788.951498 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136788.951498 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 166018.942109 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 166018.942109 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 149 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 149 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 19296 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 19296 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 19445 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 19445 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 19445 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 19445 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 9180907 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 9180907 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3283180510 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3283180510 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3292361417 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3292361417 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3292361417 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3292361417 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.163020 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.163020 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.413014 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.413014 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.408217 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.408217 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.408217 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.408217 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61616.825503 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 61616.825503 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 170148.243677 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 170148.243677 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169316.606686 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 169316.606686 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169316.606686 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 169316.606686 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -907,488 +937,488 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52020310 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1696057 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1695532 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 5631 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 5631 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 870189 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 384 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 384 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 160044 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 138785 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 912543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3510594 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 23321 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 95695 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 4542153 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29200384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 115384682 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 82512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 359600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 145027178 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 267476487 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 95232 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4838788408 # Layer occupancy (ticks) +system.toL2Bus.throughput 52172743 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1753367 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1753366 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 5661 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 5661 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 894976 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 745 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 745 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 173207 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 153920 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 966317 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3599461 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 26176 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 114965 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 4706919 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 30921472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118979348 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 89784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 413728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 150404332 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 267998065 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 148408 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4987080585 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 814500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 706500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2054232112 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2176927347 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4517736918 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4676438168 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13025458 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 14970214 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 50823334 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 63358037 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1261125 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 151553 # Transaction distribution -system.iobus.trans_dist::ReadResp 151553 # Transaction distribution -system.iobus.trans_dist::WriteReq 26624 # Transaction distribution -system.iobus.trans_dist::WriteResp 26624 # Transaction distribution -system.iobus.trans_dist::MessageReq 269 # Transaction distribution -system.iobus.trans_dist::MessageResp 269 # Transaction distribution +system.iobus.throughput 1260736 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 151186 # Transaction distribution +system.iobus.trans_dist::ReadResp 151186 # Transaction distribution +system.iobus.trans_dist::WriteReq 24735 # Transaction distribution +system.iobus.trans_dist::WriteResp 24735 # Transaction distribution +system.iobus.trans_dist::MessageReq 216 # Transaction distribution +system.iobus.trans_dist::MessageResp 216 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 312424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 43930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 538 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 312952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 38890 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 432 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 432 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4266 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.com_1.pio 15770 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 38890 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 356892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 352274 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 159641 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1396968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 1076 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 159887 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1236136 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 864 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 864 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2412 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 76 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.com_1.pio 7885 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 1236136 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1557685 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6486722 # Total data (bytes) -system.iobus.reqLayer0.occupancy 624016 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 1396887 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6479664 # Total data (bytes) +system.iobus.reqLayer0.occupancy 492564 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3409000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 3525000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 24000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 145153000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 145313000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 43000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11757000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11833000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 193475840 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 175039167 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 307064000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 307513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 26474000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 20042250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 269000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 216000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1771999673 # number of cpu cycles simulated +system.cpu0.numCycles 1821353005 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 74314462 # Number of instructions committed -system.cpu0.committedOps 150407349 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 138687072 # Number of integer alu accesses +system.cpu0.committedInsts 73292155 # Number of instructions committed +system.cpu0.committedOps 148692338 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136997121 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1088594 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14472613 # number of instructions that are conditional controls -system.cpu0.num_int_insts 138687072 # number of integer instructions +system.cpu0.num_func_calls 1072392 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14299557 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136997121 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 341744011 # number of times the integer registers were read -system.cpu0.num_int_register_writes 175930003 # number of times the integer registers were written +system.cpu0.num_int_register_reads 337067923 # number of times the integer registers were read +system.cpu0.num_int_register_writes 173978676 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 15165282 # number of memory refs -system.cpu0.num_load_insts 10883561 # Number of load instructions -system.cpu0.num_store_insts 4281721 # Number of store instructions -system.cpu0.num_idle_cycles 1050845405256.983643 # Number of idle cycles -system.cpu0.num_busy_cycles -1049073405583.983643 # Number of busy cycles -system.cpu0.not_idle_fraction -592.027991 # Percentage of non-idle cycles -system.cpu0.idle_fraction 593.027991 # Percentage of idle cycles +system.cpu0.num_mem_refs 14736464 # number of memory refs +system.cpu0.num_load_insts 10677140 # Number of load instructions +system.cpu0.num_store_insts 4059324 # Number of store instructions +system.cpu0.num_idle_cycles 1078995887905.232788 # Number of idle cycles +system.cpu0.num_busy_cycles -1077174534900.232788 # Number of busy cycles +system.cpu0.not_idle_fraction -591.414477 # Percentage of non-idle cycles +system.cpu0.idle_fraction 592.414477 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.replacements 844132 # number of replacements -system.cpu0.icache.tagsinuse 510.847733 # Cycle average of tags in use -system.cpu0.icache.total_refs 131418089 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 844644 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 155.589916 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 147339657000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 322.177037 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 98.355742 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 90.314955 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.629252 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.192101 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.176396 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.997749 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 90666828 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38386818 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2364443 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 131418089 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 90666828 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38386818 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2364443 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 131418089 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 90666828 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38386818 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2364443 # number of overall hits -system.cpu0.icache.overall_hits::total 131418089 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 388368 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 156925 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 315252 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 860545 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 388368 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 156925 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 315252 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 860545 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 388368 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 156925 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 315252 # number of overall misses -system.cpu0.icache.overall_misses::total 860545 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2194798000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4530444487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6725242487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2194798000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4530444487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6725242487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2194798000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4530444487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6725242487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 91055196 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 38543743 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2679695 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 132278634 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 91055196 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 38543743 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2679695 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 132278634 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 91055196 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 38543743 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2679695 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 132278634 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004265 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004071 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117645 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006506 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004265 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004071 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117645 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006506 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004265 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004071 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117645 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006506 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13986.286443 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14370.866757 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7815.096813 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13986.286443 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14370.866757 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7815.096813 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13986.286443 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14370.866757 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7815.096813 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6390 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 847048 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.817647 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129995405 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 847560 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 153.376050 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147328649500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.566465 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 97.238420 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 93.012763 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.626106 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.189919 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.181666 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997691 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 89325030 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38126450 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2543925 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129995405 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 89325030 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38126450 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2543925 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129995405 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 89325030 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38126450 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2543925 # number of overall hits +system.cpu0.icache.overall_hits::total 129995405 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 364401 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 155633 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 345614 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 865648 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 364401 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 155633 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 345614 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 865648 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 364401 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 155633 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 345614 # number of overall misses +system.cpu0.icache.overall_misses::total 865648 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2193404000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5014378720 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7207782720 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2193404000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5014378720 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7207782720 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2193404000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5014378720 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7207782720 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 89689431 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38282083 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2889539 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130861053 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 89689431 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38282083 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2889539 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130861053 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 89689431 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38282083 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2889539 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130861053 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004063 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004065 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.119609 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006615 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004063 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004065 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.119609 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006615 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004063 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004065 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.119609 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006615 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14093.437767 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14508.609952 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8326.459161 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14093.437767 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14508.609952 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8326.459161 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14093.437767 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14508.609952 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8326.459161 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6927 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 177 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 238 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 36.101695 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.105042 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 15890 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 15890 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 15890 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 15890 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 15890 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 15890 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 156925 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 299362 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 456287 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 156925 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 299362 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 456287 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 156925 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 299362 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 456287 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1880948000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3764163875 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5645111875 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1880948000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3764163875 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5645111875 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1880948000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3764163875 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5645111875 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004071 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111715 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003449 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004071 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111715 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.003449 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004071 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111715 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.003449 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11986.286443 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12573.953524 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12371.844639 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11986.286443 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12573.953524 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12371.844639 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11986.286443 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12573.953524 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12371.844639 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 18078 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 18078 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 18078 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 18078 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 18078 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 18078 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 155633 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 327536 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 483169 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 155633 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 327536 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 483169 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 155633 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 327536 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 483169 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1880996000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4143986636 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6024982636 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1880996000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4143986636 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6024982636 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1880996000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4143986636 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6024982636 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004065 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.113352 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003692 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004065 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.113352 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.003692 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004065 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.113352 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.003692 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12086.099992 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12469.721021 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12086.099992 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12469.721021 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12086.099992 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12652.003554 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12469.721021 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1631841 # number of replacements -system.cpu0.dcache.tagsinuse 511.999003 # Cycle average of tags in use -system.cpu0.dcache.total_refs 19620985 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1632353 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 12.020062 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 366.099399 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 139.727177 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.172427 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.715038 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.272905 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012056 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999998 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5798796 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2305234 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3428925 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11532955 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4114382 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1531325 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2440703 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8086410 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9913178 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3836559 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 5869628 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19619365 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9913178 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3836559 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 5869628 # number of overall hits -system.cpu0.dcache.overall_hits::total 19619365 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 555419 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 229498 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 889034 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1673951 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 163701 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 61819 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 89692 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 315212 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 719120 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 291317 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 978726 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1989163 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 719120 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 291317 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 978726 # number of overall misses -system.cpu0.dcache.overall_misses::total 1989163 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3268485500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15010563000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 18279048500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2114115500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 2889797998 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5003913498 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5382601000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 17900360998 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 23282961998 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5382601000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 17900360998 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 23282961998 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6354215 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2534732 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4317959 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13206906 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4278083 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1593144 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2530395 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8401622 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10632298 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4127876 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 6848354 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21608528 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10632298 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4127876 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 6848354 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21608528 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.087410 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.090541 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.205892 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.126748 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038265 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.038803 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.035446 # miss rate for WriteReq accesses +system.cpu0.dcache.tags.replacements 1634474 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999389 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19647501 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1634986 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.016923 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 379.364018 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 126.391213 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.244158 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.740945 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.246858 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012196 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5614384 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2225977 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 3715968 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11556329 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3907488 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1533784 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2648186 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8089458 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9521872 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3759761 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6364154 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19645787 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9521872 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3759761 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6364154 # number of overall hits +system.cpu0.dcache.overall_hits::total 19645787 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 541799 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 231251 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 917589 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1690639 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 148229 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 67168 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 99931 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 315328 # number of WriteReq misses +system.cpu0.dcache.demand_misses::cpu0.data 690028 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 298419 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1017520 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2005967 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 690028 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 298419 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1017520 # number of overall misses +system.cpu0.dcache.overall_misses::total 2005967 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3337683757 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15521474368 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18859158125 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2326474532 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3256971146 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5583445678 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 5664158289 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 18778445514 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24442603803 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 5664158289 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 18778445514 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24442603803 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6156183 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2457228 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4633557 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13246968 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4055717 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1600952 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2748117 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8404786 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10211900 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4058180 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7381674 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21651754 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10211900 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4058180 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7381674 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21651754 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.088009 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.094111 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.198031 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127625 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036548 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.041955 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.036363 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.037518 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.067635 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.070573 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.142914 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092055 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067635 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.070573 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.142914 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092055 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14241.890997 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16884.127041 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10919.703444 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34198.474579 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32219.127659 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15874.755714 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18476.783023 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18289.450774 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 11704.904021 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18476.783023 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18289.450774 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11704.904021 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 179212 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.067571 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.073535 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137844 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092647 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067571 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.073535 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137844 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092647 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14433.164644 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16915.497426 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11155.047367 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34636.650369 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32592.200078 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17706.786831 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18980.555156 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18455.111953 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12184.948109 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18980.555156 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18455.111953 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12184.948109 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 172601 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11783 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11703 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.209369 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.748441 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1541993 # number of writebacks -system.cpu0.dcache.writebacks::total 1541993 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 342834 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 342834 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 12370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 12370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 355204 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 355204 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 355204 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 355204 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 229498 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 546200 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 775698 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 61819 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 77322 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 139141 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 291317 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 623522 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 914839 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 291317 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 623522 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 914839 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2809489500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8130780549 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10940270049 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1990477500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2600292531 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4590770031 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4799967000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10731073080 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15531040080 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4799967000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10731073080 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15531040080 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31033142000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33153511000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64186653000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 465277000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 664192000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1129469000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31498419000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33817703000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65316122000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.090541 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.126495 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.058734 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038803 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030557 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016561 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.042337 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.042337 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12241.890997 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14886.086688 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14103.774986 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32198.474579 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33629.400830 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32993.654142 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1544497 # number of writebacks +system.cpu0.dcache.writebacks::total 1544497 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 356856 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 356856 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 12485 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 12485 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 369341 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 369341 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 369341 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 369341 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231251 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 560733 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 791984 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 67168 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 87446 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 154614 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 298419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 648179 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 946598 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 298419 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 648179 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 946598 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2872959243 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8335143522 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11208102765 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2180545468 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2931248595 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5111794063 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 5053504711 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11266392117 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16319896828 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5053504711 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11266392117 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16319896828 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31052633000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33182784500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64235417500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 405522500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 732474500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1137997000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31458155500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33915259000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65373414500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.094111 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121016 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.059786 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.041955 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031820 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018396 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.073535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087809 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.043719 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.073535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087809 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.043719 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12423.553814 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14864.727994 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14151.930803 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32464.052346 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33520.670986 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33061.650711 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16934.259250 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17381.606187 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17240.578184 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16934.259250 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17381.606187 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17240.578184 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1399,303 +1429,303 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608004713 # number of cpu cycles simulated +system.cpu1.numCycles 2606005785 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34942757 # Number of instructions committed -system.cpu1.committedOps 68016284 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63114732 # Number of integer alu accesses +system.cpu1.committedInsts 34706075 # Number of instructions committed +system.cpu1.committedOps 67513326 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 62627092 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 430753 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6467325 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63114732 # number of integer instructions +system.cpu1.num_func_calls 413647 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6441517 # number of instructions that are conditional controls +system.cpu1.num_int_insts 62627092 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 152021040 # number of times the integer registers were read -system.cpu1.num_int_register_writes 81233840 # number of times the integer registers were written +system.cpu1.num_int_register_reads 150899030 # number of times the integer registers were read +system.cpu1.num_int_register_writes 80614256 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 4322210 # number of memory refs -system.cpu1.num_load_insts 2726743 # Number of load instructions -system.cpu1.num_store_insts 1595467 # Number of store instructions -system.cpu1.num_idle_cycles 9296961839.327438 # Number of idle cycles -system.cpu1.num_busy_cycles -6688957126.327438 # Number of busy cycles -system.cpu1.not_idle_fraction -2.564780 # Percentage of non-idle cycles -system.cpu1.idle_fraction 3.564780 # Percentage of idle cycles +system.cpu1.num_mem_refs 4252332 # number of memory refs +system.cpu1.num_load_insts 2649427 # Number of load instructions +system.cpu1.num_store_insts 1602905 # Number of store instructions +system.cpu1.num_idle_cycles 9584663693.774578 # Number of idle cycles +system.cpu1.num_busy_cycles -6978657908.774579 # Number of busy cycles +system.cpu1.not_idle_fraction -2.677913 # Percentage of non-idle cycles +system.cpu1.idle_fraction 3.677913 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28107723 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28107723 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 253065 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 25890078 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25466613 # Number of BTB hits +system.cpu2.branchPred.lookups 28549199 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28549199 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 285864 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26202333 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25707724 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.364373 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 482621 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 53231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 150677905 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 98.112347 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 509000 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 57796 # Number of incorrect RAS predictions. +system.cpu2.numCycles 153739924 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8157389 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 138649085 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28107723 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 25949234 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 53330196 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1190060 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 46897 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 22689996 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 1645 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6110 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 10082 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2679696 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 114342 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1368 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 85168083 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.213895 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.414010 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8861182 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 140768018 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28549199 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26216724 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54013734 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1344784 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 58192 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 24037963 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 3706 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6519 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 19114 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 569 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2889543 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 128346 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1609 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 88045773 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.152898 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.410636 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 31941663 37.50% 37.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 506826 0.60% 38.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23646883 27.76% 65.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 259157 0.30% 66.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 526154 0.62% 66.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 751269 0.88% 67.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 273870 0.32% 67.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 459070 0.54% 68.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 26803191 31.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 34147694 38.78% 38.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 547423 0.62% 39.41% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23764633 26.99% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 284582 0.32% 66.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 557969 0.63% 67.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 795617 0.90% 68.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 319692 0.36% 68.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 484471 0.55% 69.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27143692 30.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 85168083 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.186542 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.920169 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9520844 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 21607924 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 39424228 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1229084 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 928772 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 273051293 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 4 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 928772 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10439907 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13089260 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 3699901 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 39570553 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 4982521 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 272244708 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6270 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2417106 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 1932594 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 1355 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 325535285 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 590374943 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 590374855 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 88 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 317221539 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 8313746 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 122579 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 123510 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 10816950 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 5506267 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2968253 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 324837 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 268098 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 270840712 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 382144 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 269680817 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 48233 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 5882884 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 8996381 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 45929 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 85168083 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.166454 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.381789 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 88045773 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185698 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.915624 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10285454 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 22943626 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 41627806 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1270133 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1048147 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 276853450 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 7 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1048147 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11254615 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13961054 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 3963789 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 41762702 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5184927 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 275944284 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6769 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2459328 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2061675 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 2717 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 329857779 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 599690764 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 599690564 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 200 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320509391 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 9348388 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 136043 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 137064 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11288733 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 5902057 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3230740 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 354441 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 291130 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 274390669 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 398438 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 272978735 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 57079 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 6609909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10125547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 50893 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 88045773 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.100418 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.393656 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 23491447 27.58% 27.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5639421 6.62% 34.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3592727 4.22% 38.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2433201 2.86% 41.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 24826332 29.15% 70.43% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1184872 1.39% 71.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23718098 27.85% 99.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 237817 0.28% 99.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44168 0.05% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 25312226 28.75% 28.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5904467 6.71% 35.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3803238 4.32% 39.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2580509 2.93% 42.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25019730 28.42% 71.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1259471 1.43% 72.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23861754 27.10% 99.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 255558 0.29% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 48820 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 85168083 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 88045773 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 103037 31.19% 31.19% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 241 0.07% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 31.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 181800 55.03% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 45300 13.71% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 115953 32.52% 32.52% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 120 0.03% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 32.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 188030 52.73% 85.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 52485 14.72% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 57001 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 260895656 96.74% 96.76% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 47542 0.02% 96.78% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 43696 0.02% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.80% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 5855050 2.17% 98.97% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2781872 1.03% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 70354 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263570476 96.55% 96.58% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 51118 0.02% 96.60% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 46597 0.02% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6213747 2.28% 98.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3026443 1.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 269680817 # Type of FU issued -system.cpu2.iq.rate 1.789783 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 330378 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001225 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 624940807 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 277108342 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 268465757 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 40 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 38 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 269954173 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 21 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 584645 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 272978735 # Type of FU issued +system.cpu2.iq.rate 1.775588 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 356588 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001306 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 634455588 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 281402142 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 271688146 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 29 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 273264957 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 12 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 613124 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 814531 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6351 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3024 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 433740 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 928259 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6814 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3642 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 478181 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 655738 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10426 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656152 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10356 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 928772 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 8598252 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 798569 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 271222856 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 58264 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 5506267 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2968253 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 206333 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 621407 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3570 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3024 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 146514 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 137704 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 284218 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 269282728 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 5768116 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 398089 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1048147 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9348181 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 808638 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 274789107 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 65396 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 5902057 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3230758 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 220588 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 626855 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4558 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3642 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 161804 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 161245 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 323049 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 272529284 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6113028 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 449451 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 8495654 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27379135 # Number of branches executed -system.cpu2.iew.exec_stores 2727538 # Number of stores executed -system.cpu2.iew.exec_rate 1.787141 # Inst execution rate -system.cpu2.iew.wb_sent 269160909 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 268465771 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 209852405 # num instructions producing a value -system.cpu2.iew.wb_consumers 343221010 # num instructions consuming a value +system.cpu2.iew.exec_refs 9080043 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27720555 # Number of branches executed +system.cpu2.iew.exec_stores 2967015 # Number of stores executed +system.cpu2.iew.exec_rate 1.772664 # Inst execution rate +system.cpu2.iew.wb_sent 272391201 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 271688152 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212092617 # num instructions producing a value +system.cpu2.iew.wb_consumers 346983399 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.781720 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611421 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.767193 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611247 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 6125563 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 336215 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 254201 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 84239311 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.146959 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.869440 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 6884729 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 347545 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 288057 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 86997626 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.079430 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.871941 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 28027655 33.27% 33.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 3948624 4.69% 37.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1090324 1.29% 39.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24397189 28.96% 68.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 757994 0.90% 69.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 507340 0.60% 69.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 301970 0.36% 70.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23269432 27.62% 97.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1938783 2.30% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 29972174 34.45% 34.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4215922 4.85% 39.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1166731 1.34% 40.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24592469 28.27% 68.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 801811 0.92% 69.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 544306 0.63% 70.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 310409 0.36% 70.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23365384 26.86% 97.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2028420 2.33% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 84239311 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 134086437 # Number of instructions committed -system.cpu2.commit.committedOps 265097623 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 86997626 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135649483 # Number of instructions committed +system.cpu2.commit.committedOps 267903067 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7226249 # Number of memory references committed -system.cpu2.commit.loads 4691736 # Number of loads committed -system.cpu2.commit.membars 162513 # Number of memory barriers committed -system.cpu2.commit.branches 27101249 # Number of branches committed +system.cpu2.commit.refs 7726375 # Number of memory references committed +system.cpu2.commit.loads 4973798 # Number of loads committed +system.cpu2.commit.membars 163952 # Number of memory barriers committed +system.cpu2.commit.branches 27408076 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 241753447 # Number of committed integer instructions. -system.cpu2.commit.function_calls 394614 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1938783 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 244468826 # Number of committed integer instructions. +system.cpu2.commit.function_calls 411685 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2028420 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 353502675 # The number of ROB reads -system.cpu2.rob.rob_writes 543377618 # The number of ROB writes -system.cpu2.timesIdled 448607 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65509822 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4919608430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 134086437 # Number of Instructions Simulated -system.cpu2.committedOps 265097623 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 134086437 # Number of Instructions Simulated -system.cpu2.cpi 1.123737 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.123737 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.889888 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.889888 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 494284042 # number of integer regfile reads -system.cpu2.int_regfile_writes 320739139 # number of integer regfile writes -system.cpu2.fp_regfile_reads 62606 # number of floating regfile reads -system.cpu2.fp_regfile_writes 62592 # number of floating regfile writes -system.cpu2.misc_regfile_reads 86693613 # number of misc regfile reads -system.cpu2.misc_regfile_writes 110320 # number of misc regfile writes +system.cpu2.rob.rob_reads 359731311 # The number of ROB reads +system.cpu2.rob.rob_writes 550627170 # The number of ROB writes +system.cpu2.timesIdled 462650 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65694151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4912523731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135649483 # Number of Instructions Simulated +system.cpu2.committedOps 267903067 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 135649483 # Number of Instructions Simulated +system.cpu2.cpi 1.133362 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.133362 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.882331 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.882331 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 500765277 # number of integer regfile reads +system.cpu2.int_regfile_writes 324464285 # number of integer regfile writes +system.cpu2.fp_regfile_reads 62550 # number of floating regfile reads +system.cpu2.fp_regfile_writes 62544 # number of floating regfile writes +system.cpu2.misc_regfile_reads 88091146 # number of misc regfile reads +system.cpu2.misc_regfile_writes 122333 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |