diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref')
9 files changed, 881 insertions, 880 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index fe256a291..e3424a85b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1560,7 +1560,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1583,7 +1583,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 0a8bc6fbe..0aaa4f921 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -1,7 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 3b996a550..91003600d 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:07 -gem5 started Oct 29 2014 09:27:02 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5125902116500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 560862ac3..a6e63eaeb 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.125902 # Nu sim_ticks 5125902116500 # Number of ticks simulated final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182847 # Simulator instruction rate (inst/s) -host_op_rate 361437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2297162464 # Simulator tick rate (ticks/s) -host_mem_usage 805240 # Number of bytes of host memory used -host_seconds 2231.41 # Real time elapsed on the host +host_inst_rate 225212 # Simulator instruction rate (inst/s) +host_op_rate 445179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2829401321 # Simulator tick rate (ticks/s) +host_mem_usage 748772 # Number of bytes of host memory used +host_seconds 1811.66 # Real time elapsed on the host sim_insts 408006726 # Number of instructions simulated sim_ops 806511598 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 5c0ccd72f..d43104caf 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1616,7 +1616,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1639,7 +1639,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json index 3c9f7ff5e..3be878044 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json @@ -2,7 +2,7 @@ "name": null, "sim_quantum": 0, "system": { - "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9", + "kernel": "/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9", "l2c": { "is_top_level": false, "prefetcher": null, @@ -145,7 +145,7 @@ "type": "Bridge" }, "symbolfile": "", - "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", + "readfile": "/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh", "intel_mp_table": { "oem_table_addr": 0, "name": "intel_mp_table", @@ -1176,7 +1176,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks0.image.child", - "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img", + "image_file": "/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks0.image", @@ -1204,7 +1204,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks1.image.child", - "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img", + "image_file": "/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks1.image", @@ -1629,8 +1629,9 @@ "IDD3N": "0.057", "name": "physmem", "tXSDLL": 0, - "tXAW": 30000, + "device_size": 536870912, "dll": true, + "tXAW": 30000, "write_low_thresh_perc": 50, "range": "0:134217727", "VDD2": "0.0", diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index b4d02041b..2cf33b630 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -1,7 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index ca2891ded..498a02071 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:07 -gem5 started Oct 29 2014 09:28:19 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 847df0bf1..4de64b96e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,16 +4,15 @@ sim_seconds 5.137752 # Nu sim_ticks 5137751757500 # Number of ticks simulated final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311526 # Simulator instruction rate (inst/s) -host_op_rate 619354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6572918502 # Simulator tick rate (ticks/s) -host_mem_usage 927072 # Number of bytes of host memory used -host_seconds 781.65 # Real time elapsed on the host +host_inst_rate 342085 # Simulator instruction rate (inst/s) +host_op_rate 680107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7217672543 # Simulator tick rate (ticks/s) +host_mem_usage 932836 # Number of bytes of host memory used +host_seconds 711.83 # Real time elapsed on the host sim_insts 243506025 # Number of instructions simulated sim_ops 484120527 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 475328 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 5564736 # Number of bytes read from this memory @@ -23,6 +22,7 @@ system.physmem.bytes_read::cpu1.data 2113344 # Nu system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 362880 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 2752000 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::total 11429696 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 475328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 130048 # Number of instructions bytes read from this memory @@ -31,7 +31,6 @@ system.physmem.bytes_inst_read::total 968256 # Nu system.physmem.bytes_written::writebacks 6180416 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory system.physmem.bytes_written::total 9170496 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 7427 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 86949 # Number of read requests responded to by this memory @@ -41,11 +40,11 @@ system.physmem.num_reads::cpu1.data 33021 # Nu system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 5670 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 43000 # Number of read requests responded to by this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 178589 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96569 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory system.physmem.num_writes::total 143289 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 92517 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1083107 # Total read bandwidth from this memory (bytes/s) @@ -55,6 +54,7 @@ system.physmem.bw_read::cpu1.data 411336 # To system.physmem.bw_read::cpu2.dtb.walker 523 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 70630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.data 535643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2224649 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 92517 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 25312 # Instruction read bandwidth from this memory (bytes/s) @@ -64,7 +64,6 @@ system.physmem.bw_write::writebacks 1202942 # Wr system.physmem.bw_write::pc.south_bridge.ide 581982 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1784924 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1202942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 587501 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 92517 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 1083107 # Total bandwidth to/from this memory (bytes/s) @@ -74,6 +73,7 @@ system.physmem.bw_total::cpu1.data 411336 # To system.physmem.bw_total::cpu2.dtb.walker 523 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 70630 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 535643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 587501 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4009573 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 84209 # Number of read requests accepted system.physmem.writeReqs 74716 # Number of write requests accepted @@ -329,712 +329,7 @@ system.physmem.totalEnergy::0 3434046565050 # T system.physmem.totalEnergy::1 3434197896405 # Total energy per rank (pJ) system.physmem.averagePower::0 668.395092 # Core power per rank (mW) system.physmem.averagePower::1 668.424547 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 5119571 # Transaction distribution -system.membus.trans_dist::ReadResp 5119569 # Transaction distribution -system.membus.trans_dist::WriteReq 13900 # Transaction distribution -system.membus.trans_dist::WriteResp 13900 # Transaction distribution -system.membus.trans_dist::Writeback 96569 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1658 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1658 # Transaction distribution -system.membus.trans_dist::ReadExReq 130179 # Transaction distribution -system.membus.trans_dist::ReadExResp 130179 # Transaction distribution -system.membus.trans_dist::MessageReq 1687 # Transaction distribution -system.membus.trans_dist::MessageResp 1687 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10625377 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10723708 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079977 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17581760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27232497 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3029312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30268557 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 291 # Total snoops (count) -system.membus.snoop_fanout::samples 323999 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 323999 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 323999 # Request fanout histogram -system.membus.reqLayer0.occupancy 162958500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314938500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2254000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 804193000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1127000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1664243698 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 28678745 # Layer occupancy (ticks) -system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 104648 # number of replacements -system.l2c.tags.tagsinuse 64825.327064 # Cycle average of tags in use -system.l2c.tags.total_refs 3691316 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168821 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.865266 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51329.060133 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131449 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1735.761730 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4946.132925 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 379.214744 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1982.386911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.162749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 878.696468 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3562.776774 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.783219 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.026486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075472 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005786 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.013408 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.054364 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989156 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3770 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7642 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52446 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979202 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33857298 # Number of tag accesses -system.l2c.tags.data_accesses 33857298 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 21885 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 321088 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 497388 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 12632 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 160077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 224317 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 53710 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 12539 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 370609 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 592462 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2284715 # number of ReadReq hits -system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits -system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1547592 # number of Writeback hits -system.l2c.Writeback_hits::total 1547592 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 126 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 49 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 89 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 264 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63533 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 34910 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 62567 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 161010 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21885 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11415 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 321088 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 560921 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12632 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 160077 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 259227 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 53710 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 12539 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 370609 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 655029 # number of demand (read+write) hits -system.l2c.demand_hits::total 2445727 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21885 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11415 # number of overall hits -system.l2c.overall_hits::cpu0.inst 321088 # number of overall hits -system.l2c.overall_hits::cpu0.data 560921 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12632 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6595 # number of overall hits -system.l2c.overall_hits::cpu1.inst 160077 # number of overall hits -system.l2c.overall_hits::cpu1.data 259227 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 53710 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 12539 # number of overall hits -system.l2c.overall_hits::cpu2.inst 370609 # number of overall hits -system.l2c.overall_hits::cpu2.data 655029 # number of overall hits -system.l2c.overall_hits::total 2445727 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7427 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 17501 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2032 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4808 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 42 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5670 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 10484 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47969 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 766 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 250 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 384 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1400 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 69535 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 28299 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 32603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130437 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7427 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 87036 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2032 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 33107 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 42 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5670 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 43087 # number of demand (read+write) misses -system.l2c.demand_misses::total 178406 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7427 # number of overall misses -system.l2c.overall_misses::cpu0.data 87036 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2032 # number of overall misses -system.l2c.overall_misses::cpu1.data 33107 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 42 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5670 # number of overall misses -system.l2c.overall_misses::cpu2.data 43087 # number of overall misses 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-system.l2c.overall_miss_latency::cpu1.inst 150329750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2309689164 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 3647250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 442043250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3157543915 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6063327829 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 21885 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 11417 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 328515 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 514889 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 12632 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6596 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 162109 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 229125 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 53752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 12539 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 376279 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 602946 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2332684 # number of ReadReq accesses(hits+misses) -system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) -system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1547592 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1547592 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 892 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 299 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 473 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 133068 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 63209 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 95170 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 291447 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 21885 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 11419 # number of demand (read+write) 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-system.l2c.overall_accesses::cpu0.dtb.walker 21885 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 11419 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 328515 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 647957 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 12632 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6596 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 162109 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 292334 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 53752 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 12539 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 376279 # number of overall (read+write) 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miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.858744 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836120 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.811839 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.841346 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.522552 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.447705 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.342576 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.447550 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000350 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.022608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.134324 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000152 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.012535 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.113251 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.015069 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.061719 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.067987 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000350 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.022608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.134324 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000152 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.012535 # miss rate for overall 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average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 77961.772487 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 73282.983615 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 33986.120585 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 73981.176181 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69764.375026 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 77961.772487 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 73282.983615 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 33986.120585 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles 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(read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 42 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5670 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 43087 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 83939 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2032 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 33107 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 42 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5670 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 43087 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 83939 # number of overall MSHR misses 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4993742171 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 124575250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1885882836 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 371081250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2609013085 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4993742171 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27997217000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30232738500 # number of ReadReq MSHR uncacheable cycles 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0.208964 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.061719 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.031987 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for overall accesses 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overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56963.265654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.092434 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092434 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005777 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005777 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428616 # Number of tag accesses -system.iocache.tags.data_accesses 428616 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses -system.iocache.demand_misses::total 904 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses -system.iocache.overall_misses::total 904 # number of overall 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accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145941.954646 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145941.954646 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145941.954646 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 734 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93740027 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1329860248 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1329860248 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 93740027 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7431790 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7431262 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1547592 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22056 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291447 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291447 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14997138 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72735 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 201275 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17005004 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55482624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213567857 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 271280 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 749120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270070881 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 66934 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4248687 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011209 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105278 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4201063 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4248687 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5247340592 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2425844552 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4872344858 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24091410 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 80681637 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 3554542 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554542 # Transaction distribution -system.iobus.trans_dist::WriteReq 57685 # Transaction distribution -system.iobus.trans_dist::WriteResp 33021 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 24664 # Transaction distribution -system.iobus.trans_dist::MessageReq 1687 # Transaction distribution -system.iobus.trans_dist::MessageResp 1687 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27782 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7129206 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7227828 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13891 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3570760 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605284 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2693792 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4846000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 333000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10264000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 199614020 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303080000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 27344255 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1127000 # Layer occupancy (ticks) -system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu0.numCycles 818767223 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -1098,143 +393,6 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 146799291 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 866413 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.840210 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 130156159 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 866925 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 150.135432 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149014386250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 138.994027 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 266.522548 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 105.323634 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.271473 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.520552 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.205710 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997735 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131912504 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131912504 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 87639896 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39531787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2984476 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 130156159 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87639896 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39531787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2984476 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 130156159 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87639896 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39531787 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2984476 # number of overall hits -system.cpu0.icache.overall_hits::total 130156159 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 328528 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 162109 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 398768 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 889405 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 328528 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 162109 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 398768 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 889405 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 328528 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 162109 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 398768 # number of overall misses -system.cpu0.icache.overall_misses::total 889405 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2245844750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5606326194 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7852170944 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2245844750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5606326194 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7852170944 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2245844750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5606326194 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7852170944 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87968424 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39693896 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3383244 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 131045564 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87968424 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39693896 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3383244 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 131045564 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87968424 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39693896 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3383244 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 131045564 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003735 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004084 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117866 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006787 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003735 # 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+system.cpu0.icache.overall_avg_miss_latency::total 8828.566226 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4938 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 262 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.847328 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22465 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 22465 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 22465 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 22465 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 22465 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 22465 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162109 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376303 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 538412 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 162109 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 376303 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 538412 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 162109 # number of overall MSHR misses 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4627637688 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6548542938 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004109 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004109 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004109 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12162.698710 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 2606022983 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1830,6 +1125,711 @@ system.cpu2.cc_regfile_reads 138904210 # nu system.cpu2.cc_regfile_writes 106846664 # number of cc regfile writes system.cpu2.misc_regfile_reads 88678814 # number of misc regfile reads system.cpu2.misc_regfile_writes 129757 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3554542 # Transaction distribution +system.iobus.trans_dist::ReadResp 3554542 # Transaction distribution +system.iobus.trans_dist::WriteReq 57685 # Transaction distribution +system.iobus.trans_dist::WriteResp 33021 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 24664 # Transaction distribution +system.iobus.trans_dist::MessageReq 1687 # Transaction distribution +system.iobus.trans_dist::MessageResp 1687 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27782 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7129206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7227828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13891 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 3570760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6605284 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2693792 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 4846000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 10264000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 199614020 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 303080000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 27344255 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1127000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.092434 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092434 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005777 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005777 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428616 # Number of tag accesses +system.iocache.tags.data_accesses 428616 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses +system.iocache.demand_misses::total 904 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses +system.iocache.overall_misses::total 904 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131931527 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 131931527 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 131931527 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 131931527 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 131931527 # number of overall miss cycles +system.iocache.overall_miss_latency::total 131931527 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145941.954646 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145941.954646 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145941.954646 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 734 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93740027 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1329860248 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1329860248 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 93740027 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 104648 # number of replacements +system.l2c.tags.tagsinuse 64825.327064 # Cycle average of tags in use +system.l2c.tags.total_refs 3691316 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168821 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.865266 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 51329.060133 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131449 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1735.761730 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4946.132925 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 379.214744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1982.386911 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.162749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 878.696468 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3562.776774 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.783219 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.026486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.005786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.030249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.013408 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.054364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989156 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3770 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7642 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52446 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979202 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33857298 # Number of tag accesses +system.l2c.tags.data_accesses 33857298 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 21885 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11413 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 321088 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 497388 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12632 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6595 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 160077 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 224317 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 53710 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 12539 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 370609 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 592462 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2284715 # number of ReadReq hits +system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits +system.l2c.WriteReq_hits::total 2 # number of WriteReq hits +system.l2c.Writeback_hits::writebacks 1547592 # number of Writeback hits +system.l2c.Writeback_hits::total 1547592 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 126 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 49 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 89 # number of UpgradeReq hits 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6361381 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1578314336 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1925294585 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3503608921 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 124575250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1885882836 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 371081250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2609013085 # number of demand (read+write) MSHR miss cycles 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cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58229955500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 537806500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 646167500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1183974000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28535023500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30878906000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59413929500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020984 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017388 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.009876 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836120 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.811839 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.381010 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.447705 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.342576 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.208964 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.061719 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.031987 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.061719 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.031987 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63970.153910 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65215.423502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64684.344750 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10054.377604 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.723975 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55772.795364 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59052.681808 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57528.634872 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56963.265654 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56963.265654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 5119571 # Transaction distribution +system.membus.trans_dist::ReadResp 5119569 # Transaction distribution +system.membus.trans_dist::WriteReq 13900 # Transaction distribution +system.membus.trans_dist::WriteResp 13900 # Transaction distribution +system.membus.trans_dist::Writeback 96569 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1658 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1658 # Transaction distribution +system.membus.trans_dist::ReadExReq 130179 # Transaction distribution +system.membus.trans_dist::ReadExResp 130179 # Transaction distribution +system.membus.trans_dist::MessageReq 1687 # Transaction distribution +system.membus.trans_dist::MessageResp 1687 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10625377 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10723708 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079977 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17581760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27232497 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3029312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30268557 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 291 # Total snoops (count) +system.membus.snoop_fanout::samples 323999 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 323999 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 323999 # Request fanout histogram +system.membus.reqLayer0.occupancy 162958500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 314938500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 2254000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 804193000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1127000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1664243698 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 28678745 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 7431790 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7431262 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1547592 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22056 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291447 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291447 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14997138 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72735 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 201275 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17005004 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55482624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213567857 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 271280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 749120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270070881 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 66934 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4248687 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011209 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105278 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4201063 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4248687 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5247340592 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2425844552 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4872344858 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 24091410 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 80681637 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |