diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref')
22 files changed, 18282 insertions, 16227 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index dfd7f9bb3..38f343beb 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -79,6 +84,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -143,6 +150,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -158,6 +166,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -180,26 +189,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu0.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -208,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -226,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -250,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -274,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -286,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -412,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -424,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -442,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -456,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -478,21 +534,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu0.isa] type=AlphaISA +eventq_index=0 [system.cpu0.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -523,6 +584,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -587,6 +650,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -602,6 +666,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -624,26 +689,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu1.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -652,16 +722,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -670,22 +743,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -694,22 +771,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -718,10 +799,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -730,124 +813,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -856,10 +960,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -868,16 +974,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -886,10 +995,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -900,6 +1011,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -922,25 +1034,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu1.isa] type=AlphaISA +eventq_index=0 [system.cpu1.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -948,19 +1066,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -968,28 +1089,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -1003,6 +1129,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1025,6 +1152,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1034,6 +1162,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1056,6 +1185,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1063,6 +1193,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1074,6 +1205,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1100,6 +1232,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1111,29 +1244,35 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1142,6 +1281,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1152,6 +1292,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -1160,6 +1301,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -1170,6 +1312,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -1198,6 +1341,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -1207,8 +1351,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -1225,6 +1401,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -1248,6 +1425,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -1265,6 +1443,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -1282,6 +1461,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -1299,6 +1479,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -1316,6 +1497,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -1333,6 +1515,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -1350,6 +1533,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -1367,6 +1551,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -1384,6 +1569,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -1401,6 +1587,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -1418,6 +1605,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -1435,6 +1623,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -1452,6 +1641,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -1469,6 +1659,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -1486,6 +1677,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -1503,6 +1695,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -1520,6 +1713,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -1537,6 +1731,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -1554,6 +1749,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -1572,6 +1768,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -1599,6 +1796,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1608,8 +1806,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1621,6 +1851,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -1635,6 +1866,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -1647,6 +1879,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -1657,6 +1890,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -1667,6 +1901,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1676,5 +1911,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index fc255dc72..3ddbcdbc7 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.904665 # Number of seconds simulated -sim_ticks 1904665099500 # Number of ticks simulated -final_tick 1904665099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903338 # Number of seconds simulated +sim_ticks 1903338216000 # Number of ticks simulated +final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126318 # Simulator instruction rate (inst/s) -host_op_rate 126318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4285588150 # Simulator tick rate (ticks/s) -host_mem_usage 339596 # Number of bytes of host memory used -host_seconds 444.44 # Real time elapsed on the host -sim_insts 56140339 # Number of instructions simulated -sim_ops 56140339 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 734400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24199744 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 243008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1012480 # Number of bytes read from this memory -system.physmem.bytes_read::total 28839936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 734400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 243008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7811840 # Number of bytes written to this memory -system.physmem.bytes_written::total 7811840 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11475 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 378121 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41411 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3797 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15820 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450624 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122060 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122060 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 385580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12705511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 127586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 531579 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15141736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 385580 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 127586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4101424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4101424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4101424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 385580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12705511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 127586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 531579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19243160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450624 # Number of read requests accepted -system.physmem.writeReqs 122060 # Number of write requests accepted -system.physmem.readBursts 450624 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122060 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28836416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3520 # Total number of bytes read from write queue -system.physmem.bytesWritten 7811520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28839936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7811840 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by the write queue +host_inst_rate 100362 # Simulator instruction rate (inst/s) +host_op_rate 100362 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3404824916 # Simulator tick rate (ticks/s) +host_mem_usage 359096 # Number of bytes of host memory used +host_seconds 559.01 # Real time elapsed on the host +sim_insts 56103611 # Number of instructions simulated +sim_ops 56103611 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 236544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 996032 # Number of bytes read from this memory +system.physmem.bytes_read::total 28970176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 740992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 236544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7923904 # Number of bytes written to this memory +system.physmem.bytes_written::total 7923904 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 380413 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15563 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452659 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123811 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123811 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 389312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12791438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1392383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 124278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 523308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15220719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 389312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 124278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4163161 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4163161 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4163161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 389312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12791438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1392383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 124278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 523308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19383880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 452659 # Number of read requests accepted +system.physmem.writeReqs 123811 # Number of write requests accepted +system.physmem.readBursts 452659 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123811 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28966400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3776 # Total number of bytes read from write queue +system.physmem.bytesWritten 7923264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28970176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7923904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3409 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28171 # Per bank write bursts -system.physmem.perBankRdBursts::1 27944 # Per bank write bursts -system.physmem.perBankRdBursts::2 28133 # Per bank write bursts -system.physmem.perBankRdBursts::3 27978 # Per bank write bursts -system.physmem.perBankRdBursts::4 27881 # Per bank write bursts -system.physmem.perBankRdBursts::5 28082 # Per bank write bursts -system.physmem.perBankRdBursts::6 28123 # Per bank write bursts -system.physmem.perBankRdBursts::7 28118 # Per bank write bursts -system.physmem.perBankRdBursts::8 28377 # Per bank write bursts -system.physmem.perBankRdBursts::9 28284 # Per bank write bursts -system.physmem.perBankRdBursts::10 27947 # Per bank write bursts -system.physmem.perBankRdBursts::11 28190 # Per bank write bursts -system.physmem.perBankRdBursts::12 28259 # Per bank write bursts -system.physmem.perBankRdBursts::13 28280 # Per bank write bursts -system.physmem.perBankRdBursts::14 28300 # Per bank write bursts -system.physmem.perBankRdBursts::15 28502 # Per bank write bursts -system.physmem.perBankWrBursts::0 7913 # Per bank write bursts -system.physmem.perBankWrBursts::1 7477 # Per bank write bursts -system.physmem.perBankWrBursts::2 7607 # Per bank write bursts -system.physmem.perBankWrBursts::3 7420 # Per bank write bursts -system.physmem.perBankWrBursts::4 7384 # Per bank write bursts -system.physmem.perBankWrBursts::5 7571 # Per bank write bursts -system.physmem.perBankWrBursts::6 7682 # Per bank write bursts -system.physmem.perBankWrBursts::7 7471 # Per bank write bursts -system.physmem.perBankWrBursts::8 7660 # Per bank write bursts -system.physmem.perBankWrBursts::9 7641 # Per bank write bursts -system.physmem.perBankWrBursts::10 7379 # Per bank write bursts -system.physmem.perBankWrBursts::11 7517 # Per bank write bursts -system.physmem.perBankWrBursts::12 7673 # Per bank write bursts -system.physmem.perBankWrBursts::13 7762 # Per bank write bursts -system.physmem.perBankWrBursts::14 7923 # Per bank write bursts -system.physmem.perBankWrBursts::15 7975 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3474 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28542 # Per bank write bursts +system.physmem.perBankRdBursts::1 28115 # Per bank write bursts +system.physmem.perBankRdBursts::2 28449 # Per bank write bursts +system.physmem.perBankRdBursts::3 28319 # Per bank write bursts +system.physmem.perBankRdBursts::4 28001 # Per bank write bursts +system.physmem.perBankRdBursts::5 28388 # Per bank write bursts +system.physmem.perBankRdBursts::6 28437 # Per bank write bursts +system.physmem.perBankRdBursts::7 28681 # Per bank write bursts +system.physmem.perBankRdBursts::8 28670 # Per bank write bursts +system.physmem.perBankRdBursts::9 28576 # Per bank write bursts +system.physmem.perBankRdBursts::10 28034 # Per bank write bursts +system.physmem.perBankRdBursts::11 27899 # Per bank write bursts +system.physmem.perBankRdBursts::12 27884 # Per bank write bursts +system.physmem.perBankRdBursts::13 28245 # Per bank write bursts +system.physmem.perBankRdBursts::14 28268 # Per bank write bursts +system.physmem.perBankRdBursts::15 28092 # Per bank write bursts +system.physmem.perBankWrBursts::0 8222 # Per bank write bursts +system.physmem.perBankWrBursts::1 7571 # Per bank write bursts +system.physmem.perBankWrBursts::2 7821 # Per bank write bursts +system.physmem.perBankWrBursts::3 7782 # Per bank write bursts +system.physmem.perBankWrBursts::4 7428 # Per bank write bursts +system.physmem.perBankWrBursts::5 7859 # Per bank write bursts +system.physmem.perBankWrBursts::6 7924 # Per bank write bursts +system.physmem.perBankWrBursts::7 7992 # Per bank write bursts +system.physmem.perBankWrBursts::8 7912 # Per bank write bursts +system.physmem.perBankWrBursts::9 7920 # Per bank write bursts +system.physmem.perBankWrBursts::10 7418 # Per bank write bursts +system.physmem.perBankWrBursts::11 7297 # Per bank write bursts +system.physmem.perBankWrBursts::12 7319 # Per bank write bursts +system.physmem.perBankWrBursts::13 7829 # Per bank write bursts +system.physmem.perBankWrBursts::14 7922 # Per bank write bursts +system.physmem.perBankWrBursts::15 7585 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1904663535000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1903333578000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 450624 # Read request sizes (log2) +system.physmem.readPktSize::6 452659 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122060 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 322714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123811 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 323009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 959 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -141,458 +141,451 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 46334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 790.933310 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.010271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1879.334417 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16305 35.19% 35.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6714 14.49% 49.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4888 10.55% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2813 6.07% 66.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1747 3.77% 70.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1443 3.11% 73.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1071 2.31% 75.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 878 1.89% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 653 1.41% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 584 1.26% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 640 1.38% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 489 1.06% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 295 0.64% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 293 0.63% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 217 0.47% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 380 0.82% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 150 0.32% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 199 0.43% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 125 0.27% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 141 0.30% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 397 0.86% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 230 0.50% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 690 1.49% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 125 0.27% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 87 0.19% 89.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 68 0.15% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 129 0.28% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 56 0.12% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 91 0.20% 90.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 45 0.10% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 78 0.17% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 66 0.14% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 92 0.20% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 29 0.06% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 29 0.06% 91.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 53 0.11% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 51 0.11% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 26 0.06% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 27 0.06% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 25 0.05% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 53 0.11% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 52 0.11% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 16 0.03% 92.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 30 0.06% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 33 0.07% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 86 0.19% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 27 0.06% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 14 0.03% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 51 0.11% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 26 0.06% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 25 0.05% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 50 0.11% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 28 0.06% 93.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 42 0.09% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 39 0.08% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 87 0.19% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 25 0.05% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 14 0.03% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 55 0.12% 94.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 50 0.11% 94.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 21 0.05% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 49 0.11% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 50 0.11% 94.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 11 0.02% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 26 0.06% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 86 0.19% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 38 0.08% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 26 0.06% 95.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 54 0.12% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 52 0.11% 95.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 22 0.05% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 49 0.11% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 39 0.08% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 31 0.07% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 44 0.09% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 9 0.02% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 51 0.11% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 50 0.11% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 23 0.05% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 20 0.04% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 23 0.05% 97.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 51 0.11% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 49 0.11% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 7 0.02% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 28 0.06% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 86 0.19% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 45 0.10% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 319 0.69% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 8 0.02% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 15 0.03% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 7 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 2 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-system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.50% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::15360-15363 38 0.08% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 173 0.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 46334 # Bytes accessed per row activation -system.physmem.totQLat 8608105750 # Total ticks spent queuing -system.physmem.totMemAccLat 16109367000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2252845000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5248416250 # Total ticks spent accessing banks -system.physmem.avgQLat 19104.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11648.42 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 39 0.08% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 175 0.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47120 # Bytes accessed per row activation +system.physmem.totQLat 8783315250 # Total ticks spent queuing +system.physmem.totMemAccLat 16310447750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2263000000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5264132500 # Total ticks spent accessing banks +system.physmem.avgQLat 19406.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11630.87 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35753.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 36037.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.81 # Average write queue length when enqueuing -system.physmem.readRowHits 429097 # Number of row buffer hits during reads -system.physmem.writeRowHits 97193 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes -system.physmem.avgGap 3325854.28 # Average gap between requests -system.physmem.pageHitRate 91.91 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing +system.physmem.readRowHits 430734 # Number of row buffer hits during reads +system.physmem.writeRowHits 98547 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.59 # Row buffer hit rate for writes +system.physmem.avgGap 3301704.47 # Average gap between requests +system.physmem.pageHitRate 91.82 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19299112 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296504 # Transaction distribution -system.membus.trans_dist::ReadResp 296255 # Transaction distribution -system.membus.trans_dist::WriteReq 12358 # Transaction distribution -system.membus.trans_dist::WriteResp 12358 # Transaction distribution -system.membus.trans_dist::Writeback 122060 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5288 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1522 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3409 # Transaction distribution -system.membus.trans_dist::ReadExReq 162296 # Transaction distribution -system.membus.trans_dist::ReadExResp 162161 # Transaction distribution +system.membus.throughput 19439855 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296479 # Transaction distribution +system.membus.trans_dist::ReadResp 296230 # Transaction distribution +system.membus.trans_dist::WriteReq 12351 # Transaction distribution +system.membus.trans_dist::WriteResp 12351 # Transaction distribution +system.membus.trans_dist::Writeback 123811 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5304 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1475 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3474 # Transaction distribution +system.membus.trans_dist::ReadExReq 164353 # Transaction distribution +system.membus.trans_dist::ReadExResp 164224 # Transaction distribution system.membus.trans_dist::BadAddressError 249 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 909601 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 915454 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 949201 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124660 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124660 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1073861 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68234 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31344192 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31412426 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5307584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36720010 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36720010 # Total data (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 955046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1079702 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68202 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31586624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31654826 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5307456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36962282 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36962282 # Total data (bytes) system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 36252500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1605524497 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1624596499 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 317500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3818350840 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3836772510 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376337493 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 343738 # number of replacements -system.l2c.tags.tagsinuse 65291.635140 # Cycle average of tags in use -system.l2c.tags.total_refs 2609074 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 408707 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.383727 # Average number of references to valid blocks. +system.l2c.tags.replacements 345713 # number of replacements +system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use +system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410924 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.345923 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53622.087129 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4120.650208 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5604.001242 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1368.077401 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 576.819161 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.818208 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.085510 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.020875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008802 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 744945 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 568804 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 325372 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 253262 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1892383 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 840158 # number of Writeback hits -system.l2c.Writeback_hits::total 840158 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 143496 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47101 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 190597 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 744945 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 712300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 325372 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 300363 # number of demand (read+write) hits -system.l2c.demand_hits::total 2082980 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 744945 # number of overall hits -system.l2c.overall_hits::cpu0.data 712300 # number of overall hits -system.l2c.overall_hits::cpu1.inst 325372 # number of overall hits -system.l2c.overall_hits::cpu1.data 300363 # number of overall hits -system.l2c.overall_hits::total 2082980 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11483 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272043 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3807 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1819 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289152 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2542 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 549 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3091 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 55 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 155 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 106452 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14320 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120772 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11483 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 378495 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3807 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16139 # number of demand (read+write) misses -system.l2c.demand_misses::total 409924 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11483 # number of overall misses -system.l2c.overall_misses::cpu0.data 378495 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3807 # number of overall misses -system.l2c.overall_misses::cpu1.data 16139 # number of overall misses -system.l2c.overall_misses::total 409924 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 923162249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17695673499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 318789981 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 142364996 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19079990725 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 555479 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1281945 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1837424 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 201494 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 69497 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 270991 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8670131391 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1451250197 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10121381588 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 923162249 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26365804890 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 318789981 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1593615193 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29201372313 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 923162249 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26365804890 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 318789981 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1593615193 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29201372313 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 756428 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 840847 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 329179 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 255081 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2181535 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 840158 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 840158 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2683 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 636 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3319 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 90 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 131 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 221 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 249948 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 61421 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 311369 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 756428 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1090795 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 329179 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 316502 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2492904 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 756428 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1090795 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 329179 # number of overall (read+write) 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+system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses -system.iocache.demand_misses::total 41729 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses -system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21589383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21589383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12994516805 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12994516805 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13016106188 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13016106188 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13016106188 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13016106188 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21368383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21368383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13021515788 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13021515788 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13042884171 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13042884171 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13042884171 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13042884171 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -771,40 +764,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121973.915254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 121973.915254 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312729.033621 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312729.033621 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311919.916317 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311919.916317 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 404619 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122105.045714 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122105.045714 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 313378.797362 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 313378.797362 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 312576.609174 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 312576.609174 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 407057 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29217 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29358 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.848752 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.865284 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12384383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12384383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10832260819 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10832260819 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10844645202 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10844645202 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10844645202 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10844645202 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12267383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12267383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10859254806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10859254806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10871522189 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10871522189 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10871522189 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10871522189 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -813,14 +806,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69968.265537 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 69968.265537 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260691.683168 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260691.683168 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70099.331429 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70099.331429 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 261341.326675 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 261341.326675 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -834,35 +827,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 10889682 # Number of BP lookups -system.cpu0.branchPred.condPredicted 9229516 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 284462 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7161619 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4680131 # Number of BTB hits +system.cpu0.branchPred.lookups 11006012 # Number of BP lookups +system.cpu0.branchPred.condPredicted 9319545 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 291548 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7161716 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4729334 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.350181 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 674122 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 25966 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.036324 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 682987 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 26515 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7794998 # DTB read hits -system.cpu0.dtb.read_misses 29740 # DTB read misses -system.cpu0.dtb.read_acv 552 # DTB read access violations -system.cpu0.dtb.read_accesses 624038 # DTB read accesses -system.cpu0.dtb.write_hits 5176736 # DTB write hits -system.cpu0.dtb.write_misses 7776 # DTB write misses -system.cpu0.dtb.write_acv 327 # DTB write access violations -system.cpu0.dtb.write_accesses 207382 # DTB write accesses -system.cpu0.dtb.data_hits 12971734 # DTB hits -system.cpu0.dtb.data_misses 37516 # DTB misses -system.cpu0.dtb.data_acv 879 # DTB access violations -system.cpu0.dtb.data_accesses 831420 # DTB accesses -system.cpu0.itb.fetch_hits 929400 # ITB hits -system.cpu0.itb.fetch_misses 28175 # ITB misses -system.cpu0.itb.fetch_acv 908 # ITB acv -system.cpu0.itb.fetch_accesses 957575 # ITB accesses +system.cpu0.dtb.read_hits 7888949 # DTB read hits +system.cpu0.dtb.read_misses 30101 # DTB read misses +system.cpu0.dtb.read_acv 574 # DTB read access violations +system.cpu0.dtb.read_accesses 665608 # DTB read accesses +system.cpu0.dtb.write_hits 5247941 # DTB write hits +system.cpu0.dtb.write_misses 8093 # DTB write misses +system.cpu0.dtb.write_acv 365 # DTB write access violations +system.cpu0.dtb.write_accesses 232480 # DTB write accesses +system.cpu0.dtb.data_hits 13136890 # DTB hits +system.cpu0.dtb.data_misses 38194 # DTB misses +system.cpu0.dtb.data_acv 939 # DTB access violations +system.cpu0.dtb.data_accesses 898088 # DTB accesses +system.cpu0.itb.fetch_hits 973403 # ITB hits +system.cpu0.itb.fetch_misses 31216 # ITB misses +system.cpu0.itb.fetch_acv 1004 # ITB acv +system.cpu0.itb.fetch_accesses 1004619 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -875,269 +868,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 103787820 # number of cpu cycles simulated +system.cpu0.numCycles 104578589 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21704485 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 55964987 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 10889682 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5354253 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10541115 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1495269 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 32108430 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 196165 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 243475 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6808420 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 194219 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 65778101 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.850815 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.187217 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21960114 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 56555379 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11006012 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5412321 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10656012 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1518801 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32354382 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 30030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 204805 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 243991 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6896028 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 198863 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 66418859 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.851496 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.187669 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 55236986 83.97% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 687368 1.04% 85.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1350712 2.05% 87.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 596944 0.91% 87.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2343219 3.56% 91.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 450390 0.68% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 484863 0.74% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 769593 1.17% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3858026 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 55762847 83.96% 83.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 696881 1.05% 85.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1363707 2.05% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 607827 0.92% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2362378 3.56% 91.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 460793 0.69% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 493104 0.74% 92.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 775074 1.17% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3896248 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 65778101 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.104923 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.539225 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 22868260 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 31583202 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9551685 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 850413 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 924540 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 430365 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 30891 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54921627 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 95919 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 924540 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 23764379 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12229388 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16273784 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8983229 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3602779 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 51919548 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6908 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 427524 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1365609 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 34775855 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 63273064 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 63154051 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 110251 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30610760 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4165087 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1306243 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 192817 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9794386 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8157712 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5414054 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 996311 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 651476 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 46072688 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1607529 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 45052642 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 77910 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5101692 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2707567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1088536 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 65778101 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.684919 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328831 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 66418859 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.105242 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.540793 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23145338 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 31820288 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9657130 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 858074 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 938028 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 439220 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 31710 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 55497748 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 98418 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 938028 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24047696 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12280609 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16434779 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9089203 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3628542 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52477613 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6876 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 427894 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1374075 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 35152162 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 63950241 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 63830636 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 110747 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30925813 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4226341 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1321793 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 195129 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9844333 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8256385 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5476723 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1002198 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 667476 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 46574896 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1622063 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 45553168 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 69417 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5159281 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2712846 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1098313 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 66418859 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.685847 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329893 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 45611929 69.34% 69.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9242272 14.05% 83.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4206709 6.40% 89.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2691383 4.09% 93.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2059923 3.13% 97.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1077701 1.64% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 567124 0.86% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 276618 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 44442 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 46042875 69.32% 69.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9328009 14.04% 83.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4252197 6.40% 89.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2720710 4.10% 93.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2085310 3.14% 97.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1089347 1.64% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 576580 0.87% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 279468 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 44363 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 65778101 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 66418859 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 64943 10.84% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 279384 46.63% 57.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 254855 42.53% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65077 10.66% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 284948 46.66% 57.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 260601 42.68% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30907747 68.60% 68.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47065 0.10% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 14613 0.03% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8107891 18.00% 86.75% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5235503 11.62% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 734167 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 31229788 68.56% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47289 0.10% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14649 0.03% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8205422 18.01% 86.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5307142 11.65% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 743210 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 45052642 # Type of FU issued -system.cpu0.iq.rate 0.434084 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 599182 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013300 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 156086675 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 52562386 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44135345 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 473801 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 230205 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 223474 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 45400371 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 247676 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 493959 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 45553168 # Type of FU issued +system.cpu0.iq.rate 0.435588 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 610626 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013405 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 157729759 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 53136035 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44625486 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 475478 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 231159 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 224228 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 45911492 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 248517 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 497947 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 994643 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3486 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10933 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 382957 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1006840 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3517 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11189 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 378910 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13548 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 145981 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13584 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 146356 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 924540 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8545801 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 700799 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50460891 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 559365 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8157712 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5414054 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1419298 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 572111 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4914 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10933 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 138244 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 310094 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 448338 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 44721018 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7845228 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 331623 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 938028 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8572601 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 702117 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50999649 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 565079 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8256385 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5476723 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1432117 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 572819 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5269 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11189 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 141170 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 315582 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 456752 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 45215846 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7939970 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 337321 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2780674 # number of nop insts executed -system.cpu0.iew.exec_refs 13041346 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7066025 # Number of branches executed -system.cpu0.iew.exec_stores 5196118 # Number of stores executed -system.cpu0.iew.exec_rate 0.430889 # Inst execution rate -system.cpu0.iew.wb_sent 44442278 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44358819 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22095606 # num instructions producing a value -system.cpu0.iew.wb_consumers 29563187 # num instructions consuming a value +system.cpu0.iew.exec_nop 2802690 # number of nop insts executed +system.cpu0.iew.exec_refs 13207799 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7146234 # Number of branches executed +system.cpu0.iew.exec_stores 5267829 # Number of stores executed +system.cpu0.iew.exec_rate 0.432362 # Inst execution rate +system.cpu0.iew.wb_sent 44934571 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44849714 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22315831 # num instructions producing a value +system.cpu0.iew.wb_consumers 29845824 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.427399 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.747403 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.428861 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.747704 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5494607 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 518993 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 418437 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 64853561 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.691924 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608025 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5562563 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 523750 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 426483 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 65480831 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.692465 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608721 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 47955107 73.94% 73.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7091089 10.93% 84.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3807248 5.87% 90.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2121571 3.27% 94.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1151711 1.78% 95.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 474089 0.73% 96.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 405970 0.63% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 383893 0.59% 97.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1462883 2.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 48404249 73.92% 73.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7174588 10.96% 84.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3839849 5.86% 90.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2141053 3.27% 94.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1161993 1.77% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 481151 0.73% 96.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 411214 0.63% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 389126 0.59% 97.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1477608 2.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 64853561 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 44873722 # Number of instructions committed -system.cpu0.commit.committedOps 44873722 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 65480831 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 45343202 # Number of instructions committed +system.cpu0.commit.committedOps 45343202 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12194166 # Number of memory references committed -system.cpu0.commit.loads 7163069 # Number of loads committed -system.cpu0.commit.membars 173899 # Number of memory barriers committed -system.cpu0.commit.branches 6736138 # Number of branches committed -system.cpu0.commit.fp_insts 221634 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 41596674 # Number of committed integer instructions. -system.cpu0.commit.function_calls 557213 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1462883 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12347358 # Number of memory references committed +system.cpu0.commit.loads 7249545 # Number of loads committed +system.cpu0.commit.membars 175312 # Number of memory barriers committed +system.cpu0.commit.branches 6808554 # Number of branches committed +system.cpu0.commit.fp_insts 222342 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 42040123 # Number of committed integer instructions. +system.cpu0.commit.function_calls 564734 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1477608 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 113567039 # The number of ROB reads -system.cpu0.rob.rob_writes 101661188 # The number of ROB writes -system.cpu0.timesIdled 942687 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38009719 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3705537551 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 42330060 # Number of Instructions Simulated -system.cpu0.committedOps 42330060 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 42330060 # Number of Instructions Simulated -system.cpu0.cpi 2.451870 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.451870 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.407852 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.407852 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 58864464 # number of integer regfile reads -system.cpu0.int_regfile_writes 32110567 # number of integer regfile writes -system.cpu0.fp_regfile_reads 109878 # number of floating regfile reads -system.cpu0.fp_regfile_writes 110737 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1513799 # number of misc regfile reads -system.cpu0.misc_regfile_writes 739168 # number of misc regfile writes +system.cpu0.rob.rob_reads 114710793 # The number of ROB reads +system.cpu0.rob.rob_writes 102749676 # The number of ROB writes +system.cpu0.timesIdled 949561 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38159730 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3702093008 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 42781436 # Number of Instructions Simulated +system.cpu0.committedOps 42781436 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 42781436 # Number of Instructions Simulated +system.cpu0.cpi 2.444485 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.444485 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.409084 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.409084 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 59516377 # number of integer regfile reads +system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes +system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads +system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1526243 # number of misc regfile reads +system.cpu0.misc_regfile_writes 747832 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1169,49 +1162,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 112875870 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2213010 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2212746 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12358 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12358 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 840158 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5353 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1588 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6941 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 354001 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 312453 # Transaction distribution +system.toL2Bus.throughput 112873708 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2210500 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2210236 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 840492 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5351 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1545 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6896 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 353777 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 312228 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1512954 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2808902 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 658389 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 920655 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5900900 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48411392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 107554025 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21067456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 36346017 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 213378890 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 213368266 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1622464 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5059270351 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1532372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2827999 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 634560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 901176 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5896107 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49032512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 108336621 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20304832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 35573309 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 213247274 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 213236842 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1600000 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5059383343 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 733500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3408360184 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3452114362 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5017953643 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5048329138 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1482953497 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1429282335 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1519289016 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1486623569 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1433257 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7370 # Transaction distribution -system.iobus.trans_dist::ReadResp 7370 # Transaction distribution -system.iobus.trans_dist::WriteReq 53910 # Transaction distribution -system.iobus.trans_dist::WriteResp 53910 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10510 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1434231 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7371 # Transaction distribution +system.iobus.trans_dist::ReadResp 7371 # Transaction distribution +system.iobus.trans_dist::WriteReq 53903 # Transaction distribution +system.iobus.trans_dist::WriteResp 53903 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10490 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1222,12 +1215,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122560 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39094 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122548 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41960 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1238,14 +1231,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68234 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729874 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729874 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9865000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 68202 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729826 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729826 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9845000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1265,253 +1258,253 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377768695 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377802180 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26744000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26743000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42672507 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42660009 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 755849 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.693536 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6013634 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 756358 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.950777 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 765570 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.693534 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6090993 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 766079 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.950868 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693536 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693534 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6013634 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6013634 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6013634 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6013634 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6013634 # number of overall hits -system.cpu0.icache.overall_hits::total 6013634 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 794785 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 794785 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 794785 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 794785 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 794785 # number of overall misses -system.cpu0.icache.overall_misses::total 794785 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11289773018 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11289773018 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11289773018 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11289773018 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11289773018 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11289773018 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6808419 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6808419 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6808419 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6808419 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6808419 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6808419 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116736 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116736 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116736 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116736 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116736 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116736 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14204.813903 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14204.813903 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14204.813903 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14204.813903 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5327 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 6090993 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6090993 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6090993 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6090993 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6090993 # number of overall hits +system.cpu0.icache.overall_hits::total 6090993 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 805033 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 805033 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 805033 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 805033 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 805033 # number of overall misses +system.cpu0.icache.overall_misses::total 805033 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11432598915 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11432598915 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11432598915 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11432598915 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11432598915 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11432598915 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6896026 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6896026 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6896026 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6896026 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6896026 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6896026 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116739 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116739 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116739 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116739 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116739 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116739 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14201.404060 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14201.404060 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14201.404060 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14201.404060 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4227 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 138 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 41.944882 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.630435 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38259 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 38259 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 38259 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 38259 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 38259 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 38259 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 756526 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 756526 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 756526 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 756526 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 756526 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 756526 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9285394312 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9285394312 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9285394312 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9285394312 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9285394312 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9285394312 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111116 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.111116 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.111116 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12273.727951 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38794 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 38794 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 38794 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 38794 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 38794 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 38794 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 766239 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 766239 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 766239 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 766239 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 766239 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 766239 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9400829636 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9400829636 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9400829636 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9400829636 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9400829636 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9400829636 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111113 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.111113 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111113 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12268.795553 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1092682 # number of replacements -system.cpu0.dcache.tags.tagsinuse 465.850340 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9201265 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1093194 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.416864 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1099493 # number of replacements +system.cpu0.dcache.tags.tagsinuse 471.490981 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9327298 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1100005 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.479323 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 465.850340 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.909864 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.909864 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5673895 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5673895 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3199282 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3199282 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148885 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 148885 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172652 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 172652 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8873177 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8873177 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8873177 # number of overall hits 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misses -system.cpu0.dcache.overall_misses::total 2994753 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36556454998 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36556454998 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 72896722210 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 72896722210 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251362748 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 251362748 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4670052 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4670052 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 109453177208 # number of demand (read+write) miss cycles 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61.639068 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 117 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 588957 # number of writebacks -system.cpu0.dcache.writebacks::total 588957 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 514989 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 514989 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392541 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1392541 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3960 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3960 # number of LoadLockedReq MSHR hits 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MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1087223 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1087223 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1087223 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1087223 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24857542918 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24857542918 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10684541815 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10684541815 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 151212250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 151212250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3123948 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3123948 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35542084733 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35542084733 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35542084733 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35542084733 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 990981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 990981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668402499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668402499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2659383499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2659383499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118707 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118707 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052338 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052338 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.077101 # mshr miss rate for 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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42131.640168 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42131.640168 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11842.137207 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11842.137207 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4041.329884 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4041.329884 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall 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+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1930990 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1930990 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 837490 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 837490 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256456 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256456 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12810 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12810 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 764 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 764 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1093946 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1093946 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1093946 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1093946 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24898598196 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24898598196 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10973118276 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10973118276 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 152117754 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 152117754 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3219443 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3219443 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35871716472 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35871716472 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35871716472 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35871716472 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 993486001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 993486001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1673832998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1673832998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2667318999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2667318999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117783 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117783 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076170 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076170 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004359 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004359 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091006 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091006 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29730.024473 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29730.024473 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42787.527981 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42787.527981 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11874.922248 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.922248 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4213.930628 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4213.930628 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1519,35 +1512,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4005476 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3286567 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 126561 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2463252 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1409799 # Number of BTB hits +system.cpu1.branchPred.lookups 3875512 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3181518 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 119538 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2413999 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1363069 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.233243 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 290076 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 11654 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 56.465185 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 281270 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 11131 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2861061 # DTB read hits -system.cpu1.dtb.read_misses 13171 # DTB read misses -system.cpu1.dtb.read_acv 26 # DTB read access violations -system.cpu1.dtb.read_accesses 327320 # DTB read accesses -system.cpu1.dtb.write_hits 1771736 # DTB write hits -system.cpu1.dtb.write_misses 2413 # DTB write misses -system.cpu1.dtb.write_acv 61 # DTB write access violations -system.cpu1.dtb.write_accesses 133954 # DTB write accesses -system.cpu1.dtb.data_hits 4632797 # DTB hits -system.cpu1.dtb.data_misses 15584 # DTB misses -system.cpu1.dtb.data_acv 87 # DTB access violations -system.cpu1.dtb.data_accesses 461274 # DTB accesses -system.cpu1.itb.fetch_hits 484886 # ITB hits -system.cpu1.itb.fetch_misses 6783 # ITB misses -system.cpu1.itb.fetch_acv 213 # ITB acv -system.cpu1.itb.fetch_accesses 491669 # ITB accesses +system.cpu1.dtb.read_hits 2756439 # DTB read hits +system.cpu1.dtb.read_misses 11971 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 281635 # DTB read accesses +system.cpu1.dtb.write_hits 1697476 # DTB write hits +system.cpu1.dtb.write_misses 2261 # DTB write misses +system.cpu1.dtb.write_acv 35 # DTB write access violations +system.cpu1.dtb.write_accesses 106637 # DTB write accesses +system.cpu1.dtb.data_hits 4453915 # DTB hits +system.cpu1.dtb.data_misses 14232 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 388272 # DTB accesses +system.cpu1.itb.fetch_hits 435796 # ITB hits +system.cpu1.itb.fetch_misses 5916 # ITB misses +system.cpu1.itb.fetch_acv 132 # ITB acv +system.cpu1.itb.fetch_accesses 441712 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1560,508 +1553,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 26365345 # number of cpu cycles simulated +system.cpu1.numCycles 25703316 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8788859 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 19229785 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4005476 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1699875 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3495206 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 620790 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 10702778 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65519 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 161249 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2272198 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 84032 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 23644267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.813296 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.175765 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8513027 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 18550498 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3875512 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1644339 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3370867 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 594419 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 10509044 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 56236 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 158916 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 118 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2181303 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 77306 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 23021613 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.805786 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.167146 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20149061 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 201364 0.85% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 434975 1.84% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 271433 1.15% 89.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 534220 2.26% 91.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 181805 0.77% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 209247 0.88% 92.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 254511 1.08% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1407651 5.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 19650746 85.36% 85.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 192109 0.83% 86.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 424155 1.84% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 258878 1.12% 89.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 512227 2.22% 91.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 176251 0.77% 92.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 202668 0.88% 93.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 249358 1.08% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1355221 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 23644267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.151922 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.729358 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8879389 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 10928600 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3243065 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 199967 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 393245 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 183870 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 12999 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 18844715 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 38529 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 393245 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 9206755 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3122476 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6754638 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 3034107 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1133044 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 17630254 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 270 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 267231 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 248854 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 11666322 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 21081705 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 21016911 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58919 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 9884504 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1781818 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 561630 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 56869 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3357033 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3030330 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1870850 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 319037 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 184061 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 15497472 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 666578 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 15021403 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 38685 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2244261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1133404 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 478003 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 23644267 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.635308 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.316901 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 23021613 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.150779 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.721716 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8599650 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 10723354 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3129491 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 191921 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 377196 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 176309 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 12258 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 18185515 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 36387 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 377196 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8917984 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3106321 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6595327 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2921217 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1103566 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 17011608 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 267059 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 236234 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 11254383 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 20310939 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 20246817 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58360 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9542826 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1711557 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 544600 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 54677 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3272980 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2918733 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1792509 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 312208 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 170960 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 14943030 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 650638 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 14484391 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 37394 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2166782 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1088105 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 467114 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 23021613 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.629165 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.310842 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 17155384 72.56% 72.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2869349 12.14% 84.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1269974 5.37% 90.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 909350 3.85% 93.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 787037 3.33% 97.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 325991 1.38% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 202457 0.86% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 106589 0.45% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 18136 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 16750827 72.76% 72.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2784830 12.10% 84.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1224236 5.32% 90.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 874900 3.80% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 759442 3.30% 97.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 313710 1.36% 98.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 192948 0.84% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 103377 0.45% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 17343 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 23644267 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 23021613 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 18902 7.17% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 136410 51.75% 58.92% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 108303 41.08% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 19111 7.55% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 130840 51.68% 59.23% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 103199 40.77% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 9862540 65.66% 65.68% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 23545 0.16% 65.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11158 0.07% 65.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2986833 19.88% 85.81% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1799237 11.98% 97.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 332801 2.22% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9521262 65.73% 65.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 23052 0.16% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11116 0.08% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2876494 19.86% 85.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1724250 11.90% 97.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 322940 2.23% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 15021403 # Type of FU issued -system.cpu1.iq.rate 0.569740 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 263615 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017549 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 53759316 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 18299643 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 14636122 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 230057 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 112007 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 108764 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 15161393 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 120099 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 139894 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 14484391 # Type of FU issued +system.cpu1.iq.rate 0.563522 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 253150 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017477 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 52052620 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 17652734 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 14115090 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 228319 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 110924 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 107745 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 14614655 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 119368 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 134347 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 437460 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1072 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3446 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 176357 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 418294 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 981 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3304 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 169372 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5243 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 21515 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5236 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 20861 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 393245 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2412385 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 142199 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 17062579 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 198140 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3030330 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1870850 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 597759 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52684 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2595 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3446 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 61011 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 139338 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 200349 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 14878419 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2882425 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 142984 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 377196 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2407064 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 140680 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 16469424 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 189598 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2918733 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1792509 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 583051 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52184 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2431 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3304 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 57543 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133828 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 191371 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 14348807 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2776029 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 135584 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 898529 # number of nop insts executed -system.cpu1.iew.exec_refs 4662637 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2338044 # Number of branches executed -system.cpu1.iew.exec_stores 1780212 # Number of stores executed -system.cpu1.iew.exec_rate 0.564317 # Inst execution rate -system.cpu1.iew.wb_sent 14784457 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 14744886 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 7139948 # num instructions producing a value -system.cpu1.iew.wb_consumers 10043269 # num instructions consuming a value +system.cpu1.iew.exec_nop 875756 # number of nop insts executed +system.cpu1.iew.exec_refs 4481633 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2254475 # Number of branches executed +system.cpu1.iew.exec_stores 1705604 # Number of stores executed +system.cpu1.iew.exec_rate 0.558247 # Inst execution rate +system.cpu1.iew.wb_sent 14259530 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 14222835 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 6903248 # num instructions producing a value +system.cpu1.iew.wb_consumers 9726426 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.559253 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710919 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.553346 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709741 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2396118 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 188575 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 186792 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 23251022 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.628108 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.559407 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2312839 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 183524 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 178531 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 22644417 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.622505 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.551942 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 17812881 76.61% 76.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2343231 10.08% 86.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1160626 4.99% 91.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 598215 2.57% 94.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 379804 1.63% 95.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 180518 0.78% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 173796 0.75% 97.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 135154 0.58% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 466797 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 17386197 76.78% 76.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2263939 10.00% 86.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1130304 4.99% 91.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 578693 2.56% 94.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 365284 1.61% 95.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 174241 0.77% 96.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 166825 0.74% 97.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 129123 0.57% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 449811 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 23251022 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 14604164 # Number of instructions committed -system.cpu1.commit.committedOps 14604164 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 22644417 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 14096266 # Number of instructions committed +system.cpu1.commit.committedOps 14096266 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4287363 # Number of memory references committed -system.cpu1.commit.loads 2592870 # Number of loads committed -system.cpu1.commit.membars 62980 # Number of memory barriers committed -system.cpu1.commit.branches 2183593 # Number of branches committed -system.cpu1.commit.fp_insts 107360 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 13494360 # Number of committed integer instructions. -system.cpu1.commit.function_calls 233831 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 466797 # number cycles where commit BW limit reached +system.cpu1.commit.refs 4123576 # Number of memory references committed +system.cpu1.commit.loads 2500439 # Number of loads committed +system.cpu1.commit.membars 61456 # Number of memory barriers committed +system.cpu1.commit.branches 2105755 # Number of branches committed +system.cpu1.commit.fp_insts 106451 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 13014804 # Number of committed integer instructions. +system.cpu1.commit.function_calls 225813 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 449811 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 39695803 # The number of ROB reads -system.cpu1.rob.rob_writes 34392702 # The number of ROB writes -system.cpu1.timesIdled 272923 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2721078 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3782349185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 13810279 # Number of Instructions Simulated -system.cpu1.committedOps 13810279 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 13810279 # Number of Instructions Simulated -system.cpu1.cpi 1.909110 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.909110 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.523804 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.523804 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 19249115 # number of integer regfile reads -system.cpu1.int_regfile_writes 10558811 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58616 # number of floating regfile reads -system.cpu1.fp_regfile_writes 58623 # number of floating regfile writes -system.cpu1.misc_regfile_reads 636847 # number of misc regfile reads -system.cpu1.misc_regfile_writes 274262 # number of misc regfile writes -system.cpu1.icache.tags.replacements 328629 # number of replacements -system.cpu1.icache.tags.tagsinuse 504.249918 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1927863 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 329141 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.857256 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 49124844500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.249918 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984863 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.984863 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1927863 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1927863 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1927863 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1927863 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1927863 # number of overall hits -system.cpu1.icache.overall_hits::total 1927863 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 344335 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 344335 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 344335 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 344335 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 344335 # number of overall misses -system.cpu1.icache.overall_misses::total 344335 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4815194513 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4815194513 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4815194513 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4815194513 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4815194513 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4815194513 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2272198 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2272198 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2272198 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2272198 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2272198 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2272198 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151543 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.151543 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151543 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.151543 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151543 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.151543 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13984.040289 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13984.040289 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13984.040289 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13984.040289 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1435 # number of cycles access was blocked +system.cpu1.rob.rob_reads 38521772 # The number of ROB reads +system.cpu1.rob.rob_writes 33194220 # The number of ROB writes +system.cpu1.timesIdled 266846 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2681703 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3780938744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13322175 # Number of Instructions Simulated +system.cpu1.committedOps 13322175 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 13322175 # Number of Instructions Simulated +system.cpu1.cpi 1.929363 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.929363 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.518306 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.518306 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 18552962 # number of integer regfile reads +system.cpu1.int_regfile_writes 10191479 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58039 # number of floating regfile reads +system.cpu1.fp_regfile_writes 58174 # number of floating regfile writes +system.cpu1.misc_regfile_reads 621722 # number of misc regfile reads +system.cpu1.misc_regfile_writes 265027 # number of misc regfile writes +system.cpu1.icache.tags.replacements 316719 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.225697 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1849767 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 317231 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.830978 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 49140510500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.225697 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984816 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.984816 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1849767 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1849767 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1849767 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1849767 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1849767 # number of overall hits +system.cpu1.icache.overall_hits::total 1849767 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 331536 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 331536 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 331536 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 331536 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 331536 # number of overall misses +system.cpu1.icache.overall_misses::total 331536 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4647513106 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4647513106 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4647513106 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4647513106 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4647513106 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4647513106 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2181303 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2181303 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2181303 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2181303 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2181303 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2181303 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151990 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.151990 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151990 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.151990 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151990 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.151990 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14018.125048 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14018.125048 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14018.125048 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14018.125048 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1365 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 51 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 71 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 28.137255 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.225352 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15125 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 15125 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 15125 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 15125 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 15125 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 15125 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329210 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 329210 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 329210 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 329210 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 329210 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 329210 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3979739752 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3979739752 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3979739752 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3979739752 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3979739752 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3979739752 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.144886 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.144886 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.144886 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12088.757182 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14239 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 14239 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 14239 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 14239 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 14239 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 14239 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317297 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 317297 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 317297 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 317297 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 317297 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 317297 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3842042413 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3842042413 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3842042413 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3842042413 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3842042413 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3842042413 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145462 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.145462 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.145462 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12108.662903 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 330658 # number of replacements -system.cpu1.dcache.tags.tagsinuse 495.877996 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3531981 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 331060 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 10.668704 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 42038170500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.877996 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968512 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.968512 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2174883 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2174883 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1270139 # number of WriteReq hits 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13842081157 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 13842081157 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 114418247 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 114418247 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5712098 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5712098 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 21235620880 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 21235620880 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 21235620880 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 21235620880 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2653820 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2653820 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1640098 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1640098 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 51229 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 51229 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 47070 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 47070 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4293918 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4293918 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4293918 # 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-system.cpu1.dcache.demand_miss_rate::total 0.197697 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197697 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.197697 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15437.395154 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15437.395154 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37415.176160 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37415.176160 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.225391 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14311.225391 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7008.709202 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7008.709202 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 25015.574205 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 25015.574205 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 432228 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 323504 # number of replacements +system.cpu1.dcache.tags.tagsinuse 495.920224 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3389718 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 323845 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 10.467100 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 42037852500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.920224 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968594 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.968594 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2089496 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2089496 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1222054 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1222054 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 41428 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 41428 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44398 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 44398 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3311550 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3311550 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3311550 # number of overall hits +system.cpu1.dcache.overall_hits::total 3311550 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 467553 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 467553 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 348721 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 348721 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7730 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7730 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 782 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 782 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 816274 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 816274 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 816274 # number of overall misses +system.cpu1.dcache.overall_misses::total 816274 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7286969700 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 7286969700 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13547153677 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13547153677 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 112298247 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 112298247 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5736606 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5736606 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 20834123377 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 20834123377 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 20834123377 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 20834123377 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2557049 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2557049 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1570775 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1570775 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 49158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 49158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 45180 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 45180 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4127824 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4127824 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4127824 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4127824 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.182849 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.182849 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222006 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.222006 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157248 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157248 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017309 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017309 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197749 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.197749 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197749 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.197749 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.334069 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.334069 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38848.115476 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 38848.115476 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14527.586934 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14527.586934 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7335.813299 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7335.813299 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25523.443570 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 25523.443570 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 423453 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 7570 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7447 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57.097490 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.862226 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 251201 # number of writebacks -system.cpu1.dcache.writebacks::total 251201 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211025 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 211025 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306586 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 306586 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1580 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1580 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 517611 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 517611 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 517611 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 517611 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267912 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 267912 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 63373 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 63373 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6415 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6415 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 815 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 815 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 331285 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 331285 # number of demand (read+write) MSHR misses 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number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5486449851 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5486449851 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5486449851 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5486449851 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491833500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491833500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943255503 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 943255503 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1435089003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1435089003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100953 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.100953 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.125222 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.125222 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017315 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017315 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.077152 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.077152 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12758.929059 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12758.929059 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32635.028309 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32635.028309 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11107.327046 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11107.327046 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5008.468712 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5008.468712 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 245774 # number of writebacks +system.cpu1.dcache.writebacks::total 245774 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203756 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 203756 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 288423 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 288423 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1420 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1420 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 492179 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 492179 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 492179 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 492179 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 263797 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 263797 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 60298 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 60298 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6310 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6310 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 781 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 781 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 324095 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 324095 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 324095 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 324095 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3377520942 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3377520942 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032860866 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2032860866 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70443003 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70443003 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174394 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174394 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5410381808 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5410381808 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5410381808 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5410381808 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 489946000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 489946000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 936242002 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 936242002 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1426188002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1426188002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.103165 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.103165 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038387 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038387 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017286 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017286 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.078515 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.078515 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.485036 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12803.485036 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33713.570367 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33713.570367 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11163.708875 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11163.708875 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.934699 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.934699 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2070,170 +2063,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4829 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164539 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56531 39.74% 39.74% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 39.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.35% 41.18% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.20% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 83653 58.80% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 142256 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55584 49.09% 49.09% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.70% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55568 49.08% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113224 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866804619500 98.01% 98.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62415000 0.00% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 563852000 0.03% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8731500 0.00% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37224635500 1.95% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1904664253500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983248 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 166329 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 57049 39.81% 39.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 39.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.34% 41.24% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 84196 58.75% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 143316 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56102 49.10% 49.10% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.68% 50.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56086 49.09% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114259 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865433154000 98.01% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62620000 0.00% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 558222500 0.03% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8649500 0.00% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37274722500 1.96% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903337368500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983400 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.664268 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.795917 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed -system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed -system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed -system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed -system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 202 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.666136 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.797252 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed +system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 108 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wripir 104 0.07% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2969 1.98% 2.05% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed -system.cpu0.kern.callpal::swpipl 135909 90.65% 92.74% # number of callpals executed -system.cpu0.kern.callpal::rdps 6127 4.09% 96.83% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.83% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.83% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.83% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.84% # number of callpals executed -system.cpu0.kern.callpal::rti 4274 2.85% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.22% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149930 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6311 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3010 1.99% 2.06% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.10% # number of callpals executed +system.cpu0.kern.callpal::swpipl 136886 90.50% 92.60% # number of callpals executed +system.cpu0.kern.callpal::rdps 6293 4.16% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.77% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rti 4358 2.88% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 151247 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6436 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1257 -system.cpu0.kern.mode_good::user 1258 +system.cpu0.kern.mode_good::kernel 1342 +system.cpu0.kern.mode_good::user 1343 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.199176 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.208515 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.332276 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1902741106000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1923139500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.345160 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901289587500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2047773000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2970 # number of times the context was actually changed +system.cpu0.kern.swap_context 3011 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3864 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 73072 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 25114 39.08% 39.08% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 2.99% 42.08% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 108 0.17% 42.25% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 37111 57.75% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 64257 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 24684 48.12% 48.12% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 3.75% 51.88% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 108 0.21% 52.09% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 24576 47.91% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 51292 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870089135500 98.20% 98.20% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533638000 0.03% 98.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 50840000 0.00% 98.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33685568500 1.77% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1904359182000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.982878 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3850 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 71149 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 24567 38.92% 38.92% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 3.05% 41.97% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.16% 42.13% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 36529 57.87% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 63123 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 24137 48.08% 48.08% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 3.83% 51.92% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.21% 52.12% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24033 47.88% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 50197 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1869107624500 98.20% 98.20% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533184500 0.03% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 48972500 0.00% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33633158500 1.77% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903322940000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.982497 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.662230 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.798232 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed -system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed -system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed -system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed -system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed -system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed -system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 124 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.657916 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.795225 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed +system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed +system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1277 1.92% 1.95% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 1.96% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 1.97% # number of callpals executed -system.cpu1.kern.callpal::swpipl 59282 89.28% 91.25% # number of callpals executed -system.cpu1.kern.callpal::rdps 2633 3.97% 95.21% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.21% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.22% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 95.22% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.23% # number of callpals executed -system.cpu1.kern.callpal::rti 2942 4.43% 99.66% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.28% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1228 1.89% 1.92% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 1.92% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.93% # number of callpals executed +system.cpu1.kern.callpal::swpipl 58251 89.62% 91.55% # number of callpals executed +system.cpu1.kern.callpal::rdps 2464 3.79% 95.34% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.34% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.35% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.35% # number of callpals executed +system.cpu1.kern.callpal::rti 2844 4.38% 99.73% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.20% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 66403 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1747 # number of protection mode switches -system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2062 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 557 -system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 69 -system.cpu1.kern.mode_switch_good::kernel 0.318832 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 65000 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1608 # number of protection mode switches +system.cpu1.kern.mode_switch::user 397 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 463 +system.cpu1.kern.mode_good::user 397 +system.cpu1.kern.mode_good::idle 66 +system.cpu1.kern.mode_switch_good::kernel 0.287935 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.033463 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.259251 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 38709369000 2.03% 2.03% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 835914500 0.04% 2.08% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1864803541000 97.92% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1278 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.228135 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 38501499500 2.02% 2.02% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 724848000 0.04% 2.06% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1863406690000 97.94% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1229 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 4bc22a482..275c9f168 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -79,6 +84,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -143,6 +150,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -158,6 +166,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -180,26 +189,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -208,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -226,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -250,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -274,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -286,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -412,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -424,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -442,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -456,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -478,17 +534,21 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -497,6 +557,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -519,12 +580,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -534,10 +597,12 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -545,19 +610,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -565,28 +633,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -600,6 +673,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -622,6 +696,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -629,6 +704,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -640,6 +716,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -666,6 +743,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -677,29 +755,35 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -708,6 +792,7 @@ port=3456 [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -716,6 +801,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -726,6 +812,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -754,6 +841,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -763,8 +851,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -781,6 +901,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -804,6 +925,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -821,6 +943,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -838,6 +961,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -855,6 +979,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -872,6 +997,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -889,6 +1015,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -906,6 +1033,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -923,6 +1051,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -940,6 +1069,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -957,6 +1087,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -974,6 +1105,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -991,6 +1123,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -1008,6 +1141,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -1025,6 +1159,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -1042,6 +1177,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -1059,6 +1195,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -1076,6 +1213,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -1093,6 +1231,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -1110,6 +1249,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -1128,6 +1268,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -1155,6 +1296,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1164,8 +1306,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1177,6 +1351,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -1191,6 +1366,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -1203,6 +1379,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -1213,6 +1390,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -1223,6 +1401,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1232,5 +1411,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index cb131fc03..c08f75535 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,126 +1,126 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.860198 # Number of seconds simulated -sim_ticks 1860197608000 # Number of ticks simulated -final_tick 1860197608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1860197780500 # Number of ticks simulated +final_tick 1860197780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128608 # Simulator instruction rate (inst/s) -host_op_rate 128608 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4515644283 # Simulator tick rate (ticks/s) -host_mem_usage 336512 # Number of bytes of host memory used -host_seconds 411.95 # Real time elapsed on the host -sim_insts 52979573 # Number of instructions simulated -sim_ops 52979573 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879808 # Number of bytes read from this memory +host_inst_rate 103834 # Simulator instruction rate (inst/s) +host_op_rate 103834 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3645751305 # Simulator tick rate (ticks/s) +host_mem_usage 355004 # Number of bytes of host memory used +host_seconds 510.24 # Real time elapsed on the host +sim_insts 52979882 # Number of instructions simulated +sim_ops 52979882 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24878976 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516672 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15071 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388747 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28495232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7515456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388734 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445260 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117448 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117448 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13374820 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 445238 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117429 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117429 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374371 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15319147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13374820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 15318388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374371 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19359939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445260 # Number of read requests accepted -system.physmem.writeReqs 117448 # Number of write requests accepted -system.physmem.readBursts 445260 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117448 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28493888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue -system.physmem.bytesWritten 7515904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28496640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7516672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 19358526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445238 # Number of read requests accepted +system.physmem.writeReqs 117429 # Number of write requests accepted +system.physmem.readBursts 445238 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117429 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28492032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3200 # Total number of bytes read from write queue +system.physmem.bytesWritten 7514752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28495232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7515456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 177 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 179 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 28229 # Per bank write bursts system.physmem.perBankRdBursts::1 27970 # Per bank write bursts -system.physmem.perBankRdBursts::2 28438 # Per bank write bursts -system.physmem.perBankRdBursts::3 28034 # Per bank write bursts -system.physmem.perBankRdBursts::4 27800 # Per bank write bursts -system.physmem.perBankRdBursts::5 27233 # Per bank write bursts +system.physmem.perBankRdBursts::2 28433 # Per bank write bursts +system.physmem.perBankRdBursts::3 28029 # Per bank write bursts +system.physmem.perBankRdBursts::4 27802 # Per bank write bursts +system.physmem.perBankRdBursts::5 27222 # Per bank write bursts system.physmem.perBankRdBursts::6 27248 # Per bank write bursts -system.physmem.perBankRdBursts::7 27300 # Per bank write bursts -system.physmem.perBankRdBursts::8 27656 # Per bank write bursts -system.physmem.perBankRdBursts::9 27404 # Per bank write bursts -system.physmem.perBankRdBursts::10 27929 # Per bank write bursts -system.physmem.perBankRdBursts::11 27540 # Per bank write bursts -system.physmem.perBankRdBursts::12 27555 # Per bank write bursts -system.physmem.perBankRdBursts::13 28228 # Per bank write bursts -system.physmem.perBankRdBursts::14 28334 # Per bank write bursts -system.physmem.perBankRdBursts::15 28319 # Per bank write bursts -system.physmem.perBankWrBursts::0 7929 # Per bank write bursts -system.physmem.perBankWrBursts::1 7498 # Per bank write bursts -system.physmem.perBankWrBursts::2 7947 # Per bank write bursts +system.physmem.perBankRdBursts::7 27296 # Per bank write bursts +system.physmem.perBankRdBursts::8 27665 # Per bank write bursts +system.physmem.perBankRdBursts::9 27395 # Per bank write bursts +system.physmem.perBankRdBursts::10 27922 # Per bank write bursts +system.physmem.perBankRdBursts::11 27539 # Per bank write bursts +system.physmem.perBankRdBursts::12 27561 # Per bank write bursts +system.physmem.perBankRdBursts::13 28227 # Per bank write bursts +system.physmem.perBankRdBursts::14 28327 # Per bank write bursts +system.physmem.perBankRdBursts::15 28323 # Per bank write bursts +system.physmem.perBankWrBursts::0 7932 # Per bank write bursts +system.physmem.perBankWrBursts::1 7497 # Per bank write bursts +system.physmem.perBankWrBursts::2 7944 # Per bank write bursts system.physmem.perBankWrBursts::3 7517 # Per bank write bursts -system.physmem.perBankWrBursts::4 7338 # Per bank write bursts -system.physmem.perBankWrBursts::5 6689 # Per bank write bursts -system.physmem.perBankWrBursts::6 6763 # Per bank write bursts -system.physmem.perBankWrBursts::7 6689 # Per bank write bursts -system.physmem.perBankWrBursts::8 7098 # Per bank write bursts -system.physmem.perBankWrBursts::9 6803 # Per bank write bursts -system.physmem.perBankWrBursts::10 7320 # Per bank write bursts -system.physmem.perBankWrBursts::11 6984 # Per bank write bursts -system.physmem.perBankWrBursts::12 7119 # Per bank write bursts -system.physmem.perBankWrBursts::13 7873 # Per bank write bursts -system.physmem.perBankWrBursts::14 8054 # Per bank write bursts -system.physmem.perBankWrBursts::15 7815 # Per bank write bursts +system.physmem.perBankWrBursts::4 7343 # Per bank write bursts +system.physmem.perBankWrBursts::5 6680 # Per bank write bursts +system.physmem.perBankWrBursts::6 6761 # Per bank write bursts +system.physmem.perBankWrBursts::7 6683 # Per bank write bursts +system.physmem.perBankWrBursts::8 7104 # Per bank write bursts +system.physmem.perBankWrBursts::9 6801 # Per bank write bursts +system.physmem.perBankWrBursts::10 7313 # Per bank write bursts +system.physmem.perBankWrBursts::11 6981 # Per bank write bursts +system.physmem.perBankWrBursts::12 7123 # Per bank write bursts +system.physmem.perBankWrBursts::13 7875 # Per bank write bursts +system.physmem.perBankWrBursts::14 8050 # Per bank write bursts +system.physmem.perBankWrBursts::15 7814 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 1860192151000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1860192344000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445260 # Read request sizes (log2) +system.physmem.readPktSize::6 445238 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117448 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 332300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20080 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117429 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 332275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19911 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -131,226 +131,229 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 43193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 833.653601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 238.014185 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1939.409877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14703 34.04% 34.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6277 14.53% 48.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4438 10.27% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2692 6.23% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1642 3.80% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1371 3.17% 72.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 939 2.17% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 792 1.83% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 658 1.52% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 515 1.19% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 623 1.44% 80.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 600 1.39% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 275 0.64% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 275 0.64% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 263 0.61% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 360 0.83% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 192 0.44% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 168 0.39% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 100 0.23% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 208 0.48% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 111 0.26% 86.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 353 0.82% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 185 0.43% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 668 1.55% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 85 0.20% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 47 0.11% 89.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 186 0.43% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 74 0.17% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 80 0.19% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 97 0.22% 90.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 19 0.04% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 108 0.25% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 28 0.06% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 15 0.03% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.00% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 16 0.04% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.00% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 24 0.06% 91.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 101 0.23% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 13 0.03% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 66 0.15% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 39 0.09% 91.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 82 0.19% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 66 0.15% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 13 0.03% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 95 0.22% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 10 0.02% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 3 0.01% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 24 0.06% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 91 0.21% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 11 0.03% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 39 0.09% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 79 0.18% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 94 0.22% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 22 0.05% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 12 0.03% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 4 0.01% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 12 0.03% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 13 0.03% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 67 0.16% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 68 0.16% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 99 0.23% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 11 0.03% 95.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 14 0.03% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 83 0.19% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 39 0.09% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 81 0.19% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 67 0.16% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 13 0.03% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 21 0.05% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 3 0.01% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 24 0.06% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 13 0.03% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 81 0.19% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 309 0.72% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 16 0.04% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 4 0.01% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 3 0.01% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 18 0.04% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 331 0.77% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 5 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 4574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5670 # What write queue length does an incoming req see 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594 1.37% 80.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 623 1.44% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 284 0.66% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 262 0.61% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 268 0.62% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 398 0.92% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 204 0.47% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 163 0.38% 85.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 93 0.21% 85.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 193 0.45% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 100 0.23% 86.21% # Bytes accessed per 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66 0.15% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 40 0.09% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 80 0.18% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 95 0.22% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 21 0.05% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 10 0.02% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.18% # Bytes accessed per row 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+system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 7 0.02% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 40 0.09% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 176 0.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 43193 # Bytes accessed per row activation -system.physmem.totQLat 8380902250 # Total ticks spent queuing -system.physmem.totMemAccLat 15783312250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2226085000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5176325000 # Total ticks spent accessing banks -system.physmem.avgQLat 18824.31 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11626.52 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 174 0.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 43301 # Bytes accessed per row activation +system.physmem.totQLat 8362787000 # Total ticks spent queuing +system.physmem.totMemAccLat 15768695750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225940000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5179968750 # Total ticks spent accessing banks +system.physmem.avgQLat 18784.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11635.46 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35450.83 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 35420.31 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s @@ -360,59 +363,60 @@ system.physmem.busUtil 0.15 # Da system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.37 # Average write queue length when enqueuing -system.physmem.readRowHits 424661 # Number of row buffer hits during reads -system.physmem.writeRowHits 94799 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes -system.physmem.avgGap 3305785.86 # Average gap between requests -system.physmem.pageHitRate 92.32 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19402801 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295960 # Transaction distribution -system.membus.trans_dist::ReadResp 295877 # Transaction distribution +system.physmem.avgWrQLen 11.24 # Average write queue length when enqueuing +system.physmem.readRowHits 424550 # Number of row buffer hits during reads +system.physmem.writeRowHits 94755 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.69 # Row buffer hit rate for writes +system.physmem.avgGap 3306027.09 # Average gap between requests +system.physmem.pageHitRate 92.30 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.39 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19401389 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295980 # Transaction distribution +system.membus.trans_dist::ReadResp 295901 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117448 # Transaction distribution -system.membus.trans_dist::UpgradeReq 180 # Transaction distribution -system.membus.trans_dist::UpgradeResp 180 # Transaction distribution -system.membus.trans_dist::ReadExReq 156869 # Transaction distribution -system.membus.trans_dist::ReadExResp 156869 # Transaction distribution -system.membus.trans_dist::BadAddressError 83 # Transaction distribution +system.membus.trans_dist::Writeback 117429 # Transaction distribution +system.membus.trans_dist::UpgradeReq 181 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 182 # Transaction distribution +system.membus.trans_dist::ReadExReq 156823 # Transaction distribution +system.membus.trans_dist::ReadExResp 156823 # Transaction distribution +system.membus.trans_dist::BadAddressError 79 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884143 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917357 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042103 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042036 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748404 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745780 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36057460 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36057460 # Total data (bytes) +system.membus.tot_pkt_size::total 36054836 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36054836 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29954500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29837500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1551414500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1551324500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 96500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3763341794 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3763216294 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376305243 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376313495 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261102 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261116 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710341438000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261102 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078819 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078819 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710341603000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261116 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -423,12 +427,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12983817806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12983817806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13004951689 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13004951689 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13004951689 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13004951689 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12974928560 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12974928560 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12996062443 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12996062443 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12996062443 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12996062443 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -447,17 +451,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312471.549047 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312471.549047 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311682.485057 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311682.485057 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 402476 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312257.618406 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312257.618406 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311469.441414 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311469.441414 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 401483 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29170 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29284 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.797600 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.709978 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -473,12 +477,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10821554320 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10821554320 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10833691203 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10833691203 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10833691203 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10833691203 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10812648570 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10812648570 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10824785453 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10824785453 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10824785453 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10824785453 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -489,12 +493,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260434.018098 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260434.018098 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260219.690268 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260219.690268 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -508,35 +512,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13864479 # Number of BP lookups -system.cpu.branchPred.condPredicted 11634507 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 398117 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9551974 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5822395 # Number of BTB hits +system.cpu.branchPred.lookups 13863448 # Number of BP lookups +system.cpu.branchPred.condPredicted 11631259 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399718 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9400932 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5821857 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 60.954887 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 906213 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38605 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.928509 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 906521 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39211 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9930859 # DTB read hits -system.cpu.dtb.read_misses 42001 # DTB read misses -system.cpu.dtb.read_acv 541 # DTB read access violations -system.cpu.dtb.read_accesses 942214 # DTB read accesses -system.cpu.dtb.write_hits 6592411 # DTB write hits -system.cpu.dtb.write_misses 10345 # DTB write misses +system.cpu.dtb.read_hits 9926517 # DTB read hits +system.cpu.dtb.read_misses 41406 # DTB read misses +system.cpu.dtb.read_acv 531 # DTB read access violations +system.cpu.dtb.read_accesses 940700 # DTB read accesses +system.cpu.dtb.write_hits 6593963 # DTB write hits +system.cpu.dtb.write_misses 10630 # DTB write misses system.cpu.dtb.write_acv 410 # DTB write access violations -system.cpu.dtb.write_accesses 337923 # DTB write accesses -system.cpu.dtb.data_hits 16523270 # DTB hits -system.cpu.dtb.data_misses 52346 # DTB misses -system.cpu.dtb.data_acv 951 # DTB access violations -system.cpu.dtb.data_accesses 1280137 # DTB accesses -system.cpu.itb.fetch_hits 1308071 # ITB hits -system.cpu.itb.fetch_misses 36703 # ITB misses -system.cpu.itb.fetch_acv 1058 # ITB acv -system.cpu.itb.fetch_accesses 1344774 # ITB accesses +system.cpu.dtb.write_accesses 338096 # DTB write accesses +system.cpu.dtb.data_hits 16520480 # DTB hits +system.cpu.dtb.data_misses 52036 # DTB misses +system.cpu.dtb.data_acv 941 # DTB access violations +system.cpu.dtb.data_accesses 1278796 # DTB accesses +system.cpu.itb.fetch_hits 1306353 # ITB hits +system.cpu.itb.fetch_misses 36823 # ITB misses +system.cpu.itb.fetch_acv 1069 # ITB acv +system.cpu.itb.fetch_accesses 1343176 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -549,269 +553,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 121927488 # number of cpu cycles simulated +system.cpu.numCycles 121966998 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28039089 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70847333 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13864479 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6728608 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13268188 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1998523 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38187764 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33374 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253703 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 358378 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 313 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8556240 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264321 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81433386 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870004 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.213508 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28067964 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70813073 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13863448 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6728378 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13263425 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1999195 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38181411 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 255000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 364206 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 297 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8556045 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264477 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81457086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869330 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.212823 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68165198 83.71% 83.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 850053 1.04% 84.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1699284 2.09% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 821371 1.01% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2763942 3.39% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 562061 0.69% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645266 0.79% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1012758 1.24% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4913453 6.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68193661 83.72% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 852857 1.05% 84.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1696439 2.08% 86.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 825181 1.01% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2758325 3.39% 91.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561473 0.69% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645881 0.79% 92.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1010308 1.24% 93.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4912961 6.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81433386 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.113711 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.581061 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29221081 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37872240 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12130703 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 959021 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1250340 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 583021 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69509272 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129850 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1250340 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30372674 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14147971 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20014852 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11335195 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4312352 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65701425 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7084 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 503729 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1544223 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43873094 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79768312 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79589398 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166462 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180112 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5692974 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682864 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240315 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12255388 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10448429 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6906827 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318660 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 851527 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58223534 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050984 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56812947 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113805 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6931173 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3605221 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1390018 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81433386 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697662 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359692 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81457086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.113666 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.580592 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29256938 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37863691 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12127839 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 959156 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1249461 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 584263 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42640 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69481989 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129319 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1249461 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30407522 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14148846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20005990 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11332374 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4312891 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65679549 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7211 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504797 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1541440 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43855166 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79746051 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79567055 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166544 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180329 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5674829 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682909 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240455 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12257327 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10441163 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6908790 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1318239 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 851396 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58211664 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050007 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56814932 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114609 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6922962 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3587498 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1389025 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81457086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697483 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359485 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56726750 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10882649 13.36% 83.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5163201 6.34% 89.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3388782 4.16% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2628492 3.23% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1462722 1.80% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 751690 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332968 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96132 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56746030 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10887232 13.37% 83.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5162469 6.34% 89.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3392471 4.16% 93.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2625915 3.22% 96.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461124 1.79% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 753330 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332031 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96484 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81433386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81457086 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91250 11.56% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372174 47.14% 58.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326051 41.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91940 11.62% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373423 47.20% 58.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 325849 41.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38733166 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61715 0.11% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38737583 68.18% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61738 0.11% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10362094 18.24% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6670366 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10357242 18.23% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6672763 11.74% 98.33% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56812947 # Type of FU issued -system.cpu.iq.rate 0.465957 # Inst issue rate -system.cpu.iq.fu_busy_cnt 789475 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195270080 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66882864 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55570085 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692479 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327821 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57233809 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 596971 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56814932 # Type of FU issued +system.cpu.iq.rate 0.465822 # Inst issue rate +system.cpu.iq.fu_busy_cnt 791212 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013926 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195300199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66861892 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55573336 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692571 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336551 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327871 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57237458 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361400 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598272 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1356016 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3236 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14012 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 528856 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1348718 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3201 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14139 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 530806 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17919 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 183461 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17937 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 182742 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1250340 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10233655 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 702274 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63801966 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 688802 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10448429 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6906827 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805093 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17454 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14012 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 201109 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411560 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612669 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56346471 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10001011 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466475 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1249461 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10237116 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 702035 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63785040 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 690324 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10441163 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6908790 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805677 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512237 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17569 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14139 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 202047 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411314 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 613361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56348369 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9996094 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 466562 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3527448 # number of nop insts executed -system.cpu.iew.exec_refs 16619020 # number of memory reference insts executed -system.cpu.iew.exec_branches 8923746 # Number of branches executed -system.cpu.iew.exec_stores 6618009 # Number of stores executed -system.cpu.iew.exec_rate 0.462131 # Inst execution rate -system.cpu.iew.wb_sent 56013491 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55897906 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27708487 # num instructions producing a value -system.cpu.iew.wb_consumers 37528450 # num instructions consuming a value +system.cpu.iew.exec_nop 3523369 # number of nop insts executed +system.cpu.iew.exec_refs 16615920 # number of memory reference insts executed +system.cpu.iew.exec_branches 8927027 # Number of branches executed +system.cpu.iew.exec_stores 6619826 # Number of stores executed +system.cpu.iew.exec_rate 0.461997 # Inst execution rate +system.cpu.iew.wb_sent 56016387 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55901207 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27709617 # num instructions producing a value +system.cpu.iew.wb_consumers 37531222 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458452 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738333 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458331 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738308 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7515002 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660966 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80183046 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.700527 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.629598 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7496348 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660982 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 568504 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80207625 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.700316 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.629380 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59370328 74.04% 74.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8654728 10.79% 84.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4617014 5.76% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2519187 3.14% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1509953 1.88% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 613300 0.76% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 523538 0.65% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 523484 0.65% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1851514 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59390670 74.05% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8659340 10.80% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4620197 5.76% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2517886 3.14% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1507376 1.88% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 612052 0.76% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 525608 0.66% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 522089 0.65% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1852407 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80183046 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170357 # Number of instructions committed -system.cpu.commit.committedOps 56170357 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80207625 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56170683 # Number of instructions committed +system.cpu.commit.committedOps 56170683 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470384 # Number of memory references committed -system.cpu.commit.loads 9092413 # Number of loads committed -system.cpu.commit.membars 226354 # Number of memory barriers committed -system.cpu.commit.branches 8439829 # Number of branches committed +system.cpu.commit.refs 15470429 # Number of memory references committed +system.cpu.commit.loads 9092445 # Number of loads committed +system.cpu.commit.membars 226358 # Number of memory barriers committed +system.cpu.commit.branches 8439899 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019973 # Number of committed integer instructions. -system.cpu.commit.function_calls 740579 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1851514 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52020266 # Number of committed integer instructions. +system.cpu.commit.function_calls 740581 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1852407 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141767299 # The number of ROB reads -system.cpu.rob.rob_writes 128622610 # The number of ROB writes -system.cpu.timesIdled 1192878 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40494102 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598461292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979573 # Number of Instructions Simulated -system.cpu.committedOps 52979573 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52979573 # Number of Instructions Simulated -system.cpu.cpi 2.301406 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301406 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434517 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434517 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73879526 # number of integer regfile reads -system.cpu.int_regfile_writes 40317649 # number of integer regfile writes -system.cpu.fp_regfile_reads 165968 # number of floating regfile reads -system.cpu.fp_regfile_writes 167427 # number of floating regfile writes -system.cpu.misc_regfile_reads 1984782 # number of misc regfile reads -system.cpu.misc_regfile_writes 938976 # number of misc regfile writes +system.cpu.rob.rob_reads 141772543 # The number of ROB reads +system.cpu.rob.rob_writes 128585215 # The number of ROB writes +system.cpu.timesIdled 1193212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40509912 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598422122 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979882 # Number of Instructions Simulated +system.cpu.committedOps 52979882 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52979882 # Number of Instructions Simulated +system.cpu.cpi 2.302138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.302138 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73881277 # number of integer regfile reads +system.cpu.int_regfile_writes 40316653 # number of integer regfile writes +system.cpu.fp_regfile_reads 166009 # number of floating regfile reads +system.cpu.fp_regfile_writes 167434 # number of floating regfile writes +system.cpu.misc_regfile_reads 1986207 # number of misc regfile reads +system.cpu.misc_regfile_writes 938984 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -903,225 +907,233 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377740446 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377738948 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42670757 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42679505 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111891693 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2116597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2116497 # Transaction distribution +system.cpu.toL2Bus.throughput 111941811 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2118263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2118167 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840887 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840743 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301054 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2016984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678218 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5695202 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64539584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143593268 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208132852 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208122804 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17856 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2479701498 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342536 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020543 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677710 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5698253 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64653440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143572596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208226036 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208215988 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17920 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2480284498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1516139861 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1518802860 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2192873665 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2192631666 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1007825 # number of replacements -system.cpu.icache.tags.tagsinuse 509.660233 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7491263 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1008333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.429354 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1009602 # number of replacements +system.cpu.icache.tags.tagsinuse 509.660060 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7489391 # Total number of references to valid blocks. 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-system.cpu.icache.overall_hits::cpu.inst 7491264 # number of overall hits -system.cpu.icache.overall_hits::total 7491264 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064974 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064974 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064974 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064974 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064974 # number of overall misses -system.cpu.icache.overall_misses::total 1064974 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14872208186 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14872208186 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14872208186 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14872208186 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14872208186 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14872208186 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8556238 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8556238 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8556238 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8556238 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8556238 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8556238 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124468 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124468 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124468 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124468 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124468 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124468 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13964.855655 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13964.855655 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13964.855655 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13964.855655 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5226 # number of cycles access was blocked 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14896343949 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14896343949 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14896343949 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14896343949 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14896343949 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14896343949 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8556044 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8556044 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8556044 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8556044 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8556044 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8556044 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124666 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124666 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124666 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124666 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124666 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124666 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13965.514478 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13965.514478 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13965.514478 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13965.514478 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4660 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 214 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.420561 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 23.417085 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56421 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56421 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56421 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56421 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 56421 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 56421 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008553 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1008553 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1008553 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1008553 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1008553 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1008553 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12184986133 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12184986133 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12184986133 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12184986133 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12184986133 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12184986133 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117873 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.117873 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.117873 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.651765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.651765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.651765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.651765 # average 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uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333940000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882589500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882589500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216529500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216529500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136841 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277661 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167615 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277661 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167615 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68277.949744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52613.620092 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53430.409929 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14000.868421 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14000.868421 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70394.702055 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70394.702055 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68277.949744 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57886.071698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58273.250386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68277.949744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57886.071698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58273.250386 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1203,161 +1223,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1401398 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994568 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11815525 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401910 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.428162 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1401219 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994567 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11810743 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401731 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.425827 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994568 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994567 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7210216 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7210216 # number of ReadReq hits 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miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117511571842 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117511571842 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117511571842 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117511571842 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9016796 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9016796 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208971 # number of LoadLockedReq accesses(hits+misses) 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0.316284 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3750918 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3750918 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3750918 # number of overall misses +system.cpu.dcache.overall_misses::total 3750918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40335866684 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40335866684 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77256495609 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77256495609 # number of WriteReq miss cycles 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+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200485 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200485 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316233 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316233 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108908 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108908 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247354 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247354 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247354 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247354 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22323.812086 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22323.812086 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39693.638678 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39693.638678 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14153.204830 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14153.204830 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31327.914673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31327.914673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3032993 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.247424 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247424 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247424 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247424 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22324.601467 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22324.601467 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39738.379165 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39738.379165 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14184.097150 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.097150 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31350.288727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31350.288727 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3041849 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 98350 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 98391 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.838770 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.915927 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840887 # number of writebacks -system.cpu.dcache.writebacks::total 840887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722519 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 722519 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643978 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643978 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5197 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5197 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2366497 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2366497 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2366497 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2366497 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084061 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084061 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300460 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300460 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17534 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17534 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840743 # number of writebacks +system.cpu.dcache.writebacks::total 840743 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722826 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722826 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643736 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5220 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5220 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2366562 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2366562 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2366562 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2366562 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083964 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083964 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300392 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300392 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17518 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17518 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384521 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384521 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384521 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384521 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27189046254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27189046254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11757002855 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11757002855 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761751 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761751 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38946049109 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38946049109 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38946049109 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38946049109 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424137500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424137500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997802998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997802998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421940498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421940498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120227 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120227 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048873 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048873 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384356 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384356 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384356 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384356 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27183263254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27183263254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11761438359 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11761438359 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200916999 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200916999 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38944701613 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38944701613 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38944701613 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38944701613 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424030000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424030000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997779498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997779498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421809498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421809498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048862 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091300 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091300 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25080.734621 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25080.734621 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39130.010168 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39130.010168 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11449.854625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11449.854625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091317 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091317 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25077.643957 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25077.643957 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39153.633782 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39153.633782 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11469.174506 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11469.174506 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1366,7 +1386,7 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6437 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl @@ -1378,11 +1398,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.41% # nu system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818037303500 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64303500 0.00% 97.74% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561270000 0.03% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41533903500 2.23% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860196780500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1818029044000 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64103000 0.00% 97.74% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561251500 0.03% 97.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41542545500 2.23% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860196944000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1446,9 +1466,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326384 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29638597000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2732860000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827825315500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29636227500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2736556500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827824152000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index 8b5822c19..8069712e0 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -60,6 +65,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -93,6 +99,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -115,11 +122,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu0.icache] @@ -128,6 +137,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -150,21 +160,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu0.isa] type=AlphaISA +eventq_index=0 [system.cpu0.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -176,6 +191,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -196,17 +212,21 @@ workload= [system.cpu1.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu1.isa] type=AlphaISA +eventq_index=0 [system.cpu1.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -237,6 +257,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -299,6 +321,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -310,21 +333,25 @@ predType=tournament [system.cpu2.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu2.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -333,16 +360,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -351,22 +381,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -375,22 +409,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -399,10 +437,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -411,124 +451,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -537,10 +598,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -549,16 +612,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -567,27 +633,33 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu2.isa] type=AlphaISA +eventq_index=0 [system.cpu2.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -595,19 +667,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -615,28 +690,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -650,6 +730,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -672,6 +753,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -681,6 +763,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -703,6 +786,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -710,6 +794,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -721,6 +806,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -747,6 +833,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -758,29 +845,35 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -789,6 +882,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -799,6 +893,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -807,6 +902,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -817,6 +913,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -845,6 +942,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -854,8 +952,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -872,6 +1002,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -895,6 +1026,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -912,6 +1044,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -929,6 +1062,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -946,6 +1080,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -963,6 +1098,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -980,6 +1116,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -997,6 +1134,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -1014,6 +1152,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -1031,6 +1170,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -1048,6 +1188,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -1065,6 +1206,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -1082,6 +1224,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -1099,6 +1242,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -1116,6 +1260,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -1133,6 +1278,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -1150,6 +1296,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -1167,6 +1314,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -1184,6 +1332,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -1201,6 +1350,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -1219,6 +1369,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -1246,6 +1397,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1255,8 +1407,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1268,6 +1452,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -1282,6 +1467,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -1294,6 +1480,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -1304,6 +1491,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -1314,6 +1502,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1323,5 +1512,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 739cb26e4..caa1e9081 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842698 # Number of seconds simulated -sim_ticks 1842698476000 # Number of ticks simulated -final_tick 1842698476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842697 # Number of seconds simulated +sim_ticks 1842697218000 # Number of ticks simulated +final_tick 1842697218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 222585 # Simulator instruction rate (inst/s) -host_op_rate 222585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5605413242 # Simulator tick rate (ticks/s) -host_mem_usage 334468 # Number of bytes of host memory used -host_seconds 328.74 # Real time elapsed on the host -sim_insts 73171582 # Number of instructions simulated -sim_ops 73171582 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 489344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20103680 # Number of bytes read from this memory +host_inst_rate 189301 # Simulator instruction rate (inst/s) +host_op_rate 189301 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4767309141 # Simulator tick rate (ticks/s) +host_mem_usage 353980 # Number of bytes of host memory used +host_seconds 386.53 # Real time elapsed on the host +sim_insts 73170192 # Number of instructions simulated +sim_ops 73170192 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 489152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20102912 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 144384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2235712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 284736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2526400 # Number of bytes read from this memory -system.physmem.bytes_read::total 28436608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 489344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 144384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 284736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7460736 # Number of bytes written to this memory -system.physmem.bytes_written::total 7460736 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314120 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 144448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2236224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 284928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2526528 # Number of bytes read from this memory +system.physmem.bytes_read::total 28436544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 489152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 284928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918528 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7459712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7459712 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7643 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314108 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2256 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34933 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39475 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444322 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116574 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116574 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 265558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10909913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 78355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1213282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 154521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1371033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15432046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 78355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 154521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048810 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048810 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10909913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 78355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1213282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 154521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1371033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19480856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98004 # Number of read requests accepted -system.physmem.writeReqs 44399 # Number of write requests accepted -system.physmem.readBursts 98004 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44399 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6271808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 2840768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6272256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2841536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu1.inst 2257 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39477 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444321 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116558 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116558 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 265454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10909504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 78389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1213560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 154626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1371103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15432022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265454 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 78389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 154626 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498469 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048257 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048257 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10909504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 78389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1213560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 154626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1371103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19480279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98018 # Number of read requests accepted +system.physmem.writeReqs 44365 # Number of write requests accepted +system.physmem.readBursts 98018 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44365 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6272576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 2838464 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6273152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2839360 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6232 # Per bank write bursts -system.physmem.perBankRdBursts::1 6028 # Per bank write bursts -system.physmem.perBankRdBursts::2 6221 # Per bank write bursts -system.physmem.perBankRdBursts::3 6513 # Per bank write bursts -system.physmem.perBankRdBursts::4 5794 # Per bank write bursts -system.physmem.perBankRdBursts::5 6242 # Per bank write bursts -system.physmem.perBankRdBursts::6 5925 # Per bank write bursts -system.physmem.perBankRdBursts::7 6039 # Per bank write bursts -system.physmem.perBankRdBursts::8 6348 # Per bank write bursts -system.physmem.perBankRdBursts::9 6026 # Per bank write bursts -system.physmem.perBankRdBursts::10 6373 # Per bank write bursts -system.physmem.perBankRdBursts::11 5867 # Per bank write bursts -system.physmem.perBankRdBursts::12 5876 # Per bank write bursts -system.physmem.perBankRdBursts::13 6234 # Per bank write bursts -system.physmem.perBankRdBursts::14 6235 # Per bank write bursts -system.physmem.perBankRdBursts::15 6044 # Per bank write bursts -system.physmem.perBankWrBursts::0 2859 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 42 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6238 # Per bank write bursts +system.physmem.perBankRdBursts::1 6029 # Per bank write bursts +system.physmem.perBankRdBursts::2 6222 # Per bank write bursts +system.physmem.perBankRdBursts::3 6415 # Per bank write bursts +system.physmem.perBankRdBursts::4 5671 # Per bank write bursts +system.physmem.perBankRdBursts::5 6259 # Per bank write bursts +system.physmem.perBankRdBursts::6 6020 # Per bank write bursts +system.physmem.perBankRdBursts::7 6028 # Per bank write bursts +system.physmem.perBankRdBursts::8 6370 # Per bank write bursts +system.physmem.perBankRdBursts::9 6122 # Per bank write bursts +system.physmem.perBankRdBursts::10 6366 # Per bank write bursts +system.physmem.perBankRdBursts::11 5871 # Per bank write bursts +system.physmem.perBankRdBursts::12 5882 # Per bank write bursts +system.physmem.perBankRdBursts::13 6242 # Per bank write bursts +system.physmem.perBankRdBursts::14 6237 # Per bank write bursts +system.physmem.perBankRdBursts::15 6037 # Per bank write bursts +system.physmem.perBankWrBursts::0 2849 # Per bank write bursts system.physmem.perBankWrBursts::1 2656 # Per bank write bursts -system.physmem.perBankWrBursts::2 2839 # Per bank write bursts -system.physmem.perBankWrBursts::3 3122 # Per bank write bursts -system.physmem.perBankWrBursts::4 2688 # Per bank write bursts -system.physmem.perBankWrBursts::5 2969 # Per bank write bursts -system.physmem.perBankWrBursts::6 2850 # Per bank write bursts -system.physmem.perBankWrBursts::7 2699 # Per bank write bursts -system.physmem.perBankWrBursts::8 3075 # Per bank write bursts -system.physmem.perBankWrBursts::9 2558 # Per bank write bursts -system.physmem.perBankWrBursts::10 2888 # Per bank write bursts -system.physmem.perBankWrBursts::11 2432 # Per bank write bursts -system.physmem.perBankWrBursts::12 2458 # Per bank write bursts -system.physmem.perBankWrBursts::13 2707 # Per bank write bursts -system.physmem.perBankWrBursts::14 2844 # Per bank write bursts -system.physmem.perBankWrBursts::15 2743 # Per bank write bursts +system.physmem.perBankWrBursts::2 2849 # Per bank write bursts +system.physmem.perBankWrBursts::3 3015 # Per bank write bursts +system.physmem.perBankWrBursts::4 2565 # Per bank write bursts +system.physmem.perBankWrBursts::5 2994 # Per bank write bursts +system.physmem.perBankWrBursts::6 2937 # Per bank write bursts +system.physmem.perBankWrBursts::7 2695 # Per bank write bursts +system.physmem.perBankWrBursts::8 3093 # Per bank write bursts +system.physmem.perBankWrBursts::9 2622 # Per bank write bursts +system.physmem.perBankWrBursts::10 2879 # Per bank write bursts +system.physmem.perBankWrBursts::11 2436 # Per bank write bursts +system.physmem.perBankWrBursts::12 2462 # Per bank write bursts +system.physmem.perBankWrBursts::13 2714 # Per bank write bursts +system.physmem.perBankWrBursts::14 2848 # Per bank write bursts +system.physmem.perBankWrBursts::15 2737 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 1841686150500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 1841684892500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98004 # Read request sizes (log2) +system.physmem.readPktSize::6 98018 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44399 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 66399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 14093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 963 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44365 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 66438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 959 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -151,181 +151,177 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 17930 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 508.141439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 169.008973 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1572.275953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 7528 41.99% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 2973 16.58% 58.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 1838 10.25% 68.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 1006 5.61% 74.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 670 3.74% 78.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 572 3.19% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 359 2.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 327 1.82% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 240 1.34% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 222 1.24% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 225 1.25% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 213 1.19% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 93 0.52% 90.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 79 0.44% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 78 0.44% 91.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 102 0.57% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 45 0.25% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 56 0.31% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 39 0.22% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 53 0.30% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 119 0.66% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 70 0.39% 94.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 89 0.50% 94.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 16 0.09% 95.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 5 0.03% 95.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 36 0.20% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 6 0.03% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 15 0.08% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 5 0.03% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 11 0.06% 95.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 11 0.06% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 2 0.01% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 1 0.01% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 2 0.01% 95.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.01% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 4 0.02% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 10 0.06% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 3 0.02% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 13 0.07% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 7 0.04% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 13 0.07% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 2 0.01% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 23 0.13% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.01% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 14 0.08% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.01% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 76 0.42% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.01% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 4 0.02% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 1 0.01% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 9 0.05% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 5 0.03% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.01% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 8 0.04% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 8 0.04% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 3 0.02% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 4 0.02% 98.25% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 1794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 17929 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 508.069831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.315652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1577.422962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 7580 42.28% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2972 16.58% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1827 10.19% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 983 5.48% 74.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 676 3.77% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 569 3.17% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 353 1.97% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 316 1.76% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 239 1.33% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 212 1.18% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 225 1.25% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 207 1.15% 90.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 92 0.51% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 80 0.45% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 62 0.35% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 115 0.64% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 35 0.20% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 50 0.28% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 54 0.30% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 63 0.35% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 123 0.69% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 74 0.41% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 80 0.45% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 19 0.11% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 7 0.04% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 37 0.21% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 7 0.04% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 18 0.10% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 6 0.03% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 9 0.05% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 16 0.09% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 1 0.01% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 4 0.02% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 12 0.07% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 11 0.06% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 9 0.05% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 13 0.07% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 3 0.02% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 22 0.12% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 13 0.07% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.01% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 77 0.43% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 5 0.03% 97.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 8 0.04% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 4 0.02% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 6 0.03% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 9 0.05% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 2 0.01% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 3 0.02% 98.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 5 0.03% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 6 0.03% 98.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.01% 98.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.01% 98.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 20 0.11% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 2 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 2 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 4 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 1 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 1 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 2 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 2 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 14 0.08% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 76 0.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 17930 # Bytes accessed per row activation -system.physmem.totQLat 2684942500 # Total ticks spent queuing -system.physmem.totMemAccLat 4336678750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 489985000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1161751250 # Total ticks spent accessing banks -system.physmem.avgQLat 27398.21 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11854.97 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7040-7043 1 0.01% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 21 0.12% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 4 0.02% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 2 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.01% 99.36% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.09% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 75 0.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 17929 # Bytes accessed per row activation +system.physmem.totQLat 2679388500 # Total ticks spent queuing +system.physmem.totMemAccLat 4331514750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 490045000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1162081250 # Total ticks spent accessing banks +system.physmem.avgQLat 27338.19 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11856.88 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44253.18 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44195.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s @@ -335,229 +331,233 @@ system.physmem.busUtil 0.04 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.18 # Average write queue length when enqueuing -system.physmem.readRowHits 89612 # Number of row buffer hits during reads -system.physmem.writeRowHits 34842 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.47 # Row buffer hit rate for writes -system.physmem.avgGap 12932916.80 # Average gap between requests +system.physmem.avgWrQLen 0.16 # Average write queue length when enqueuing +system.physmem.readRowHits 89637 # Number of row buffer hits during reads +system.physmem.writeRowHits 34794 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.43 # Row buffer hit rate for writes +system.physmem.avgGap 12934724.60 # Average gap between requests system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19524796 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44746 # Transaction distribution -system.membus.trans_dist::ReadResp 44539 # Transaction distribution -system.membus.trans_dist::WriteReq 3750 # Transaction distribution -system.membus.trans_dist::WriteResp 3750 # Transaction distribution -system.membus.trans_dist::Writeback 44399 # Transaction distribution -system.membus.trans_dist::UpgradeReq 43 # Transaction distribution -system.membus.trans_dist::UpgradeResp 43 # Transaction distribution -system.membus.trans_dist::ReadExReq 56527 # Transaction distribution -system.membus.trans_dist::ReadExResp 56527 # Transaction distribution -system.membus.trans_dist::BadAddressError 207 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 414 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 203660 # Packet count per connected master and slave (bytes) +system.membus.throughput 19524219 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44737 # Transaction distribution +system.membus.trans_dist::ReadResp 44533 # Transaction distribution +system.membus.trans_dist::WriteReq 3749 # Transaction distribution +system.membus.trans_dist::WriteResp 3749 # Transaction distribution +system.membus.trans_dist::Writeback 44365 # Transaction distribution +system.membus.trans_dist::UpgradeReq 45 # Transaction distribution +system.membus.trans_dist::UpgradeResp 45 # Transaction distribution +system.membus.trans_dist::ReadExReq 56547 # Transaction distribution +system.membus.trans_dist::ReadExResp 56547 # Transaction distribution +system.membus.trans_dist::BadAddressError 204 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 408 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 203650 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 254372 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15690 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6953984 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6969674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 254362 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15689 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6952704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6968393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9129482 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35968328 # Total data (bytes) +system.membus.tot_pkt_size::total 9128201 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35967240 # Total data (bytes) system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12460500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12468500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 511769750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 514332500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 256500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 252500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 762797456 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 764298954 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 153003500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 152995500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 337399 # number of replacements -system.l2c.tags.tagsinuse 65421.710089 # Cycle average of tags in use -system.l2c.tags.total_refs 2471820 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402562 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.140222 # Average number of references to valid blocks. +system.l2c.tags.replacements 337398 # number of replacements +system.l2c.tags.tagsinuse 65420.701532 # Cycle average of tags in use +system.l2c.tags.total_refs 2472173 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402561 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.141114 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54901.425298 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2456.924718 # Average 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number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 621588000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 693591500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1315179500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017836 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167730 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.070555 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020465 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.769231 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407317 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241636 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.131052 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.240385 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.070551 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020457 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408127 # mshr miss rate for ReadExReq accesses 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accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241107 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.114659 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034745 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54503.385170 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55036.589787 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 56800.435805 # average ReadReq mshr miss latency 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blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078432 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078432 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694870354000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254904 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -684,14 +684,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # 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miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5314732731 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5314732731 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5324036194 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5324036194 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5324036194 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5324036194 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -708,19 +708,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 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was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127905.581705 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 127905.581705 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127598.231132 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127598.231132 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 168308 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12345 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12241 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.641555 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.749530 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -734,14 +734,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 16965 system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses 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system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82832.797101 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82832.797101 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262498.060902 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 262498.060902 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262518.982659 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 262518.982659 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -775,22 +775,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4920992 # DTB read hits +system.cpu0.dtb.read_hits 4920578 # DTB read hits system.cpu0.dtb.read_misses 6099 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428234 # DTB read accesses -system.cpu0.dtb.write_hits 3511178 # DTB write hits +system.cpu0.dtb.read_accesses 428233 # DTB read accesses +system.cpu0.dtb.write_hits 3510258 # DTB write hits system.cpu0.dtb.write_misses 670 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations system.cpu0.dtb.write_accesses 163777 # DTB write accesses -system.cpu0.dtb.data_hits 8432170 # DTB hits +system.cpu0.dtb.data_hits 8430836 # DTB hits system.cpu0.dtb.data_misses 6769 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 592011 # DTB accesses -system.cpu0.itb.fetch_hits 2763046 # ITB hits +system.cpu0.dtb.data_accesses 592010 # DTB accesses +system.cpu0.itb.fetch_hits 2762930 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2766080 # ITB accesses +system.cpu0.itb.fetch_accesses 2765964 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -803,51 +803,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928344318 # number of cpu cycles simulated +system.cpu0.numCycles 928345000 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33880492 # Number of instructions committed -system.cpu0.committedOps 33880492 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31739536 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169894 # Number of float alu accesses -system.cpu0.num_func_calls 813170 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4699422 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31739536 # number of integer instructions -system.cpu0.num_fp_insts 169894 # number of float instructions -system.cpu0.num_int_register_reads 44596322 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23159667 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87728 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89270 # number of times the floating registers were written -system.cpu0.num_mem_refs 8462332 # number of memory refs -system.cpu0.num_load_insts 4942381 # Number of load instructions -system.cpu0.num_store_insts 3519951 # Number of store instructions -system.cpu0.num_idle_cycles 904625586.132235 # Number of idle cycles -system.cpu0.num_busy_cycles 23718731.867765 # Number of busy cycles +system.cpu0.committedInsts 33879417 # Number of instructions committed +system.cpu0.committedOps 33879417 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31738664 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 170028 # Number of float alu accesses +system.cpu0.num_func_calls 812853 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4700164 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31738664 # number of integer instructions +system.cpu0.num_fp_insts 170028 # number of float instructions +system.cpu0.num_int_register_reads 44595421 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23158595 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87794 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89338 # number of times the floating registers were written +system.cpu0.num_mem_refs 8461010 # number of memory refs +system.cpu0.num_load_insts 4941975 # Number of load instructions +system.cpu0.num_store_insts 3519035 # Number of store instructions +system.cpu0.num_idle_cycles 904626845.998199 # Number of idle cycles +system.cpu0.num_busy_cycles 23718154.001801 # Number of busy cycles system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6416 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211386 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6418 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105698 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819501633500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38918500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365019000 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22792135500 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842697706500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1819507118500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38781000 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365071000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22785478000 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842696448500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694791 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815828 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -883,10 +883,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -895,21 +895,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192241 # number of callpals executed +system.cpu0.kern.callpal::total 192238 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1909 -system.cpu0.kern.mode_good::user 1739 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391309 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29773270000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2593332500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810331099500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29794763000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2592746500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810308934500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -941,58 +941,59 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110448008 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 784800 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 784578 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3750 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3750 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 371852 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150627 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133731 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 207 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846719 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1369630 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2216349 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27094720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55304714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82399434 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203511688 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10688 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2136322000 # Layer occupancy (ticks) +system.toL2Bus.throughput 110459996 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 784722 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 784503 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371354 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150558 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133662 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 204 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 847542 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1368014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2215556 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27120896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55237129 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82358025 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203533320 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 11008 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2134008000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1907046997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1908780020 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2233138904 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2230620167 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469141 # Throughput (bytes/s) +system.iobus.throughput 1469142 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 2975 # Transaction distribution system.iobus.trans_dist::ReadResp 2975 # Transaction distribution -system.iobus.trans_dist::WriteReq 20646 # Transaction distribution -system.iobus.trans_dist::WriteResp 20646 # Transaction distribution +system.iobus.trans_dist::WriteReq 20645 # Transaction distribution +system.iobus.trans_dist::WriteResp 20645 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8370 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13310 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47240 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4186 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4185 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15690 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15689 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1098482 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1098481 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -1000,368 +1001,384 @@ system.iobus.reqLayer1.occupancy 102000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6239000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6237000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 153606200 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 153613694 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9562000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9561000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17411500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17409500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 950723 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.190316 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43428114 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 951234 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.654501 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 951005 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.190319 # Cycle average of tags in use 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of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19372 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47406 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184040 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126440 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21396 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51446 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7296247 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1917905 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3687741 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12901893 # number of demand (read+write) hits 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# number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2152 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6843 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18737 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 891144 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 142967 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1129269 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2163380 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 891144 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 142967 # number of overall misses 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131218249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 3914593759 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27438287243 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 31352881002 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3914593759 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27438287243 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31352881002 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4804508 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1183842 # 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accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2061032 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4816640 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15066255 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150162 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083613 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181999 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.151782 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049927 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050580 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315894 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131685 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077052 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100862 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124906 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092409 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108742 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069556 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234482 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.143580 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108742 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069556 # miss rate for overall accesses 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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7002.012367 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14524.024099 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14524.024099 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 591087 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 822 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 17697 # number of cycles access was blocked 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0.092402 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108843 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069372 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234434 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.143600 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108843 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069372 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234434 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.143600 # miss rate for overall accesses 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average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27381.100247 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24297.388171 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14492.544538 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27381.100247 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24297.388171 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14492.544538 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 584754 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 852 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 17600 # number of cycles access was blocked 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number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu2.data 788163 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 788163 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu2.data 788163 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 788163 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98995 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252117 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 351112 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44362 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89135 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133497 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2165 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5430 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7595 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 143357 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 341252 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 484609 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 143357 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 341252 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 484609 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2056105000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4263367239 # number of ReadReq MSHR miss cycles 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uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791088500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660683500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737485500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1398169000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083613 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086086 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050580 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047212 # mshr miss rate for WriteReq accesses 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rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20769.786353 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16910.272766 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.451318 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35250.039245 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29537.732081 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31435.972269 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11180.946882 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12184.806630 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.650428 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98671 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 251974 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 350645 # number of ReadReq MSHR misses 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484073 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 142967 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 341106 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484073 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2050323500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4260770982 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6311094482 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1561811741 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2625415492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4187227233 # number of WriteReq MSHR miss cycles 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cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6886186474 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10498321715 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296522000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310560000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607082000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364175500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426698000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790873500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660697500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737258000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397955500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083348 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086014 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039320 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047221 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021705 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099981 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099910 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037342 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032132 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032132 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20779.393135 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16909.565995 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.529801 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35258.527655 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29455.363865 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31381.923082 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11237.918216 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12112.592251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11864.005547 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1376,22 +1393,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1203387 # DTB read hits +system.cpu1.dtb.read_hits 1203332 # DTB read hits system.cpu1.dtb.read_misses 1366 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142939 # DTB read accesses -system.cpu1.dtb.write_hits 898859 # DTB write hits +system.cpu1.dtb.read_accesses 142940 # DTB read accesses +system.cpu1.dtb.write_hits 898898 # DTB write hits system.cpu1.dtb.write_misses 183 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations system.cpu1.dtb.write_accesses 58529 # DTB write accesses -system.cpu1.dtb.data_hits 2102246 # DTB hits +system.cpu1.dtb.data_hits 2102230 # DTB hits system.cpu1.dtb.data_misses 1549 # DTB misses system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 201468 # DTB accesses -system.cpu1.itb.fetch_hits 859133 # ITB hits +system.cpu1.dtb.data_accesses 201469 # DTB accesses +system.cpu1.itb.fetch_hits 859402 # ITB hits system.cpu1.itb.fetch_misses 692 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 859825 # ITB accesses +system.cpu1.itb.fetch_accesses 860094 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1404,28 +1421,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953620014 # number of cpu cycles simulated +system.cpu1.numCycles 953617285 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7953643 # Number of instructions committed -system.cpu1.committedOps 7953643 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7410219 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45003 # Number of float alu accesses -system.cpu1.num_func_calls 212713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1020267 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7410219 # number of integer instructions -system.cpu1.num_fp_insts 45003 # number of float instructions -system.cpu1.num_int_register_reads 10384111 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5386902 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24304 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24611 # number of times the floating registers were written -system.cpu1.num_mem_refs 2109479 # number of memory refs -system.cpu1.num_load_insts 1208276 # Number of load instructions -system.cpu1.num_store_insts 901203 # Number of store instructions -system.cpu1.num_idle_cycles 922135498.680812 # Number of idle cycles -system.cpu1.num_busy_cycles 31484515.319188 # Number of busy cycles -system.cpu1.not_idle_fraction 0.033016 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.966984 # Percentage of idle cycles +system.cpu1.committedInsts 7956345 # Number of instructions committed +system.cpu1.committedOps 7956345 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7412681 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44901 # Number of float alu accesses +system.cpu1.num_func_calls 213028 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1020887 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7412681 # number of integer instructions +system.cpu1.num_fp_insts 44901 # number of float instructions +system.cpu1.num_int_register_reads 10388601 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5388855 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24208 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24605 # number of times the floating registers were written +system.cpu1.num_mem_refs 2109439 # number of memory refs +system.cpu1.num_load_insts 1208206 # Number of load instructions +system.cpu1.num_store_insts 901233 # Number of store instructions +system.cpu1.num_idle_cycles 922131579.439540 # Number of idle cycles +system.cpu1.num_busy_cycles 31485705.560460 # Number of busy cycles +system.cpu1.not_idle_fraction 0.033017 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.966983 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1443,35 +1460,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9128355 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8449925 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 124319 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7461780 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6520544 # Number of BTB hits +system.cpu2.branchPred.lookups 9131296 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8453261 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 124867 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7606484 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6524985 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 87.385905 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 281902 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13317 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.781880 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 282035 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13344 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3185589 # DTB read hits -system.cpu2.dtb.read_misses 11798 # DTB read misses -system.cpu2.dtb.read_acv 121 # DTB read access violations -system.cpu2.dtb.read_accesses 217406 # DTB read accesses -system.cpu2.dtb.write_hits 2009886 # DTB write hits -system.cpu2.dtb.write_misses 2608 # DTB write misses -system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 82301 # DTB write accesses -system.cpu2.dtb.data_hits 5195475 # DTB hits -system.cpu2.dtb.data_misses 14406 # DTB misses -system.cpu2.dtb.data_acv 227 # DTB access violations -system.cpu2.dtb.data_accesses 299707 # DTB accesses -system.cpu2.itb.fetch_hits 369992 # ITB hits -system.cpu2.itb.fetch_misses 5727 # ITB misses -system.cpu2.itb.fetch_acv 273 # ITB acv -system.cpu2.itb.fetch_accesses 375719 # ITB accesses +system.cpu2.dtb.read_hits 3186348 # DTB read hits +system.cpu2.dtb.read_misses 11810 # DTB read misses +system.cpu2.dtb.read_acv 124 # DTB read access violations +system.cpu2.dtb.read_accesses 217745 # DTB read accesses +system.cpu2.dtb.write_hits 2009701 # DTB write hits +system.cpu2.dtb.write_misses 2606 # DTB write misses +system.cpu2.dtb.write_acv 109 # DTB write access violations +system.cpu2.dtb.write_accesses 82375 # DTB write accesses +system.cpu2.dtb.data_hits 5196049 # DTB hits +system.cpu2.dtb.data_misses 14416 # DTB misses +system.cpu2.dtb.data_acv 233 # DTB access violations +system.cpu2.dtb.data_accesses 300120 # DTB accesses +system.cpu2.itb.fetch_hits 370442 # ITB hits +system.cpu2.itb.fetch_misses 5628 # ITB misses +system.cpu2.itb.fetch_acv 253 # ITB acv +system.cpu2.itb.fetch_accesses 376070 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1484,137 +1501,137 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31308710 # number of cpu cycles simulated +system.cpu2.numCycles 31313073 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8320877 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 36988805 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9128355 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6802446 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8846835 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 603748 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9639992 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 11047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63718 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 87241 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2552980 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 86276 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27364450 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.351710 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.294118 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8328585 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 37006400 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9131296 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6807020 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8851345 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 606644 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9641968 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10046 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1931 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63228 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 87070 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2553376 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 86779 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27379324 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.351618 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.293970 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18517615 67.67% 67.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 268760 0.98% 68.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 429758 1.57% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4997201 18.26% 88.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 759565 2.78% 91.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 164512 0.60% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 190396 0.70% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 427414 1.56% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1609229 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18527979 67.67% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 269262 0.98% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 428968 1.57% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5000608 18.26% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 759354 2.77% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 165275 0.60% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 190932 0.70% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 427573 1.56% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1609373 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27364450 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.291560 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.181422 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8471005 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9721532 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8236973 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 308822 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 380199 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165870 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12770 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36596033 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40157 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 380199 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8829996 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2781091 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5750095 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8109315 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1267845 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35455371 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2432 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 230458 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 443882 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23756988 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44373855 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44317462 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52634 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21971271 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1785717 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 500561 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59005 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3706520 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3341982 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2099682 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 368903 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 258103 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32963824 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 619272 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32519364 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 32677 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2138512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1074729 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 437003 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27364450 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.188380 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.575952 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27379324 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.291613 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.181819 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8475609 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9724872 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8241247 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 308907 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 382752 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165606 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12712 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36612854 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39749 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 382752 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8834671 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2773280 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5760129 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8113478 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1269087 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35472103 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2436 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 230799 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 444723 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23769376 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44394567 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44338159 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52651 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21967508 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1801868 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 500326 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 58967 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3713170 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3346051 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2099971 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 366369 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 258671 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32979578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 619087 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32529976 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 34753 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2147129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1082645 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 436861 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27379324 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.188122 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.575744 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15094542 55.16% 55.16% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3058510 11.18% 66.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1555503 5.68% 72.02% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5825063 21.29% 93.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 904805 3.31% 96.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 480018 1.75% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 285628 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141467 0.52% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18914 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15104518 55.17% 55.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3059496 11.17% 66.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1557193 5.69% 72.03% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5827645 21.28% 93.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 904106 3.30% 96.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480512 1.76% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 285612 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141433 0.52% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18809 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27364450 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27379324 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33388 13.55% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 112327 45.58% 59.13% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100703 40.87% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 32920 13.41% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112185 45.69% 59.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100449 40.91% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26855600 82.58% 82.59% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20032 0.06% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26864472 82.58% 82.59% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20045 0.06% 82.65% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8424 0.03% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8419 0.03% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued @@ -1640,114 +1657,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3311528 10.18% 92.87% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2031960 6.25% 99.11% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 288160 0.89% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3313279 10.19% 92.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2032055 6.25% 99.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288046 0.89% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32519364 # Type of FU issued -system.cpu2.iq.rate 1.038668 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 246418 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007578 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92448223 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35610975 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32122316 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234050 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114559 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110669 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32641435 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 121907 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 186593 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32529976 # Type of FU issued +system.cpu2.iq.rate 1.038862 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 245554 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007549 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92485827 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35635212 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32132884 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 233756 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114401 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110529 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32651329 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121761 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186414 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 407978 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1104 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4025 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 156833 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 413956 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3936 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 157547 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4157 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 26970 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4151 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 27254 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 380199 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2010765 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 204147 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34852291 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 222063 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3341982 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2099682 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 549953 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 141753 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1988 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4025 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63582 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127875 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 191457 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32361861 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3205658 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 157503 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 382752 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2003866 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 204399 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34866454 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 220221 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3346051 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2099971 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 549960 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 142228 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1969 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3936 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63951 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 128015 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 191966 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32372492 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3206448 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 157484 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1269195 # number of nop insts executed -system.cpu2.iew.exec_refs 5222587 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7560841 # Number of branches executed -system.cpu2.iew.exec_stores 2016929 # Number of stores executed -system.cpu2.iew.exec_rate 1.033638 # Inst execution rate -system.cpu2.iew.wb_sent 32266608 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32232985 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18776213 # num instructions producing a value -system.cpu2.iew.wb_consumers 21965918 # num instructions consuming a value +system.cpu2.iew.exec_nop 1267789 # number of nop insts executed +system.cpu2.iew.exec_refs 5223192 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7564928 # Number of branches executed +system.cpu2.iew.exec_stores 2016744 # Number of stores executed +system.cpu2.iew.exec_rate 1.033833 # Inst execution rate +system.cpu2.iew.wb_sent 32276755 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32243413 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18781769 # num instructions producing a value +system.cpu2.iew.wb_consumers 21976070 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.029521 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.854788 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.029711 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.854646 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2305690 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 182269 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 176747 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26984251 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.204438 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.848007 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2322975 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182226 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 177336 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26996572 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.203754 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846865 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16102351 59.67% 59.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2321930 8.60% 68.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1225737 4.54% 72.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5569081 20.64% 93.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 502606 1.86% 95.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 185666 0.69% 96.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 176683 0.65% 96.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180209 0.67% 97.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 719988 2.67% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16110852 59.68% 59.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2323792 8.61% 68.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1227035 4.55% 72.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5572191 20.64% 93.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 501625 1.86% 95.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185779 0.69% 96.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 177561 0.66% 96.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179863 0.67% 97.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 717874 2.66% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26984251 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32500866 # Number of instructions committed -system.cpu2.commit.committedOps 32500866 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26996572 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32497229 # Number of instructions committed +system.cpu2.commit.committedOps 32497229 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4876853 # Number of memory references committed -system.cpu2.commit.loads 2934004 # Number of loads committed -system.cpu2.commit.membars 63840 # Number of memory barriers committed -system.cpu2.commit.branches 7415854 # Number of branches committed -system.cpu2.commit.fp_insts 109494 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31057555 # Number of committed integer instructions. -system.cpu2.commit.function_calls 228510 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 719988 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4874519 # Number of memory references committed +system.cpu2.commit.loads 2932095 # Number of loads committed +system.cpu2.commit.membars 63814 # Number of memory barriers committed +system.cpu2.commit.branches 7417113 # Number of branches committed +system.cpu2.commit.fp_insts 109328 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31054650 # Number of committed integer instructions. +system.cpu2.commit.function_calls 228340 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 717874 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 60996891 # The number of ROB reads -system.cpu2.rob.rob_writes 69992925 # The number of ROB writes -system.cpu2.timesIdled 244953 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3944260 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746464525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31337447 # Number of Instructions Simulated -system.cpu2.committedOps 31337447 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 31337447 # Number of Instructions Simulated -system.cpu2.cpi 0.999083 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.999083 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.000918 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.000918 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42570866 # number of integer regfile reads -system.cpu2.int_regfile_writes 22648106 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67644 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67951 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5345306 # number of misc regfile reads -system.cpu2.misc_regfile_writes 257045 # number of misc regfile writes +system.cpu2.rob.rob_reads 61024976 # The number of ROB reads +system.cpu2.rob.rob_writes 70022633 # The number of ROB writes +system.cpu2.timesIdled 244840 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3933749 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746460059 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31334430 # Number of Instructions Simulated +system.cpu2.committedOps 31334430 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31334430 # Number of Instructions Simulated +system.cpu2.cpi 0.999318 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.999318 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.000682 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.000682 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42582766 # number of integer regfile reads +system.cpu2.int_regfile_writes 22654603 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67639 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67817 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5347337 # number of misc regfile reads +system.cpu2.misc_regfile_writes 256988 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index d132fd20b..25f2809e1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -188,6 +199,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.checker.dtb +eventq_index=0 exitOnError=false function_trace=false function_trace_start=0 @@ -212,18 +224,21 @@ workload= [system.cpu.checker.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] [system.cpu.checker.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -242,18 +257,21 @@ midr=890224640 [system.cpu.checker.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[4] [system.cpu.checker.tracer] type=ExeTracer +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -261,6 +279,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -283,18 +302,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -303,15 +325,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -320,16 +345,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -338,22 +366,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -362,22 +394,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -386,10 +422,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -398,124 +436,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -524,10 +583,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -536,16 +597,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -554,10 +618,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -568,6 +634,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -590,14 +657,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -616,12 +686,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -632,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -654,12 +727,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -669,19 +744,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -694,6 +773,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -716,6 +796,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -723,6 +804,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -734,6 +816,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -760,6 +843,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -771,19 +855,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -793,6 +881,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -802,6 +891,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -830,6 +920,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -839,8 +930,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -852,6 +975,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -867,6 +991,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -881,6 +1007,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -890,6 +1017,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -911,8 +1039,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -921,6 +1051,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -931,6 +1062,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -941,6 +1073,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -951,6 +1084,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -965,6 +1099,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -978,6 +1113,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -995,6 +1131,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1007,6 +1144,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1018,6 +1156,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1028,6 +1167,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1040,6 +1180,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1053,6 +1194,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1063,6 +1205,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1073,6 +1216,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1083,6 +1227,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1095,6 +1240,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1109,6 +1255,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1121,6 +1268,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1135,6 +1283,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1145,6 +1294,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1155,6 +1305,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1165,6 +1316,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1173,6 +1325,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1180,11 +1333,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 8cfdfc3f7..d7c49d42e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525141 # Number of seconds simulated -sim_ticks 2525141046500 # Number of ticks simulated -final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525132 # Number of seconds simulated +sim_ticks 2525131633500 # Number of ticks simulated +final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50522 # Simulator instruction rate (inst/s) -host_op_rate 65007 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2115457252 # Simulator tick rate (ticks/s) -host_mem_usage 427804 # Number of bytes of host memory used -host_seconds 1193.66 # Real time elapsed on the host -sim_insts 60305756 # Number of instructions simulated -sim_ops 77596741 # Number of ops (including micro ops) simulated +host_inst_rate 41051 # Simulator instruction rate (inst/s) +host_op_rate 52821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1718892257 # Simulator tick rate (ticks/s) +host_mem_usage 447424 # Number of bytes of host memory used +host_seconds 1469.05 # Real time elapsed on the host +sim_insts 60305678 # Number of instructions simulated +sim_ops 77596684 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.writeReqs 813149 # Number of write requests accepted system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943582 # Per bank write bursts -system.physmem.perBankRdBursts::1 943145 # Per bank write bursts -system.physmem.perBankRdBursts::2 939291 # Per bank write bursts -system.physmem.perBankRdBursts::3 939307 # Per bank write bursts -system.physmem.perBankRdBursts::4 943115 # Per bank write bursts -system.physmem.perBankRdBursts::5 943141 # Per bank write bursts -system.physmem.perBankRdBursts::6 939138 # Per bank write bursts -system.physmem.perBankRdBursts::7 938546 # Per bank write bursts -system.physmem.perBankRdBursts::8 943996 # Per bank write bursts -system.physmem.perBankRdBursts::9 943390 # Per bank write bursts -system.physmem.perBankRdBursts::10 938426 # Per bank write bursts -system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943580 # Per bank write bursts +system.physmem.perBankRdBursts::1 943152 # Per bank write bursts +system.physmem.perBankRdBursts::2 939288 # Per bank write bursts +system.physmem.perBankRdBursts::3 939310 # Per bank write bursts +system.physmem.perBankRdBursts::4 943113 # Per bank write bursts +system.physmem.perBankRdBursts::5 943139 # Per bank write bursts +system.physmem.perBankRdBursts::6 939134 # Per bank write bursts +system.physmem.perBankRdBursts::7 938551 # Per bank write bursts +system.physmem.perBankRdBursts::8 944000 # Per bank write bursts +system.physmem.perBankRdBursts::9 943392 # Per bank write bursts +system.physmem.perBankRdBursts::10 938425 # Per bank write bursts +system.physmem.perBankRdBursts::11 937973 # Per bank write bursts system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943533 # Per bank write bursts -system.physmem.perBankRdBursts::14 939234 # Per bank write bursts -system.physmem.perBankRdBursts::15 938672 # Per bank write bursts -system.physmem.perBankWrBursts::0 6704 # Per bank write bursts -system.physmem.perBankWrBursts::1 6457 # Per bank write bursts -system.physmem.perBankWrBursts::2 6598 # Per bank write bursts -system.physmem.perBankWrBursts::3 6635 # Per bank write bursts -system.physmem.perBankWrBursts::4 6561 # Per bank write bursts -system.physmem.perBankWrBursts::5 6794 # Per bank write bursts -system.physmem.perBankWrBursts::6 6789 # Per bank write bursts -system.physmem.perBankWrBursts::7 6723 # Per bank write bursts -system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankRdBursts::13 943534 # Per bank write bursts +system.physmem.perBankRdBursts::14 939230 # Per bank write bursts +system.physmem.perBankRdBursts::15 938669 # Per bank write bursts +system.physmem.perBankWrBursts::0 6703 # Per bank write bursts +system.physmem.perBankWrBursts::1 6464 # Per bank write bursts +system.physmem.perBankWrBursts::2 6595 # Per bank write bursts +system.physmem.perBankWrBursts::3 6634 # Per bank write bursts +system.physmem.perBankWrBursts::4 6559 # Per bank write bursts +system.physmem.perBankWrBursts::5 6792 # Per bank write bursts +system.physmem.perBankWrBursts::6 6793 # Per bank write bursts +system.physmem.perBankWrBursts::7 6730 # Per bank write bursts +system.physmem.perBankWrBursts::8 7130 # Per bank write bursts system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6538 # Per bank write bursts -system.physmem.perBankWrBursts::11 6183 # Per bank write bursts -system.physmem.perBankWrBursts::12 7149 # Per bank write bursts -system.physmem.perBankWrBursts::13 6765 # Per bank write bursts -system.physmem.perBankWrBursts::14 7038 # Per bank write bursts -system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.perBankWrBursts::10 6539 # Per bank write bursts +system.physmem.perBankWrBursts::11 6181 # Per bank write bursts +system.physmem.perBankWrBursts::12 7151 # Per bank write bursts +system.physmem.perBankWrBursts::13 6766 # Per bank write bursts +system.physmem.perBankWrBursts::14 7035 # Per bank write bursts +system.physmem.perBankWrBursts::15 6897 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.totGap 2525130505500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 36 # Read request sizes (log2) @@ -109,26 +109,26 @@ system.physmem.writePktSize::2 754018 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59125 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59131 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -142,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see @@ -174,521 +174,534 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 358 0.42% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 154 0.18% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 62.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 15 0.02% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 31 0.04% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 11 0.01% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 39 0.05% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 368 0.43% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 15 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 165 0.19% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 92 0.11% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row 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-system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 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-system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 82 0.10% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 365 0.42% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 75 0.09% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 129 0.15% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38464-38471 1 0.00% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 14 0.02% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 267 0.31% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 140 0.16% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 70 0.08% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 351 0.41% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 129 0.15% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 76 0.09% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 2 0.00% 88.56% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 349 0.41% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 70 0.08% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 140 0.16% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 77 0.09% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 267 0.31% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 3 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 14 0.02% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 127 0.15% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 80 0.09% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 364 0.42% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 83 0.10% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 73 0.08% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 144 0.17% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 337 0.39% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 24 0.03% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 3 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 16 0.02% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 144 0.17% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 2 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 327 0.38% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 69 0.08% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 79 0.09% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 89 0.10% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation @@ -714,15 +727,15 @@ system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation -system.physmem.totQLat 365610387500 # Total ticks spent queuing -system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation +system.physmem.totQLat 365453646000 # Total ticks spent queuing +system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks -system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks +system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s @@ -732,14 +745,14 @@ system.physmem.busUtil 3.00 # Da system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing -system.physmem.readRowHits 14986740 # Number of row buffer hits during reads -system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing +system.physmem.readRowHits 14986798 # Number of row buffer hits during reads +system.physmem.writeRowHits 93332 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes -system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes +system.physmem.avgGap 158713.50 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -752,50 +765,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54899945 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149440 # Transaction distribution -system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.throughput 54900302 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149434 # Transaction distribution +system.membus.trans_dist::ReadResp 16149434 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59131 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131442 # Transaction distribution -system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution +system.membus.trans_dist::ReadExReq 131448 # Transaction distribution +system.membus.trans_dist::ReadExResp 131448 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630105 # Total data (bytes) +system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630489 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -803,7 +816,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.throughput 48285786 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -913,22 +926,22 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14384905 # Number of BP lookups -system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits +system.cpu.branchPred.lookups 14384927 # Number of BP lookups +system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986852 # DTB read hits -system.cpu.checker.dtb.read_misses 7306 # DTB read misses -system.cpu.checker.dtb.write_hits 11227410 # DTB write hits +system.cpu.checker.dtb.read_hits 14986834 # DTB read hits +system.cpu.checker.dtb.read_misses 7307 # DTB read misses +system.cpu.checker.dtb.write_hits 11227416 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -939,13 +952,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994158 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229601 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994141 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229607 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214262 # DTB hits -system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26223759 # DTB accesses -system.cpu.checker.itb.inst_hits 61479743 # ITB inst hits +system.cpu.checker.dtb.hits 26214250 # DTB hits +system.cpu.checker.dtb.misses 9498 # DTB misses +system.cpu.checker.dtb.accesses 26223748 # DTB accesses +system.cpu.checker.itb.inst_hits 61479663 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -962,36 +975,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484214 # ITB inst accesses -system.cpu.checker.itb.hits 61479743 # DTB hits +system.cpu.checker.itb.inst_accesses 61484134 # ITB inst accesses +system.cpu.checker.itb.hits 61479663 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61484214 # DTB accesses -system.cpu.checker.numCycles 77882535 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484134 # DTB accesses +system.cpu.checker.numCycles 77882476 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51179212 # DTB read hits -system.cpu.dtb.read_misses 64531 # DTB read misses -system.cpu.dtb.write_hits 11698539 # DTB write hits -system.cpu.dtb.write_misses 15837 # DTB write misses +system.cpu.dtb.read_hits 51182106 # DTB read hits +system.cpu.dtb.read_misses 64421 # DTB read misses +system.cpu.dtb.write_hits 11699698 # DTB write hits +system.cpu.dtb.write_misses 15824 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6568 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6560 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51243743 # DTB read accesses -system.cpu.dtb.write_accesses 11714376 # DTB write accesses +system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246527 # DTB read accesses +system.cpu.dtb.write_accesses 11715522 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62877751 # DTB hits -system.cpu.dtb.misses 80368 # DTB misses -system.cpu.dtb.accesses 62958119 # DTB accesses -system.cpu.itb.inst_hits 11513998 # ITB inst hits -system.cpu.itb.inst_misses 11344 # ITB inst misses +system.cpu.dtb.hits 62881804 # DTB hits +system.cpu.dtb.misses 80245 # DTB misses +system.cpu.dtb.accesses 62962049 # DTB accesses +system.cpu.itb.inst_hits 11522583 # ITB inst hits +system.cpu.itb.inst_misses 11276 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -1000,148 +1013,148 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4962 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4956 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11525342 # ITB inst accesses -system.cpu.itb.hits 11513998 # DTB hits -system.cpu.itb.misses 11344 # DTB misses -system.cpu.itb.accesses 11525342 # DTB accesses -system.cpu.numCycles 474882944 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11533859 # ITB inst accesses +system.cpu.itb.hits 11522583 # DTB hits +system.cpu.itb.misses 11276 # DTB misses +system.cpu.itb.accesses 11533859 # DTB accesses +system.cpu.numCycles 474898657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle +system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -1154,397 +1167,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued -system.cpu.iq.rate 0.258795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued +system.cpu.iq.rate 0.258806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221869 # number of nop insts executed -system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475076 # Number of branches executed -system.cpu.iew.exec_stores 12210518 # Number of stores executed -system.cpu.iew.exec_rate 0.254424 # Inst execution rate -system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47026181 # num instructions producing a value -system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value +system.cpu.iew.exec_nop 221761 # number of nop insts executed +system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475005 # Number of branches executed +system.cpu.iew.exec_stores 12211635 # Number of stores executed +system.cpu.iew.exec_rate 0.254432 # Inst execution rate +system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47031033 # num instructions producing a value +system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456137 # Number of instructions committed -system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456059 # Number of instructions committed +system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385736 # Number of memory references committed -system.cpu.commit.loads 15654008 # Number of loads committed -system.cpu.commit.membars 403573 # Number of memory barriers committed -system.cpu.commit.branches 9961077 # Number of branches committed +system.cpu.commit.refs 27385723 # Number of memory references committed +system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 9961071 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. -system.cpu.commit.function_calls 991208 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. +system.cpu.commit.function_calls 991207 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240636318 # The number of ROB reads -system.cpu.rob.rob_writes 195934369 # The number of ROB writes -system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305756 # Number of Instructions Simulated -system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated -system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547208472 # number of integer regfile reads -system.cpu.int_regfile_writes 87526189 # number of integer regfile writes -system.cpu.fp_regfile_reads 8624 # number of floating regfile reads -system.cpu.fp_regfile_writes 3008 # number of floating regfile writes -system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.rob.rob_reads 240665808 # The number of ROB reads +system.cpu.rob.rob_writes 195946920 # The number of ROB writes +system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305678 # Number of Instructions Simulated +system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated +system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547244885 # number of integer regfile reads +system.cpu.int_regfile_writes 87532646 # number of integer regfile writes +system.cpu.fp_regfile_reads 8511 # number of floating regfile reads +system.cpu.fp_regfile_writes 2972 # number of floating regfile writes +system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution +system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980741 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 980798 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits -system.cpu.icache.overall_hits::total 10449649 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses -system.cpu.icache.overall_misses::total 1060761 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits +system.cpu.icache.overall_hits::total 10457750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses +system.cpu.icache.overall_misses::total 1061214 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits 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0.012589 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377712817 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383900066 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015983 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092607 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092607 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.515972 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63422.125669 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61918.540746 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63471.335270 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63471.335270 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency 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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.replacements 643483 # number of replacements system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits 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ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits 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+system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks -system.cpu.dcache.writebacks::total 607699 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks +system.cpu.dcache.writebacks::total 607897 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1841,16 +1854,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 7ff8826e3..98e6f2256 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,18 +602,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -581,6 +647,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -645,6 +713,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -660,6 +729,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -682,18 +752,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -702,15 +775,18 @@ port=system.toL2Bus.slave[7] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -719,16 +795,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -737,22 +816,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -761,22 +844,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -785,10 +872,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -797,124 +886,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -923,10 +1033,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -935,16 +1047,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -953,10 +1068,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -967,6 +1084,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -989,14 +1107,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -1015,31 +1136,37 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -1052,6 +1179,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1074,6 +1202,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1083,6 +1212,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1105,6 +1235,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1112,6 +1243,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1123,6 +1255,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1149,6 +1282,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1160,19 +1294,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1182,6 +1320,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -1191,6 +1330,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1219,6 +1359,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -1228,8 +1369,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1241,6 +1414,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -1256,6 +1430,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -1270,6 +1446,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1279,6 +1456,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1300,8 +1478,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1310,6 +1490,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1320,6 +1501,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1330,6 +1512,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1340,6 +1523,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1354,6 +1538,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1367,6 +1552,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1384,6 +1570,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1396,6 +1583,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1407,6 +1595,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1417,6 +1606,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1429,6 +1619,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1442,6 +1633,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1452,6 +1644,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1462,6 +1655,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1472,6 +1666,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1484,6 +1679,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1498,6 +1694,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1510,6 +1707,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1524,6 +1722,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1534,6 +1733,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1544,6 +1744,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1554,6 +1755,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1562,6 +1764,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1570,6 +1773,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1579,11 +1783,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 22f0dd0ff..fbdae72ae 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.104766 # Number of seconds simulated -sim_ticks 1104765949000 # Number of ticks simulated -final_tick 1104765949000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1104766159000 # Number of ticks simulated +final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62642 # Simulator instruction rate (inst/s) -host_op_rate 80640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1123477436 # Simulator tick rate (ticks/s) -host_mem_usage 430892 # Number of bytes of host memory used -host_seconds 983.35 # Real time elapsed on the host -sim_insts 61598253 # Number of instructions simulated -sim_ops 79296895 # Number of ops (including micro ops) simulated +host_inst_rate 49697 # Simulator instruction rate (inst/s) +host_op_rate 63978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 891289209 # Simulator tick rate (ticks/s) +host_mem_usage 450492 # Number of bytes of host memory used +host_seconds 1239.51 # Real time elapsed on the host +sim_insts 61600257 # Number of instructions simulated +sim_ops 79301805 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4366132 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5251248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4268480 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu0.inst 409280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7295824 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294864 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6378 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6357 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66695 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 66680 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823531 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44134945 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823516 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44134936 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 369483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3952088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4753267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53579613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 369483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 737749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3863696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4752513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53579603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 737807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3862827 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6603954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3863696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44134945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 6603084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3862827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44134936 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 369483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3967476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7478138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60183567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3968054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7477383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60182687 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 6257980 # Number of read requests accepted -system.physmem.writeReqs 823531 # Number of write requests accepted +system.physmem.writeReqs 823516 # Number of write requests accepted system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823531 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 398200448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2310272 # Total number of bytes read from write queue -system.physmem.bytesWritten 7402624 # Total number of bytes written to DRAM +system.physmem.writeBursts 823516 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 398158784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2351936 # Total number of bytes read from write queue +system.physmem.bytesWritten 7399168 # Total number of bytes written to DRAM system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7295824 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 36098 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707850 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12605 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 391110 # Per bank write bursts -system.physmem.perBankRdBursts::1 390863 # Per bank write bursts -system.physmem.perBankRdBursts::2 386866 # Per bank write bursts -system.physmem.perBankRdBursts::3 386878 # Per bank write bursts -system.physmem.perBankRdBursts::4 391778 # Per bank write bursts -system.physmem.perBankRdBursts::5 391417 # Per bank write bursts -system.physmem.perBankRdBursts::6 386925 # Per bank write bursts -system.physmem.perBankRdBursts::7 386783 # Per bank write bursts -system.physmem.perBankRdBursts::8 391442 # Per bank write bursts -system.physmem.perBankRdBursts::9 391216 # Per bank write bursts -system.physmem.perBankRdBursts::10 386574 # Per bank write bursts -system.physmem.perBankRdBursts::11 385570 # Per bank write bursts -system.physmem.perBankRdBursts::12 390981 # Per bank write bursts -system.physmem.perBankRdBursts::13 390596 # Per bank write bursts -system.physmem.perBankRdBursts::14 386700 # Per bank write bursts -system.physmem.perBankRdBursts::15 386183 # Per bank write bursts -system.physmem.perBankWrBursts::0 7188 # Per bank write bursts -system.physmem.perBankWrBursts::1 7193 # Per bank write bursts -system.physmem.perBankWrBursts::2 7297 # Per bank write bursts -system.physmem.perBankWrBursts::3 7231 # Per bank write bursts -system.physmem.perBankWrBursts::4 7835 # Per bank write bursts -system.physmem.perBankWrBursts::5 7450 # Per bank write bursts -system.physmem.perBankWrBursts::6 7370 # Per bank write bursts -system.physmem.perBankWrBursts::7 7176 # Per bank write bursts -system.physmem.perBankWrBursts::8 7508 # Per bank write bursts -system.physmem.perBankWrBursts::9 7517 # Per bank write bursts -system.physmem.perBankWrBursts::10 6849 # Per bank write bursts -system.physmem.perBankWrBursts::11 6596 # Per bank write bursts -system.physmem.perBankWrBursts::12 7160 # Per bank write bursts -system.physmem.perBankWrBursts::13 6824 # Per bank write bursts -system.physmem.perBankWrBursts::14 7287 # Per bank write bursts -system.physmem.perBankWrBursts::15 7185 # Per bank write bursts +system.physmem.bytesWrittenSys 7294864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36749 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707898 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12570 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 391105 # Per bank write bursts +system.physmem.perBankRdBursts::1 391040 # Per bank write bursts +system.physmem.perBankRdBursts::2 387008 # Per bank write bursts +system.physmem.perBankRdBursts::3 386856 # Per bank write bursts +system.physmem.perBankRdBursts::4 391768 # Per bank write bursts +system.physmem.perBankRdBursts::5 391357 # Per bank write bursts +system.physmem.perBankRdBursts::6 387221 # Per bank write bursts +system.physmem.perBankRdBursts::7 386642 # Per bank write bursts +system.physmem.perBankRdBursts::8 391438 # Per bank write bursts +system.physmem.perBankRdBursts::9 391160 # Per bank write bursts +system.physmem.perBankRdBursts::10 385906 # Per bank write bursts +system.physmem.perBankRdBursts::11 385319 # Per bank write bursts +system.physmem.perBankRdBursts::12 390977 # Per bank write bursts +system.physmem.perBankRdBursts::13 390642 # Per bank write bursts +system.physmem.perBankRdBursts::14 386557 # Per bank write bursts +system.physmem.perBankRdBursts::15 386235 # Per bank write bursts +system.physmem.perBankWrBursts::0 7173 # Per bank write bursts +system.physmem.perBankWrBursts::1 7194 # Per bank write bursts +system.physmem.perBankWrBursts::2 7298 # Per bank write bursts +system.physmem.perBankWrBursts::3 7217 # Per bank write bursts +system.physmem.perBankWrBursts::4 7815 # Per bank write bursts +system.physmem.perBankWrBursts::5 7451 # Per bank write bursts +system.physmem.perBankWrBursts::6 7359 # Per bank write bursts +system.physmem.perBankWrBursts::7 7185 # Per bank write bursts +system.physmem.perBankWrBursts::8 7499 # Per bank write bursts +system.physmem.perBankWrBursts::9 7507 # Per bank write bursts +system.physmem.perBankWrBursts::10 6838 # Per bank write bursts +system.physmem.perBankWrBursts::11 6616 # Per bank write bursts +system.physmem.perBankWrBursts::12 7156 # Per bank write bursts +system.physmem.perBankWrBursts::13 6834 # Per bank write bursts +system.physmem.perBankWrBursts::14 7291 # Per bank write bursts +system.physmem.perBankWrBursts::15 7179 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1104764856500 # Total gap between requests +system.physmem.totGap 1104765054500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 105 # Read request sizes (log2) @@ -126,29 +126,29 @@ system.physmem.writePktSize::2 756836 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66695 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 548369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 494073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 445478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1468713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1058783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1047686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1043195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 25416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66680 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 551365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 495534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 447275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1468617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1056766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1046048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1041328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,547 +159,563 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5702.673097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 368.783347 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 12967.835637 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25909 36.43% 36.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14850 20.88% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3162 4.45% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2234 3.14% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1545 2.17% 67.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1302 1.83% 68.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 996 1.40% 70.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1191 1.67% 71.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 629 0.88% 72.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 663 0.93% 73.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 567 0.80% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 536 0.75% 75.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 288 0.40% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 263 0.37% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 175 0.25% 76.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 373 0.52% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 125 0.18% 77.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 132 0.19% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 91 0.13% 77.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 197 0.28% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 57 0.08% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 541 0.76% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 41 0.06% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 225 0.32% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 27 0.04% 78.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 110 0.15% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 22 0.03% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 16 0.02% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 61 0.09% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 267 0.38% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 16 0.02% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 40 0.06% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 17 0.02% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 50 0.07% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 11 0.02% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 22 0.03% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 43 0.06% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 4 0.01% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 15 0.02% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 8 0.01% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 32 0.04% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 30 0.04% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 157 0.22% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 6 0.01% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 17 0.02% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 2 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 36 0.05% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 17 0.02% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 8 0.01% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 39 0.05% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 6 0.01% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 181 0.25% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 9 0.01% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 12 0.02% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 12 0.02% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 102 0.14% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 17 0.02% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 25 0.04% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 11 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 5 0.01% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 19 0.03% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 161 0.23% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 9 0.01% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 14 0.02% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 3 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 16 0.02% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 18 0.03% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 5 0.01% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 8 0.01% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 5 0.01% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 150 0.21% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 2 0.00% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.02% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 13 0.02% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 95 0.13% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 7 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 23 0.03% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 70891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5720.862056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 370.371771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 12983.455583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25780 36.37% 36.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14831 20.92% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3170 4.47% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2175 3.07% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1493 2.11% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1297 1.83% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1053 1.49% 70.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1149 1.62% 71.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 657 0.93% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 651 0.92% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 556 0.78% 74.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 523 0.74% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 304 0.43% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 266 0.38% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 142 0.20% 76.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 425 0.60% 76.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 119 0.17% 77.01% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::36864-36871 174 0.25% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 72 0.10% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 7 0.01% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 17 0.02% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37696-37703 2 0.00% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 76 0.11% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 72 0.10% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.67% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::40128-40135 1 0.00% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 82 0.12% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40263 1 0.00% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 23 0.03% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40896-40903 1 0.00% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 150 0.21% 94.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41024-41031 1 0.00% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41088-41095 1 0.00% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 2 0.00% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 70 0.10% 94.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 82 0.12% 94.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41792-41799 1 0.00% 94.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 16 0.02% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 13 0.02% 94.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 66 0.09% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 92 0.13% 95.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42880-42887 2 0.00% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 82 0.12% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 90 0.13% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43392-43399 1 0.00% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 4 0.01% 95.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 144 0.20% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 2 0.00% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 2 0.00% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 5 0.01% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 85 0.12% 95.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 155 0.22% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 16 0.02% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 96.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45504-45511 2 0.00% 96.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 71 0.10% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 2 0.00% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 19 0.03% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 138 0.19% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 14 0.02% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 15 0.02% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 10 0.01% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 214 0.30% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 31 0.04% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 15 0.02% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 70 0.10% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 146 0.21% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 10 0.01% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 20 0.03% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48832-48839 2 0.00% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 13 0.02% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 1979 2.78% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 75 0.11% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 86 0.12% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 74 0.10% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 73 0.10% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 3 0.00% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 16 0.02% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 9 0.01% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 74 0.10% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 4 0.01% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 173 0.24% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 19 0.03% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 34 0.05% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 76 0.11% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 150 0.21% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 8 0.01% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 9 0.01% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 17 0.02% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 174 0.25% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 22 0.03% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 2 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 3 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 21 0.03% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 208 0.29% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 12 0.02% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 4 0.01% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 10 0.01% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2000 2.82% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50311 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50887 4 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51719 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51904-51911 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52352-52359 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52672-52679 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71125 # Bytes accessed per row activation -system.physmem.totQLat 151840872500 # Total ticks spent queuing -system.physmem.totMemAccLat 191562815000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 31109410000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8612532500 # Total ticks spent accessing banks -system.physmem.avgQLat 24404.33 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1384.23 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 70891 # Bytes accessed per row activation +system.physmem.totQLat 151784626000 # Total ticks spent queuing +system.physmem.totMemAccLat 191524282250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 31106155000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8633501250 # Total ticks spent accessing banks +system.physmem.avgQLat 24397.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1387.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30788.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30785.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s @@ -708,14 +724,14 @@ system.physmem.busUtil 2.87 # Da system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.06 # Average write queue length when enqueuing -system.physmem.readRowHits 6168484 # Number of row buffer hits during reads -system.physmem.writeRowHits 97939 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.13 # Average write queue length when enqueuing +system.physmem.readRowHits 6167948 # Number of row buffer hits during reads +system.physmem.writeRowHits 98004 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.66 # Row buffer hit rate for writes -system.physmem.avgGap 156006.94 # Average gap between requests +system.physmem.writeRowHitRate 84.77 # Row buffer hit rate for writes +system.physmem.avgGap 156007.30 # Average gap between requests system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 3.92 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 3.90 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -734,286 +750,286 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 62369736 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306752 # Transaction distribution -system.membus.trans_dist::ReadResp 7306752 # Transaction distribution -system.membus.trans_dist::WriteReq 767894 # Transaction distribution -system.membus.trans_dist::WriteResp 767894 # Transaction distribution -system.membus.trans_dist::Writeback 66695 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33888 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17695 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12605 # Transaction distribution -system.membus.trans_dist::ReadExReq 138070 # Transaction distribution -system.membus.trans_dist::ReadExResp 137680 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382518 # Packet count per connected master and slave (bytes) +system.membus.throughput 62368825 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306736 # Transaction distribution +system.membus.trans_dist::ReadResp 7306736 # Transaction distribution +system.membus.trans_dist::WriteReq 767886 # Transaction distribution +system.membus.trans_dist::WriteResp 767886 # Transaction distribution +system.membus.trans_dist::Writeback 66680 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33856 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17703 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12570 # Transaction distribution +system.membus.trans_dist::ReadExReq 138080 # Transaction distribution +system.membus.trans_dist::ReadExResp 137692 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382504 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366229 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366129 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555925 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389781 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555825 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389767 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23264 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729972 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20145177 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729012 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20144183 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68903961 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68903961 # Total data (bytes) +system.membus.tot_pkt_size::total 68902967 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68902967 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487006499 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486954500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9880000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9891500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 749500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 747500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8612723499 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8614133500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4837509170 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4838543340 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13760375954 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) system.l2c.tags.replacements 72740 # number of replacements -system.l2c.tags.tagsinuse 53853.567584 # Cycle average of tags in use -system.l2c.tags.total_refs 1839137 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use +system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.334423 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 13.325933 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39512.680536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.162068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257969 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4009.847433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2829.767621 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.955070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3709.355619 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3778.541270 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602916 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061185 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057656 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821740 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22065 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386342 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30647 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5089 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198399 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403772 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581386 # number of Writeback hits -system.l2c.Writeback_hits::total 581386 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2084 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48317 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58643 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22065 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386342 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214931 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5089 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 590258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 257042 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510732 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22065 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386342 # number of overall hits -system.l2c.overall_hits::cpu0.data 214931 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30647 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5089 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590258 # number of overall hits -system.l2c.overall_hits::cpu1.data 257042 # number of overall hits -system.l2c.overall_hits::total 1510732 # number of overall hits +system.l2c.tags.occ_blocks::writebacks 39518.362493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.391068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.010261 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4016.186215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2832.215798 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.504423 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3702.179063 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3777.323870 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.603002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043216 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000130 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056491 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057637 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821841 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22002 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4348 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 385872 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166544 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 31083 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5052 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589425 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198327 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1402653 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581363 # number of Writeback hits +system.l2c.Writeback_hits::total 581363 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1344 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq 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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63156.973522 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65507.251603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62685.936512 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.485283 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10089.113917 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.462688 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.555730 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.934625 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10033.371429 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57735.641497 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69024.341151 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63933.038618 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171110152435 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184524186173 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036720 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030405 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017630 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.792848 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836509 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.810762 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.756272 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753758 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566902 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567738 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567361 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098774 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098774 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62578.188661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65201.487138 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62839.467228 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.691291 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10093.271186 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10051.992377 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.216430 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10048.609524 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10028.535613 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57372.440322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68943.264778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63723.943645 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1204,61 +1220,61 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 136691596 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2708551 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2708550 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581386 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33382 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18023 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51405 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258959 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258959 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785985 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1193885 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4802054 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14684 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 71694 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8011498 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25134272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847315 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17444 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38184256 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47797126 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20356 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 122632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146211713 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146211713 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4800508 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4894625900 # Layer occupancy (ticks) +system.toL2Bus.throughput 136617428 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2707473 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2707472 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767886 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767886 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 581363 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33341 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18047 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51388 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258982 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258982 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785116 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073701 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13590 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55763 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1192186 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72416 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8009257 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25105344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847157 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17404 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88060 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38129856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47787842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 124384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146120255 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146120255 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4810056 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4893985918 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1771371395 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1769514129 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1514575770 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1514543493 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9208452 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9260456 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34011429 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33892454 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2689519761 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2685747678 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3237226447 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3237154790 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9617950 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9609448 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41300207 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41592193 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46298101 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution -system.iobus.trans_dist::WriteReq 7950 # Transaction distribution -system.iobus.trans_dist::WriteResp 7950 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) +system.iobus.throughput 46298079 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278155 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278155 # Transaction distribution +system.iobus.trans_dist::WriteReq 7945 # Transaction distribution +system.iobus.trans_dist::WriteResp 7945 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30446 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) @@ -1281,11 +1297,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382504 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572214 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 14572200 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40164 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) @@ -1308,12 +1324,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389767 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148565 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148565 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 51148551 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148551 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21348000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1361,42 +1377,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374568000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374559000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16664438046 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16664463058 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6002691 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4577903 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294712 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3771820 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2913648 # Number of BTB hits +system.cpu0.branchPred.lookups 5998612 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4575425 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295221 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3794321 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2910648 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.247801 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672509 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28479 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.710642 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672923 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29222 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8905508 # DTB read hits -system.cpu0.dtb.read_misses 28991 # DTB read misses -system.cpu0.dtb.write_hits 5140500 # DTB write hits -system.cpu0.dtb.write_misses 5723 # DTB write misses +system.cpu0.dtb.read_hits 8906772 # DTB read hits +system.cpu0.dtb.read_misses 28714 # DTB read misses +system.cpu0.dtb.write_hits 5141355 # DTB write hits +system.cpu0.dtb.write_misses 5491 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1824 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 969 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 924 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 556 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8934499 # DTB read accesses -system.cpu0.dtb.write_accesses 5146223 # DTB write accesses +system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8935486 # DTB read accesses +system.cpu0.dtb.write_accesses 5146846 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14046008 # DTB hits -system.cpu0.dtb.misses 34714 # DTB misses -system.cpu0.dtb.accesses 14080722 # DTB accesses -system.cpu0.itb.inst_hits 4219281 # ITB inst hits -system.cpu0.itb.inst_misses 5089 # ITB inst misses +system.cpu0.dtb.hits 14048127 # DTB hits +system.cpu0.dtb.misses 34205 # DTB misses +system.cpu0.dtb.accesses 14082332 # DTB accesses +system.cpu0.itb.inst_hits 4217878 # ITB inst hits +system.cpu0.itb.inst_misses 5102 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1405,530 +1421,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1343 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1349 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1465 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4224370 # ITB inst accesses -system.cpu0.itb.hits 4219281 # DTB hits -system.cpu0.itb.misses 5089 # DTB misses -system.cpu0.itb.accesses 4224370 # DTB accesses -system.cpu0.numCycles 69432037 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4222980 # ITB inst accesses +system.cpu0.itb.hits 4217878 # DTB hits +system.cpu0.itb.misses 5102 # DTB misses +system.cpu0.itb.accesses 4222980 # DTB accesses +system.cpu0.numCycles 69399845 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11713503 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32019404 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6002691 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3586157 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7516730 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1449804 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61386 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19631994 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46872 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1335943 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4217707 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157539 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41351812 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.000563 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.381156 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11707943 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32011744 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5998612 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3583571 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450698 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61322 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19616707 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4844 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46699 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1334001 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4216315 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157019 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2077 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41328581 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.001115 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381687 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33842541 81.84% 81.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565579 1.37% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816874 1.98% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676358 1.64% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772843 1.87% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558608 1.35% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669211 1.62% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351371 0.85% 92.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098427 7.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33820062 81.83% 81.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 563590 1.36% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816833 1.98% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 678550 1.64% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773451 1.87% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557877 1.35% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 667950 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351268 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3099000 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41351812 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086454 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461162 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12216999 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20826551 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6820783 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 510850 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 976629 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935170 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64759 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40012064 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213022 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 976629 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12786291 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5985032 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12800887 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6711570 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2091403 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38907337 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435425 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1163203 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39252215 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175728295 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 161804372 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3955 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30935092 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8317122 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411284 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370379 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5367119 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7645996 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5688511 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1121166 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1220161 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36823164 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895382 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37236653 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80347 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6279547 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13158300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256522 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41351812 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.900484 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514831 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41328581 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086436 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461265 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12211654 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20807916 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6822131 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 509652 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977228 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934234 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64577 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40012411 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212282 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977228 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12781253 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5974864 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12788176 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6710782 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2096278 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38908722 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1870 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435924 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1167673 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 74 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39248766 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175739111 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 161807828 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3998 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30938690 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8310075 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411292 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370393 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5377655 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7648768 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5690459 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124911 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1238842 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36825251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895403 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37248866 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80758 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6273186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13119240 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256527 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41328581 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901286 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.515261 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26282952 63.56% 63.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5688374 13.76% 77.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3116432 7.54% 84.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2466494 5.96% 90.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2112034 5.11% 95.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 939185 2.27% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 506930 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184996 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54415 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26256934 63.53% 63.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5686623 13.76% 77.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3113893 7.53% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2469463 5.98% 90.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128203 5.15% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 923425 2.23% 98.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 509489 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185211 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 55340 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41351812 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41328581 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27736 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.04% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842113 78.49% 81.12% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202594 18.88% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26660 2.48% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 451 0.04% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 843359 78.54% 81.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 203361 18.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22326150 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46947 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22336119 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46932 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9362954 25.14% 85.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5447671 14.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9364529 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5448283 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37236653 # Type of FU issued -system.cpu0.iq.rate 0.536304 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1072896 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028813 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117004426 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44005967 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34332716 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8422 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4624 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3857 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38252914 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4421 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307648 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37248866 # Type of FU issued +system.cpu0.iq.rate 0.536728 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1073831 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028829 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117006401 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44001611 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34345325 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8483 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4644 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3871 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38265951 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4467 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306869 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1368398 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2491 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13086 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537466 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1369766 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2413 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12945 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 538318 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192854 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5939 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192768 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5933 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 976629 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4337522 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 100010 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37836354 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83498 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7645996 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5688511 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571219 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39755 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6621 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13086 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149491 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117486 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266977 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36859042 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9220953 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 377611 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977228 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4326370 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 99368 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37837801 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83554 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7648768 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5690459 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571361 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39650 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5884 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12945 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150463 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117241 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267704 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36870822 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9222297 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 378044 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117808 # number of nop insts executed -system.cpu0.iew.exec_refs 14621413 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4853789 # Number of branches executed -system.cpu0.iew.exec_stores 5400460 # Number of stores executed -system.cpu0.iew.exec_rate 0.530865 # Inst execution rate -system.cpu0.iew.wb_sent 36664720 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34336573 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18306413 # num instructions producing a value -system.cpu0.iew.wb_consumers 35193198 # num instructions consuming a value +system.cpu0.iew.exec_nop 117147 # number of nop insts executed +system.cpu0.iew.exec_refs 14623543 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4855012 # Number of branches executed +system.cpu0.iew.exec_stores 5401246 # Number of stores executed +system.cpu0.iew.exec_rate 0.531281 # Inst execution rate +system.cpu0.iew.wb_sent 36677243 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34349196 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18314277 # num instructions producing a value +system.cpu0.iew.wb_consumers 35200184 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.494535 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520169 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.494946 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520289 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6085996 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638860 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231074 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40375183 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775004 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.739173 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6083137 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638876 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231723 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40351353 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775579 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.741147 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28737053 71.18% 71.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5697190 14.11% 85.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1882101 4.66% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 980199 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 786708 1.95% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 526531 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 398386 0.99% 96.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 216969 0.54% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1150046 2.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28712298 71.16% 71.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5699883 14.13% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1888088 4.68% 89.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 980743 2.43% 92.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 789976 1.96% 94.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 505077 1.25% 95.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395357 0.98% 96.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 219519 0.54% 97.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1160412 2.88% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40375183 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23683551 # Number of instructions committed -system.cpu0.commit.committedOps 31290943 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40351353 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23685352 # Number of instructions committed +system.cpu0.commit.committedOps 31295648 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11428643 # Number of memory references committed -system.cpu0.commit.loads 6277598 # Number of loads committed -system.cpu0.commit.membars 229694 # Number of memory barriers committed -system.cpu0.commit.branches 4245889 # Number of branches committed +system.cpu0.commit.refs 11431143 # Number of memory references committed +system.cpu0.commit.loads 6279002 # Number of loads committed +system.cpu0.commit.membars 229688 # Number of memory barriers committed +system.cpu0.commit.branches 4246153 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27646853 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489416 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1150046 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27651273 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489419 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1160412 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75750709 # The number of ROB reads -system.cpu0.rob.rob_writes 75732466 # The number of ROB writes -system.cpu0.timesIdled 364061 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28080225 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2140058132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23602809 # Number of Instructions Simulated -system.cpu0.committedOps 31210201 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23602809 # Number of Instructions Simulated -system.cpu0.cpi 2.941685 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.941685 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.339941 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.339941 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171807193 # number of integer regfile reads -system.cpu0.int_regfile_writes 34081987 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3237 # number of floating regfile reads -system.cpu0.fp_regfile_writes 886 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13003191 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451099 # number of misc regfile writes -system.cpu0.icache.tags.replacements 392605 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.965142 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3793600 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393117 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.650053 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7051834000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.965142 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997979 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997979 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3793600 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3793600 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3793600 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3793600 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3793600 # number of overall hits -system.cpu0.icache.overall_hits::total 3793600 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423979 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423979 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423979 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423979 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423979 # number of overall misses -system.cpu0.icache.overall_misses::total 423979 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5892352014 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5892352014 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5892352014 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5892352014 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5892352014 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5892352014 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4217579 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4217579 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4217579 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4217579 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4217579 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4217579 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100527 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100527 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100527 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100527 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100527 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100527 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.744969 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.744969 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13897.744969 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13897.744969 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3802 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75718589 # The number of ROB reads +system.cpu0.rob.rob_writes 75736714 # The number of ROB writes +system.cpu0.timesIdled 363087 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28071264 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2140090760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23604610 # Number of Instructions Simulated +system.cpu0.committedOps 31214906 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23604610 # Number of Instructions Simulated +system.cpu0.cpi 2.940097 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.940097 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.340125 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.340125 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171854579 # number of integer regfile reads +system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads +system.cpu0.fp_regfile_writes 904 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13012931 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451079 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392190 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 392702 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.656758 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7054061250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3792228 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3792228 # number of overall hits +system.cpu0.icache.overall_hits::total 3792228 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423961 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423961 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423961 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423961 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423961 # number of overall misses +system.cpu0.icache.overall_misses::total 423961 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5895815248 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5895815248 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5895815248 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5895815248 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5895815248 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5895815248 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4216189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4216189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4216189 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4216189 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4216189 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4216189 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13906.503777 # average ReadReq miss latency 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blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.362069 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30839 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30839 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30839 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30839 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30839 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30839 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393140 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393140 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393140 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393140 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393140 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393140 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4794002596 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4794002596 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4794002596 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4794002596 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4794002596 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4794002596 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093215 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093215 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093215 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12194.135921 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31238 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31238 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31238 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31238 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31238 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31238 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392723 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 392723 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 392723 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 392723 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 392723 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 392723 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4798060362 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4798060362 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4798060362 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4798060362 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4798060362 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4798060362 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093146 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093146 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093146 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.416250 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 276287 # number of replacements -system.cpu0.dcache.tags.tagsinuse 459.684046 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9258198 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276799 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.447368 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 276315 # number of replacements +system.cpu0.dcache.tags.tagsinuse 459.475838 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9261350 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276827 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.455371 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 43491250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.684046 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897820 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.897820 # Average percentage of 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blocked -system.cpu0.dcache.blocked::no_mshrs 609 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.568144 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 78.442748 # average number of cycles each access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.475838 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.897414 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5781234 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5781234 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3158881 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3158881 # number of WriteReq hits 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0.181102 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181102 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181102 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14108.118468 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14108.118468 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50233.162540 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50233.162540 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10346.271621 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10346.271621 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6147.486204 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6147.486204 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43084.696471 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43084.696471 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10884 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 8688 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 601 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.109817 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 67.875000 # average number of cycles each access was blocked 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(read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319286 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319286 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319286 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2419086873 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2419086873 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5310990170 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5310990170 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68672765 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68672765 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30919365 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30919365 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7730077043 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7730077043 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7730077043 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7730077043 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504888791 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504888791 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131913883 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131913883 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636802674 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636802674 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030598 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030598 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.writebacks::writebacks 256502 # number of writebacks +system.cpu0.dcache.writebacks::total 256502 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202469 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202469 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455378 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1455378 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657847 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657847 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657847 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657847 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188768 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188768 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130516 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130516 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8280 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8280 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7466 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7466 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319284 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319284 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319284 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319284 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2415025620 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2415025620 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5290299960 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5290299960 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68915513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68915513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30963868 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30963868 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7705325580 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7705325580 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7705325580 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7705325580 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504357282 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504357282 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131166881 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131166881 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14635524163 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14635524163 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030582 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030582 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056029 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056029 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029255 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029255 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12812.892268 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12812.892268 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40701.921064 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40701.921064 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8288.806880 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.806880 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4150.807491 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4150.807491 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029246 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029246 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12793.617668 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12793.617668 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40533.727359 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40533.727359 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8323.129589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8323.129589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4147.316903 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4147.316903 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1936,38 +1952,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8781819 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7169373 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 406881 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5765537 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4953289 # Number of BTB hits +system.cpu1.branchPred.lookups 8777296 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7163659 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407085 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5785994 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4951432 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.912015 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772113 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42948 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.576169 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 773226 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42749 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42694682 # DTB read hits -system.cpu1.dtb.read_misses 36199 # DTB read misses -system.cpu1.dtb.write_hits 6825983 # DTB write hits -system.cpu1.dtb.write_misses 10603 # DTB write misses +system.cpu1.dtb.read_hits 42697243 # DTB read hits +system.cpu1.dtb.read_misses 36228 # DTB read misses +system.cpu1.dtb.write_hits 6821056 # DTB write hits +system.cpu1.dtb.write_misses 10680 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2691 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 287 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2016 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2677 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 664 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42730881 # DTB read accesses -system.cpu1.dtb.write_accesses 6836586 # DTB write accesses +system.cpu1.dtb.perms_faults 642 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42733471 # DTB read accesses +system.cpu1.dtb.write_accesses 6831736 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49520665 # DTB hits -system.cpu1.dtb.misses 46802 # DTB misses -system.cpu1.dtb.accesses 49567467 # DTB accesses -system.cpu1.itb.inst_hits 7578103 # ITB inst hits -system.cpu1.itb.inst_misses 5415 # ITB inst misses +system.cpu1.dtb.hits 49518299 # DTB hits +system.cpu1.dtb.misses 46908 # DTB misses +system.cpu1.dtb.accesses 49565207 # DTB accesses +system.cpu1.itb.inst_hits 7578630 # ITB inst hits +system.cpu1.itb.inst_misses 5358 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1976,114 +1992,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1496 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1501 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7583518 # ITB inst accesses -system.cpu1.itb.hits 7578103 # DTB hits -system.cpu1.itb.misses 5415 # DTB misses -system.cpu1.itb.accesses 7583518 # DTB accesses -system.cpu1.numCycles 409882606 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583988 # ITB inst accesses +system.cpu1.itb.hits 7578630 # DTB hits +system.cpu1.itb.misses 5358 # DTB misses +system.cpu1.itb.accesses 7583988 # DTB accesses +system.cpu1.numCycles 409868912 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18878139 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60299044 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8781819 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5725402 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13123323 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3309042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63154 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78443797 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42366 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1440662 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7576329 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 547353 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2737 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114261108 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.645293 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.969526 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18867977 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60276924 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8777296 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5724658 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13120224 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3305222 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63128 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78446194 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5050 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41923 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1438516 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7576833 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 547191 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2712 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114243922 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.645142 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.969298 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101145087 88.52% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796077 0.70% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 936773 0.82% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1687391 1.48% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1395150 1.22% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 571856 0.50% 93.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1930284 1.69% 94.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 409373 0.36% 95.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5389117 4.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101131185 88.52% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796172 0.70% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937688 0.82% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1689020 1.48% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1395475 1.22% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 568258 0.50% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1928403 1.69% 94.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410429 0.36% 95.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5387292 4.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114261108 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021425 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.147113 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20196476 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 79405562 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11967958 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523276 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2167836 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1103528 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98181 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69822224 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 326370 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2167836 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21386304 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34427825 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40782107 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11206546 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4290490 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 65904089 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18821 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 671145 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3046869 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 355 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69217965 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 302501585 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 280690851 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6493 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49057579 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20160386 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444741 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387793 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7877859 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12590402 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7938263 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1041211 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1447247 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60694774 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157845 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87723814 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94478 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13427979 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 35976172 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277080 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114261108 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.767749 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513486 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114243922 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021415 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147064 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20194584 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 79395702 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11966487 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 522966 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2164183 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1104463 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98170 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69803405 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327162 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2164183 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21384110 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34428627 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40773355 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11205851 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4287796 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65891244 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18827 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 669159 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3045569 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1057 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69207054 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302452168 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 280640301 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6501 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49057788 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20149266 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444930 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388060 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7871220 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12589854 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7931577 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1030582 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1486229 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60667262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158299 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87712047 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93594 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13406861 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35899906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277508 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114243922 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.767761 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513174 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84436887 73.90% 73.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8271726 7.24% 81.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4125209 3.61% 84.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3692140 3.23% 87.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10373138 9.08% 97.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1967895 1.72% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1041724 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 276233 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 76156 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84413448 73.89% 73.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8278708 7.25% 81.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4125885 3.61% 84.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3695285 3.23% 87.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10373691 9.08% 97.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966586 1.72% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1039954 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 274624 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75741 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114261108 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114243922 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32226 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 994 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32139 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 997 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -2111,13 +2127,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7551636 95.89% 96.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 290793 3.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551678 95.88% 96.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 291209 3.70% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36606472 41.73% 42.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59249 0.07% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36599204 41.73% 42.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59264 0.07% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued @@ -2130,376 +2146,376 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43568189 49.67% 91.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7174305 8.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43568617 49.67% 91.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7169368 8.17% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87723814 # Type of FU issued -system.cpu1.iq.rate 0.214022 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7875649 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089778 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 297709996 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75289267 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53144243 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15477 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8000 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95277128 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8273 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 341654 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87712047 # Type of FU issued +system.cpu1.iq.rate 0.214000 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7876023 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089794 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 297668917 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75240910 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53134013 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15426 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7990 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6798 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95265766 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8242 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342419 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2834942 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3919 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1098203 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2834348 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3679 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17028 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1091492 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31919752 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 674526 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31919677 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675013 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2167836 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26657812 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 361941 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61957280 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112544 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12590402 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7938263 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869014 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64925 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17226 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 200285 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154811 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355096 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85998990 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43064757 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1724824 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2164183 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26656099 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 359793 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61930029 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112185 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12589854 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7931577 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869499 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 63855 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3879 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17028 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201052 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154389 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355441 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85989380 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43067298 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1722667 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104661 # number of nop insts executed -system.cpu1.iew.exec_refs 50176981 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6911907 # Number of branches executed -system.cpu1.iew.exec_stores 7112224 # Number of stores executed -system.cpu1.iew.exec_rate 0.209814 # Inst execution rate -system.cpu1.iew.wb_sent 85240093 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53151046 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29713379 # num instructions producing a value -system.cpu1.iew.wb_consumers 52980753 # num instructions consuming a value +system.cpu1.iew.exec_nop 104468 # number of nop insts executed +system.cpu1.iew.exec_refs 50174734 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6912361 # Number of branches executed +system.cpu1.iew.exec_stores 7107436 # Number of stores executed +system.cpu1.iew.exec_rate 0.209797 # Inst execution rate +system.cpu1.iew.wb_sent 85230326 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53140811 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29705560 # num instructions producing a value +system.cpu1.iew.wb_consumers 52974804 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.129674 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560833 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.129653 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560749 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13311701 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880765 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310263 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112093272 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.429609 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.397405 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13285222 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880791 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310591 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112079739 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.429663 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.397726 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95372912 85.08% 85.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8221460 7.33% 92.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2092695 1.87% 94.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254196 1.12% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1248841 1.11% 96.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 572620 0.51% 97.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 992421 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531111 0.47% 98.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1807016 1.61% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95362610 85.08% 85.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8223786 7.34% 92.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2087568 1.86% 94.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1250330 1.12% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1251085 1.12% 96.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 572828 0.51% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 991388 0.88% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 531334 0.47% 98.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1808810 1.61% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112093272 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38065083 # Number of instructions committed -system.cpu1.commit.committedOps 48156333 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112079739 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38065286 # Number of instructions committed +system.cpu1.commit.committedOps 48156538 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16595520 # Number of memory references committed -system.cpu1.commit.loads 9755460 # Number of loads committed +system.cpu1.commit.refs 16595591 # Number of memory references committed +system.cpu1.commit.loads 9755506 # Number of loads committed system.cpu1.commit.membars 190120 # Number of memory barriers committed -system.cpu1.commit.branches 5967695 # Number of branches committed +system.cpu1.commit.branches 5967745 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42691207 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534629 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1807016 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42691339 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534627 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1808810 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 170710273 # The number of ROB reads -system.cpu1.rob.rob_writes 125186848 # The number of ROB writes -system.cpu1.timesIdled 1415125 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295621498 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1799013115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37995444 # Number of Instructions Simulated -system.cpu1.committedOps 48086694 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37995444 # Number of Instructions Simulated -system.cpu1.cpi 10.787678 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.787678 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092698 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092698 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 384930549 # number of integer regfile reads -system.cpu1.int_regfile_writes 55277579 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5074 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18448778 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405411 # number of misc regfile writes -system.cpu1.icache.tags.replacements 596659 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.521199 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6934084 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 597171 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.611555 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74930526000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.521199 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938518 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938518 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 6934084 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6934084 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6934084 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6934084 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6934084 # number of overall hits -system.cpu1.icache.overall_hits::total 6934084 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 642197 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 642197 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 642197 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 642197 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 642197 # number of overall misses -system.cpu1.icache.overall_misses::total 642197 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8716898620 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8716898620 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8716898620 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8716898620 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8716898620 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8716898620 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576281 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7576281 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7576281 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7576281 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7576281 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7576281 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084764 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084764 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084764 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084764 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084764 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084764 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.558612 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.558612 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13573.558612 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13573.558612 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3156 # number of cycles access was blocked +system.cpu1.rob.rob_reads 170668638 # The number of ROB reads +system.cpu1.rob.rob_writes 125130415 # The number of ROB writes +system.cpu1.timesIdled 1414400 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295624990 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1799026779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37995647 # Number of Instructions Simulated +system.cpu1.committedOps 48086899 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37995647 # Number of Instructions Simulated +system.cpu1.cpi 10.787260 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.787260 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092702 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092702 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 384897666 # number of integer regfile reads +system.cpu1.int_regfile_writes 55271640 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5031 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18454230 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405462 # number of misc regfile writes +system.cpu1.icache.tags.replacements 595825 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.685801 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6935518 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 596337 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.630199 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74918873000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.685801 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938839 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938839 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6935518 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6935518 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6935518 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6935518 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6935518 # number of overall hits +system.cpu1.icache.overall_hits::total 6935518 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641267 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641267 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641267 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641267 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641267 # number of overall misses +system.cpu1.icache.overall_misses::total 641267 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8704460293 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8704460293 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8704460293 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8704460293 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8704460293 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8704460293 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576785 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7576785 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7576785 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7576785 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7576785 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7576785 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084636 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084636 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084636 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084636 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084636 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084636 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.847232 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.847232 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13573.847232 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13573.847232 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2595 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 176 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.610526 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.744318 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44987 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44987 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44987 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44987 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44987 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44987 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597210 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597210 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597210 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 597210 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 597210 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 597210 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7115046481 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7115046481 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7115046481 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7115046481 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7115046481 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7115046481 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44906 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44906 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44906 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44906 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44906 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44906 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596361 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 596361 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 596361 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 596361 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 596361 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 596361 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7105400062 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7105400062 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7105400062 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7105400062 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7105400062 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7105400062 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3356250 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3356250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078826 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078826 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078826 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11913.810018 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078709 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.078709 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078709 # mshr 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0.125229 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100265 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100265 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135859 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135859 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135859 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135859 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.359434 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.359434 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51480.325677 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 51480.325677 # average WriteReq miss latency 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(read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12448715 # number of overall hits +system.cpu1.dcache.overall_hits::total 12448715 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 397211 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 397211 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1557491 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1557491 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13987 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13987 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10584 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10584 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1954702 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1954702 # number of demand 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# number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396167 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1396167 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1435 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1435 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566512 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566512 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566512 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566512 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228371 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228371 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161692 # number of 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-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2847018297 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7247965426 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7247965426 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87929505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87929505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31688093 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31688093 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10094983723 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 10094983723 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10094983723 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 10094983723 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925175261 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925175261 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25838951416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25838951416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194764126677 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194764126677 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026235 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028384 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028384 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112335 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112335 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100256 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027085 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027085 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12466.636731 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12466.636731 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44825.751589 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44825.751589 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7033.235082 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7033.235082 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 2996.793361 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2996.793361 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324862 # number of writebacks +system.cpu1.dcache.writebacks::total 324862 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168849 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 168849 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395866 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395866 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1564715 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1564715 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1564715 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1564715 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228362 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228362 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161625 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161625 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12531 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12531 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10581 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10581 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389987 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389987 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389987 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389987 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2843265804 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2843265804 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7240277216 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7240277216 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88160756 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88160756 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31863585 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31863585 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10083543020 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 10083543020 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10083543020 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 10083543020 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925167755 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925167755 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25834747063 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25834747063 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194759914818 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194759914818 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028372 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028372 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112330 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112330 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027076 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027076 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12450.695843 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12450.695843 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44796.765451 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44796.765451 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7035.412657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7035.412657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3011.396371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3011.396371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2521,18 +2537,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612781961046 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 612781961046 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612781961046 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 612781961046 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612762276058 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 612762276058 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612762276058 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 612762276058 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41730 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41714 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48851 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48863 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index f1e51a584..49d73e9a8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,12 +602,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -555,6 +620,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -577,12 +643,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -592,19 +660,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -617,6 +689,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -639,6 +712,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -646,6 +720,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -657,6 +732,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -683,6 +759,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -694,19 +771,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -716,6 +797,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -725,6 +807,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -753,6 +836,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -762,8 +846,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -775,6 +891,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -790,6 +907,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -804,6 +923,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -813,6 +933,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -834,8 +955,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -844,6 +967,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -854,6 +978,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -864,6 +989,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -874,6 +1000,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -888,6 +1015,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -901,6 +1029,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -918,6 +1047,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -930,6 +1060,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -941,6 +1072,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -951,6 +1083,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -963,6 +1096,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -976,6 +1110,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -986,6 +1121,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -996,6 +1132,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1006,6 +1143,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1018,6 +1156,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1032,6 +1171,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1044,6 +1184,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1058,6 +1199,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1068,6 +1210,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1078,6 +1221,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1088,6 +1232,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1096,6 +1241,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1103,11 +1249,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b60e42a06..65955f345 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525141 # Number of seconds simulated -sim_ticks 2525141046500 # Number of ticks simulated -final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525132 # Number of seconds simulated +sim_ticks 2525131633500 # Number of ticks simulated +final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61643 # Simulator instruction rate (inst/s) -host_op_rate 79318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581152882 # Simulator tick rate (ticks/s) -host_mem_usage 426780 # Number of bytes of host memory used -host_seconds 978.30 # Real time elapsed on the host -sim_insts 60305756 # Number of instructions simulated -sim_ops 77596741 # Number of ops (including micro ops) simulated +host_inst_rate 49653 # Simulator instruction rate (inst/s) +host_op_rate 63890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2079077169 # Simulator tick rate (ticks/s) +host_mem_usage 446400 # Number of bytes of host memory used +host_seconds 1214.54 # Real time elapsed on the host +sim_insts 60305678 # Number of instructions simulated +sim_ops 77596684 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.writeReqs 813149 # Number of write requests accepted system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943582 # Per bank write bursts -system.physmem.perBankRdBursts::1 943145 # Per bank write bursts -system.physmem.perBankRdBursts::2 939291 # Per bank write bursts -system.physmem.perBankRdBursts::3 939307 # Per bank write bursts -system.physmem.perBankRdBursts::4 943115 # Per bank write bursts -system.physmem.perBankRdBursts::5 943141 # Per bank write bursts -system.physmem.perBankRdBursts::6 939138 # Per bank write bursts -system.physmem.perBankRdBursts::7 938546 # Per bank write bursts -system.physmem.perBankRdBursts::8 943996 # Per bank write bursts -system.physmem.perBankRdBursts::9 943390 # Per bank write bursts -system.physmem.perBankRdBursts::10 938426 # Per bank write bursts -system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943580 # Per bank write bursts +system.physmem.perBankRdBursts::1 943152 # Per bank write bursts +system.physmem.perBankRdBursts::2 939288 # Per bank write bursts +system.physmem.perBankRdBursts::3 939310 # Per bank write bursts +system.physmem.perBankRdBursts::4 943113 # Per bank write bursts +system.physmem.perBankRdBursts::5 943139 # Per bank write bursts +system.physmem.perBankRdBursts::6 939134 # Per bank write bursts +system.physmem.perBankRdBursts::7 938551 # Per bank write bursts +system.physmem.perBankRdBursts::8 944000 # Per bank write bursts +system.physmem.perBankRdBursts::9 943392 # Per bank write bursts +system.physmem.perBankRdBursts::10 938425 # Per bank write bursts +system.physmem.perBankRdBursts::11 937973 # Per bank write bursts system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943533 # Per bank write bursts -system.physmem.perBankRdBursts::14 939234 # Per bank write bursts -system.physmem.perBankRdBursts::15 938672 # Per bank write bursts -system.physmem.perBankWrBursts::0 6704 # Per bank write bursts -system.physmem.perBankWrBursts::1 6457 # Per bank write bursts -system.physmem.perBankWrBursts::2 6598 # Per bank write bursts -system.physmem.perBankWrBursts::3 6635 # Per bank write bursts -system.physmem.perBankWrBursts::4 6561 # Per bank write bursts -system.physmem.perBankWrBursts::5 6794 # Per bank write bursts -system.physmem.perBankWrBursts::6 6789 # Per bank write bursts -system.physmem.perBankWrBursts::7 6723 # Per bank write bursts -system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankRdBursts::13 943534 # Per bank write bursts +system.physmem.perBankRdBursts::14 939230 # Per bank write bursts +system.physmem.perBankRdBursts::15 938669 # Per bank write bursts +system.physmem.perBankWrBursts::0 6703 # Per bank write bursts +system.physmem.perBankWrBursts::1 6464 # Per bank write bursts +system.physmem.perBankWrBursts::2 6595 # Per bank write bursts +system.physmem.perBankWrBursts::3 6634 # Per bank write bursts +system.physmem.perBankWrBursts::4 6559 # Per bank write bursts +system.physmem.perBankWrBursts::5 6792 # Per bank write bursts +system.physmem.perBankWrBursts::6 6793 # Per bank write bursts +system.physmem.perBankWrBursts::7 6730 # Per bank write bursts +system.physmem.perBankWrBursts::8 7130 # Per bank write bursts system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6538 # Per bank write bursts -system.physmem.perBankWrBursts::11 6183 # Per bank write bursts -system.physmem.perBankWrBursts::12 7149 # Per bank write bursts -system.physmem.perBankWrBursts::13 6765 # Per bank write bursts -system.physmem.perBankWrBursts::14 7038 # Per bank write bursts -system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.perBankWrBursts::10 6539 # Per bank write bursts +system.physmem.perBankWrBursts::11 6181 # Per bank write bursts +system.physmem.perBankWrBursts::12 7151 # Per bank write bursts +system.physmem.perBankWrBursts::13 6766 # Per bank write bursts +system.physmem.perBankWrBursts::14 7035 # Per bank write bursts +system.physmem.perBankWrBursts::15 6897 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.totGap 2525130505500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 36 # Read request sizes (log2) @@ -109,26 +109,26 @@ system.physmem.writePktSize::2 754018 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59125 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59131 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -142,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see @@ -174,521 +174,534 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation @@ -714,15 +727,15 @@ system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation -system.physmem.totQLat 365610387500 # Total ticks spent queuing -system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation +system.physmem.totQLat 365453646000 # Total ticks spent queuing +system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks -system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks +system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s @@ -732,14 +745,14 @@ system.physmem.busUtil 3.00 # Da system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing -system.physmem.readRowHits 14986740 # Number of row buffer hits during reads -system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing +system.physmem.readRowHits 14986798 # Number of row buffer hits during reads +system.physmem.writeRowHits 93332 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes -system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes +system.physmem.avgGap 158713.50 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -752,50 +765,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54899945 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149440 # Transaction distribution -system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.throughput 54900302 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149434 # Transaction distribution +system.membus.trans_dist::ReadResp 16149434 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59131 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131442 # Transaction distribution -system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution +system.membus.trans_dist::ReadExReq 131448 # Transaction distribution +system.membus.trans_dist::ReadExResp 131448 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630105 # Total data (bytes) +system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630489 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -803,7 +816,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.throughput 48285786 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -913,40 +926,40 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14384905 # Number of BP lookups -system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits +system.cpu.branchPred.lookups 14384927 # Number of BP lookups +system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51179212 # DTB read hits -system.cpu.dtb.read_misses 64531 # DTB read misses -system.cpu.dtb.write_hits 11698539 # DTB write hits -system.cpu.dtb.write_misses 15837 # DTB write misses +system.cpu.dtb.read_hits 51182106 # DTB read hits +system.cpu.dtb.read_misses 64421 # DTB read misses +system.cpu.dtb.write_hits 11699698 # DTB write hits +system.cpu.dtb.write_misses 15824 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3571 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3567 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51243743 # DTB read accesses -system.cpu.dtb.write_accesses 11714376 # DTB write accesses +system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246527 # DTB read accesses +system.cpu.dtb.write_accesses 11715522 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62877751 # DTB hits -system.cpu.dtb.misses 80368 # DTB misses -system.cpu.dtb.accesses 62958119 # DTB accesses -system.cpu.itb.inst_hits 11513998 # ITB inst hits -system.cpu.itb.inst_misses 11344 # ITB inst misses +system.cpu.dtb.hits 62881804 # DTB hits +system.cpu.dtb.misses 80245 # DTB misses +system.cpu.dtb.accesses 62962049 # DTB accesses +system.cpu.itb.inst_hits 11522583 # ITB inst hits +system.cpu.itb.inst_misses 11276 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -955,148 +968,148 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2483 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11525342 # ITB inst accesses -system.cpu.itb.hits 11513998 # DTB hits -system.cpu.itb.misses 11344 # DTB misses -system.cpu.itb.accesses 11525342 # DTB accesses -system.cpu.numCycles 474882944 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11533859 # ITB inst accesses +system.cpu.itb.hits 11522583 # DTB hits +system.cpu.itb.misses 11276 # DTB misses +system.cpu.itb.accesses 11533859 # DTB accesses +system.cpu.numCycles 474898657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle +system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -1109,397 +1122,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued -system.cpu.iq.rate 0.258795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued +system.cpu.iq.rate 0.258806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221869 # number of nop insts executed -system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475076 # Number of branches executed -system.cpu.iew.exec_stores 12210518 # Number of stores executed -system.cpu.iew.exec_rate 0.254424 # Inst execution rate -system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47026181 # num instructions producing a value -system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value +system.cpu.iew.exec_nop 221761 # number of nop insts executed +system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475005 # Number of branches executed +system.cpu.iew.exec_stores 12211635 # Number of stores executed +system.cpu.iew.exec_rate 0.254432 # Inst execution rate +system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47031033 # num instructions producing a value +system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456137 # Number of instructions committed -system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456059 # Number of instructions committed +system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385736 # Number of memory references committed -system.cpu.commit.loads 15654008 # Number of loads committed -system.cpu.commit.membars 403573 # Number of memory barriers committed -system.cpu.commit.branches 9961077 # Number of branches committed +system.cpu.commit.refs 27385723 # Number of memory references committed +system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 9961071 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. -system.cpu.commit.function_calls 991208 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. +system.cpu.commit.function_calls 991207 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240636318 # The number of ROB reads -system.cpu.rob.rob_writes 195934369 # The number of ROB writes -system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305756 # Number of Instructions Simulated -system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated -system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547208469 # number of integer regfile reads -system.cpu.int_regfile_writes 87526188 # number of integer regfile writes -system.cpu.fp_regfile_reads 8624 # number of floating regfile reads -system.cpu.fp_regfile_writes 3008 # number of floating regfile writes -system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.rob.rob_reads 240665808 # The number of ROB reads +system.cpu.rob.rob_writes 195946920 # The number of ROB writes +system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305678 # Number of Instructions Simulated +system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated +system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547244882 # number of integer regfile reads +system.cpu.int_regfile_writes 87532645 # number of integer regfile writes +system.cpu.fp_regfile_reads 8511 # number of floating regfile reads +system.cpu.fp_regfile_writes 2972 # number of floating regfile writes +system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution +system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980741 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 980798 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits -system.cpu.icache.overall_hits::total 10449649 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses -system.cpu.icache.overall_misses::total 1060761 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits +system.cpu.icache.overall_hits::total 10457750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses +system.cpu.icache.overall_misses::total 1061214 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of 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cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 747187750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130906263 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9881313263 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935059000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941246249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442653817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442653817 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377712817 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383900066 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015983 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092607 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092607 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average ReadReq mshr miss latency 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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.replacements 643483 # number of replacements system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits 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ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits 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demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks -system.cpu.dcache.writebacks::total 607699 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634638 # number 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-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks +system.cpu.dcache.writebacks::total 607897 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1796,16 +1809,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index c314ac71a..745161c28 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,18 +228,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -234,6 +254,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -255,17 +276,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -284,17 +308,20 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -325,6 +352,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -387,6 +416,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -399,12 +429,14 @@ predType=tournament [system.cpu2.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu2.dtb.walker [system.cpu2.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system @@ -412,15 +444,18 @@ sys=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -429,16 +464,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -447,22 +485,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -471,22 +513,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -495,10 +541,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -507,124 +555,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -633,10 +702,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -645,16 +716,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -663,16 +737,19 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu2.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -691,30 +768,36 @@ midr=890224640 [system.cpu2.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu2.itb.walker [system.cpu2.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -727,6 +810,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -749,6 +833,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -758,6 +843,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -780,6 +866,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -787,6 +874,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -798,6 +886,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -824,6 +913,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -835,19 +925,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -857,6 +951,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -866,6 +961,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -894,6 +990,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -903,8 +1000,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -916,6 +1045,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -931,6 +1061,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -945,6 +1077,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -954,6 +1087,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -975,8 +1109,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -985,6 +1121,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -995,6 +1132,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1005,6 +1143,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1015,6 +1154,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1029,6 +1169,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1042,6 +1183,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1059,6 +1201,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1071,6 +1214,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1082,6 +1226,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1092,6 +1237,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1104,6 +1250,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1117,6 +1264,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1127,6 +1275,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1137,6 +1286,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1147,6 +1297,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1159,6 +1310,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1173,6 +1325,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1185,6 +1338,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1199,6 +1353,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1209,6 +1364,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1219,6 +1375,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1229,6 +1386,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1237,6 +1395,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1245,6 +1404,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1254,11 +1414,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 506582551..3eab7d5a6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,166 +1,182 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403658 # Number of seconds simulated -sim_ticks 2403657545000 # Number of ticks simulated -final_tick 2403657545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403659 # Number of seconds simulated +sim_ticks 2403658742000 # Number of ticks simulated +final_tick 2403658742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183148 # Simulator instruction rate (inst/s) -host_op_rate 235229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7297160965 # Simulator tick rate (ticks/s) -host_mem_usage 427808 # Number of bytes of host memory used -host_seconds 329.40 # Real time elapsed on the host -sim_insts 60328152 # Number of instructions simulated -sim_ops 77483430 # Number of ops (including micro ops) simulated +host_inst_rate 141358 # Simulator instruction rate (inst/s) +host_op_rate 181555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5632122143 # Simulator tick rate (ticks/s) +host_mem_usage 447420 # Number of bytes of host memory used +host_seconds 426.78 # Real time elapsed on the host +sim_insts 60328128 # Number of instructions simulated +sim_ops 77483556 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7048656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7049296 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 675392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1353632 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 674944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1353888 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512480 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3744384 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298192 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 186496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743872 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298256 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558320 # Number of bytes written to this memory -system.physmem.bytes_written::total 6760200 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558256 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759688 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14209 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14210 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110179 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10553 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58506 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324548 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 10546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2914 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21162 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512409 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324564 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389580 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812460 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47768482 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu2.data 389564 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812452 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768458 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2932471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 563155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 563261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213208 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540090 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540117 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648312 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47768482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648285 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768458 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3472561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472852 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 347261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1211467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54675779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13467317 # Number of read requests accepted -system.physmem.writeReqs 446508 # Number of write requests accepted -system.physmem.readBursts 13467317 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446508 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 861908288 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.data 347074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1211546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54675299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13477345 # Number of read requests accepted +system.physmem.writeReqs 446482 # Number of write requests accepted +system.physmem.readBursts 13477345 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446482 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 862550080 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 2866432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109734624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2812152 # Total written bytes from the system interface side +system.physmem.bytesWritten 2865536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109813728 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2811448 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 401719 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2372 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 837719 # Per bank write bursts -system.physmem.perBankRdBursts::1 837389 # Per bank write bursts -system.physmem.perBankRdBursts::2 837556 # Per bank write bursts -system.physmem.perBankRdBursts::3 837999 # Per bank write bursts -system.physmem.perBankRdBursts::4 838842 # Per bank write bursts -system.physmem.perBankRdBursts::5 838880 # Per bank write bursts -system.physmem.perBankRdBursts::6 838796 # Per bank write bursts -system.physmem.perBankRdBursts::7 839742 # Per bank write bursts -system.physmem.perBankRdBursts::8 840911 # Per bank write bursts -system.physmem.perBankRdBursts::9 843323 # Per bank write bursts -system.physmem.perBankRdBursts::10 844015 # Per bank write bursts -system.physmem.perBankRdBursts::11 845500 # Per bank write bursts -system.physmem.perBankRdBursts::12 847242 # Per bank write bursts -system.physmem.perBankRdBursts::13 846993 # Per bank write bursts -system.physmem.perBankRdBursts::14 845867 # Per bank write bursts -system.physmem.perBankRdBursts::15 846543 # Per bank write bursts -system.physmem.perBankWrBursts::0 2729 # Per bank write bursts -system.physmem.perBankWrBursts::1 2587 # Per bank write bursts -system.physmem.perBankWrBursts::2 2574 # Per bank write bursts -system.physmem.perBankWrBursts::3 3045 # Per bank write bursts -system.physmem.perBankWrBursts::4 3468 # Per bank write bursts -system.physmem.perBankWrBursts::5 3206 # Per bank write bursts -system.physmem.perBankWrBursts::6 2544 # Per bank write bursts -system.physmem.perBankWrBursts::7 2321 # Per bank write bursts -system.physmem.perBankWrBursts::8 2236 # Per bank write bursts -system.physmem.perBankWrBursts::9 2427 # Per bank write bursts -system.physmem.perBankWrBursts::10 2367 # Per bank write bursts -system.physmem.perBankWrBursts::11 2798 # Per bank write bursts -system.physmem.perBankWrBursts::12 3813 # Per bank write bursts -system.physmem.perBankWrBursts::13 3444 # Per bank write bursts -system.physmem.perBankWrBursts::14 2680 # Per bank write bursts -system.physmem.perBankWrBursts::15 2549 # Per bank write bursts +system.physmem.mergedWrBursts 401707 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2370 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837716 # Per bank write bursts +system.physmem.perBankRdBursts::1 837382 # Per bank write bursts +system.physmem.perBankRdBursts::2 837561 # Per bank write bursts +system.physmem.perBankRdBursts::3 838016 # Per bank write bursts +system.physmem.perBankRdBursts::4 839132 # Per bank write bursts +system.physmem.perBankRdBursts::5 839847 # Per bank write bursts +system.physmem.perBankRdBursts::6 839973 # Per bank write bursts +system.physmem.perBankRdBursts::7 841200 # Per bank write bursts +system.physmem.perBankRdBursts::8 842679 # Per bank write bursts +system.physmem.perBankRdBursts::9 845377 # Per bank write bursts +system.physmem.perBankRdBursts::10 845421 # Per bank write bursts +system.physmem.perBankRdBursts::11 845910 # Per bank write bursts +system.physmem.perBankRdBursts::12 847235 # Per bank write bursts +system.physmem.perBankRdBursts::13 846991 # Per bank write bursts +system.physmem.perBankRdBursts::14 846262 # Per bank write bursts +system.physmem.perBankRdBursts::15 846643 # Per bank write bursts +system.physmem.perBankWrBursts::0 2727 # Per bank write bursts +system.physmem.perBankWrBursts::1 2580 # Per bank write bursts +system.physmem.perBankWrBursts::2 2569 # Per bank write bursts +system.physmem.perBankWrBursts::3 3046 # Per bank write bursts +system.physmem.perBankWrBursts::4 3472 # Per bank write bursts +system.physmem.perBankWrBursts::5 3199 # Per bank write bursts +system.physmem.perBankWrBursts::6 2543 # Per bank write bursts +system.physmem.perBankWrBursts::7 2318 # Per bank write bursts +system.physmem.perBankWrBursts::8 2233 # Per bank write bursts +system.physmem.perBankWrBursts::9 2426 # Per bank write bursts +system.physmem.perBankWrBursts::10 2368 # Per bank write bursts +system.physmem.perBankWrBursts::11 2824 # Per bank write bursts +system.physmem.perBankWrBursts::12 3814 # Per bank write bursts +system.physmem.perBankWrBursts::13 3447 # Per bank write bursts +system.physmem.perBankWrBursts::14 2652 # Per bank write bursts +system.physmem.perBankWrBursts::15 2556 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402622305000 # Total gap between requests +system.physmem.totGap 2402623562000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13431664 # Read request sizes (log2) +system.physmem.readPktSize::3 13441712 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35645 # Read request sizes (log2) +system.physmem.readPktSize::6 35625 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429406 # Write request sizes (log2) +system.physmem.writePktSize::2 429390 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17102 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 965936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 943404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 937737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3274872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2367219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2366833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2384991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 47923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 55146 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17092 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 971418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 948778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 943230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3279616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2365953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2365403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2381873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 51923 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 17612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 17582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -176,30 +192,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -208,304 +224,298 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 17848.429795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3200.071202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 18346.519598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 8608 17.77% 17.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 4824 9.96% 27.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 1006 2.08% 29.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 654 1.35% 31.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 399 0.82% 31.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 406 0.84% 32.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 283 0.58% 33.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 297 0.61% 34.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 176 0.36% 34.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 170 0.35% 34.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 172 0.35% 35.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 155 0.32% 35.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 77 0.16% 35.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 80 0.17% 35.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 48 0.10% 35.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 416 0.86% 36.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 18 0.04% 36.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 23 0.05% 36.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 23 0.05% 36.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 108 0.22% 37.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 17 0.04% 37.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 165 0.34% 37.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 12 0.02% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 112 0.23% 37.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 15 0.03% 37.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 32 0.07% 37.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 7 0.01% 37.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 140 0.29% 38.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 6 0.01% 38.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 13 0.03% 38.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 455 0.94% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 12 0.02% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 2 0.00% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 72 0.15% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 5 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 6 0.01% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 5 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 10 0.02% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 5 0.01% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 505 1.04% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 5 0.01% 40.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 5 0.01% 40.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 65 0.13% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 5 0.01% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.02% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 15 0.03% 40.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 3 0.01% 40.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 4 0.01% 40.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 6 0.01% 40.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 66 0.14% 40.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 3 0.01% 40.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 327 0.67% 41.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 8 0.02% 41.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 41.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 130 0.27% 41.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 41.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 4 0.01% 41.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.01% 41.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 68 0.14% 41.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.01% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 5 0.01% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 4 0.01% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 42.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 258 0.53% 42.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 42.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 4 0.01% 42.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 3 0.01% 42.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 88 0.18% 42.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 3 0.01% 42.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 8 0.02% 42.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.01% 42.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 92 0.19% 42.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 4 0.01% 43.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 7 0.01% 43.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 43.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 102 0.21% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 2 0.00% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 3 0.01% 43.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 481 0.99% 44.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 2 0.00% 44.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 3 0.01% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 1 0.00% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.01% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 67 0.14% 44.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 5 0.01% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 6 0.01% 44.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 131 0.27% 44.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 1 0.00% 44.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 1 0.00% 44.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 72 0.15% 44.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 2 0.00% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 13 0.03% 44.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 133 0.27% 45.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 66 0.14% 45.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 64 0.13% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 385 0.79% 46.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 65 0.13% 46.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 128 0.26% 46.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 73 0.15% 46.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 128 0.26% 47.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 64 0.13% 47.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 478 0.99% 48.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 63 0.13% 48.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 48.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 89 0.18% 48.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 86 0.18% 48.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 257 0.53% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 1 0.00% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 65 0.13% 49.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 320 0.66% 50.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 64 0.13% 50.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 14 0.03% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 64 0.13% 50.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 499 1.03% 51.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 64 0.13% 51.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 442 0.91% 52.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 66 0.14% 53.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 72 0.15% 53.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 362 0.75% 54.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 2 0.00% 54.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 6 0.01% 54.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 781 1.61% 55.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 7 0.01% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 362 0.75% 56.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 72 0.15% 56.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 64 0.13% 56.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 128 0.26% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 57.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 442 0.91% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 499 1.03% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 64 0.13% 59.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 12 0.02% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 66 0.14% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 320 0.66% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 128 0.26% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 256 0.53% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 85 0.18% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 87 0.18% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 64 0.13% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 478 0.99% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 67 0.14% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 128 0.26% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 71 0.15% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 129 0.27% 63.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 64 0.13% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 384 0.79% 64.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 64 0.13% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 64 0.13% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 129 0.27% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 70 0.14% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 128 0.26% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 1 0.00% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 66 0.14% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 480 0.99% 66.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 64 0.13% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 89 0.18% 66.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 86 0.18% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 1 0.00% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 67.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 127 0.26% 67.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 320 0.66% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 65 0.13% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 13 0.03% 68.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 64 0.13% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 497 1.03% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 64 0.13% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 442 0.91% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 1 0.00% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 65 0.13% 71.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 72 0.15% 71.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 362 0.75% 72.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 6 0.01% 72.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 778 1.61% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 5 0.01% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 1 0.00% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 2 0.00% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 362 0.75% 74.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 72 0.15% 74.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 66 0.14% 74.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 443 0.91% 75.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 499 1.03% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.13% 77.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 13 0.03% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 321 0.66% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 127 0.26% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 1 0.00% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 257 0.53% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 1 0.00% 79.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 86 0.18% 79.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 89 0.18% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 479 0.99% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39495 1 0.00% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 128 0.26% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 71 0.15% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 128 0.26% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 64 0.13% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 64 0.13% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 384 0.79% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 129 0.27% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 71 0.15% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 128 0.26% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 67 0.14% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 477 0.98% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 64 0.13% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 87 0.18% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 84 0.17% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 128 0.26% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 320 0.66% 86.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 65 0.13% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 12 0.02% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 64 0.13% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 498 1.03% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 1 0.00% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 64 0.13% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 443 0.91% 88.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 66 0.14% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 72 0.15% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 362 0.75% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 2 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 2 0.00% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 1 0.00% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 7 0.01% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4749 9.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48451 # Bytes accessed per row activation -system.physmem.totQLat 326245474250 # Total ticks spent queuing -system.physmem.totMemAccLat 407559786750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67336585000 # Total ticks spent in databus transfers -system.physmem.totBankLat 13977727500 # Total ticks spent accessing banks -system.physmem.avgQLat 24224.98 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1037.90 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 48550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17825.239135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3190.498487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18342.849091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8610 17.73% 17.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4856 10.00% 27.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 981 2.02% 29.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 733 1.51% 31.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 427 0.88% 32.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 370 0.76% 32.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 272 0.56% 33.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 308 0.63% 34.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 164 0.34% 34.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 164 0.34% 34.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 166 0.34% 35.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 231 0.48% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 82 0.17% 35.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 88 0.18% 35.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 37 0.08% 36.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 306 0.63% 36.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 22 0.05% 36.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 33 0.07% 36.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 21 0.04% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 99 0.20% 37.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 20 0.04% 37.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 170 0.35% 37.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 13 0.03% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 137 0.28% 37.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 12 0.02% 37.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 29 0.06% 37.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 10 0.02% 37.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 139 0.29% 38.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 7 0.01% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 378 0.78% 38.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 7 0.01% 38.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 7 0.01% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 70 0.14% 39.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 3 0.01% 39.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 71 0.15% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 5 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 4 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 4 0.01% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 9 0.02% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 7 0.01% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 5 0.01% 39.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 411 0.85% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 4 0.01% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 1 0.00% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 132 0.27% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 40.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 5 0.01% 40.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 3 0.01% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 73 0.15% 40.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 384 0.79% 41.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 41.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 3 0.01% 41.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 131 0.27% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 8 0.02% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 2 0.00% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 2 0.00% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 68 0.14% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 2 0.00% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 42.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 5 0.01% 42.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 34 0.07% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 6 0.01% 42.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 4 0.01% 42.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 263 0.54% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 3 0.01% 42.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 5 0.01% 42.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 131 0.27% 43.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 4 0.01% 43.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 9 0.02% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.01% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 70 0.14% 43.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 3 0.01% 43.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 4 0.01% 43.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 5 0.01% 43.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 103 0.21% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 4 0.01% 43.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 9 0.02% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 323 0.67% 44.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 3 0.01% 44.21% # Bytes accessed per row activation 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0.60% 45.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 2 0.00% 45.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 14 0.03% 45.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 4 0.01% 45.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 128 0.26% 45.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 65 0.13% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 1 0.00% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 415 0.85% 46.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 291 0.60% 47.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 81 0.17% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 3 0.01% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 64 0.13% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 64 0.13% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 128 0.26% 48.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 256 0.53% 49.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 32 0.07% 49.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 64 0.13% 49.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 375 0.77% 50.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 68 0.14% 50.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12615 1 0.00% 50.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 65 0.13% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 125 0.26% 50.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 51.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 408 0.84% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 1 0.00% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 64 0.13% 51.97% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::19008-19015 1 0.00% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 407 0.84% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 125 0.26% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 65 0.13% 59.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 70 0.14% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 59.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 376 0.77% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 127 0.26% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 29 0.06% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 256 0.53% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 128 0.26% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 64 0.13% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 65 0.13% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 320 0.66% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 3 0.01% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 82 0.17% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 292 0.60% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 129 0.27% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 414 0.85% 64.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 65 0.13% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 129 0.27% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 291 0.60% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 80 0.16% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 4 0.01% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 320 0.66% 66.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 65 0.13% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 64 0.13% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 128 0.26% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 32 0.07% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 128 0.26% 67.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 377 0.78% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 68 0.14% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 65 0.13% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 125 0.26% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 410 0.84% 69.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 1 0.00% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 64 0.13% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 65 0.13% 70.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 363 0.75% 70.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 96 0.20% 71.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 68 0.14% 71.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 256 0.53% 72.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 64 0.13% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 72 0.15% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 1.32% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 72 0.15% 73.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 73.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 63 0.13% 73.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 256 0.53% 74.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 68 0.14% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 96 0.20% 74.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 363 0.75% 75.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 75.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.13% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 1 0.00% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 410 0.84% 76.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 125 0.26% 77.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 65 0.13% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 68 0.14% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 376 0.77% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 128 0.26% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 65 0.13% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 32 0.07% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 256 0.53% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 128 0.26% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 64 0.13% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 320 0.66% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 4 0.01% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 80 0.16% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 292 0.60% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 129 0.27% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 65 0.13% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 413 0.85% 82.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 129 0.27% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 292 0.60% 83.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 82 0.17% 83.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 3 0.01% 83.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 320 0.66% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 65 0.13% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 65 0.13% 84.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 128 0.26% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 29 0.06% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 127 0.26% 85.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 375 0.77% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 70 0.14% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 1 0.00% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 64 0.13% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 125 0.26% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 406 0.84% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 64 0.13% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 364 0.75% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 96 0.20% 89.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 69 0.14% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 258 0.53% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 71 0.15% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4686 9.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48550 # Bytes accessed per row activation +system.physmem.totQLat 326412969750 # Total ticks spent queuing +system.physmem.totMemAccLat 407861489750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67386725000 # Total ticks spent in databus transfers +system.physmem.totBankLat 14061795000 # Total ticks spent accessing banks +system.physmem.avgQLat 24219.38 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1043.37 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30262.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30262.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage @@ -513,328 +523,330 @@ system.physmem.busUtilRead 2.80 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing -system.physmem.readRowHits 13424164 # Number of row buffer hits during reads -system.physmem.writeRowHits 39490 # Number of row buffer hits during writes +system.physmem.readRowHits 13434104 # Number of row buffer hits during reads +system.physmem.writeRowHits 39465 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 88.17 # Row buffer hit rate for writes -system.physmem.avgGap 172678.78 # Average gap between requests +system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes +system.physmem.avgGap 172554.83 # Average gap between requests system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.76 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55673060 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13803640 # Transaction distribution -system.membus.trans_dist::ReadResp 13803640 # Transaction distribution -system.membus.trans_dist::WriteReq 432247 # Transaction distribution -system.membus.trans_dist::WriteResp 432247 # Transaction distribution -system.membus.trans_dist::Writeback 17102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2372 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2372 # Transaction distribution -system.membus.trans_dist::ReadExReq 28053 # Transaction distribution -system.membus.trans_dist::ReadExResp 28053 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 734214 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 0.75 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55672581 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13813538 # Transaction distribution +system.membus.trans_dist::ReadResp 13813538 # Transaction distribution +system.membus.trans_dist::WriteReq 432230 # Transaction distribution +system.membus.trans_dist::WriteResp 432230 # Transaction distribution +system.membus.trans_dist::Writeback 17092 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2370 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2370 # Transaction distribution +system.membus.trans_dist::ReadExReq 28046 # Transaction distribution +system.membus.trans_dist::ReadExResp 28046 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 733938 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1686398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26863328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26863328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28549726 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 738102 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1686036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26883424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26883424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28569460 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 737821 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5093464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5832006 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107453312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107453312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113285318 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133818970 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5091480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5829741 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107533696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107533696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113363437 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817886 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 417653000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 418359500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 204500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14595653500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14607428500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1597948868 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1598779620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30334798000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30355600750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63262 # number of replacements -system.l2c.tags.tagsinuse 50391.923695 # Cycle average of tags in use -system.l2c.tags.total_refs 1749292 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128659 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.596344 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375568862000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36846.357046 # Average occupied blocks per requestor +system.l2c.tags.replacements 63253 # number of replacements +system.l2c.tags.tagsinuse 50392.264505 # Cycle average of tags in use +system.l2c.tags.total_refs 1749443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128649 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.598574 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375574111000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36861.205107 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5224.016956 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3834.498559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5227.235315 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3840.097341 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 503.830830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 691.484420 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832714 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1696.766805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1584.142905 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562231 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 502.876093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 689.542033 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.851035 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974650 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1682.063126 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1580.426346 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562457 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058510 # Average 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rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023420 # mshr miss rate for overall accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.344476 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366569 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117092 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115599 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023400 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115599 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023400 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63510.695187 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64946.202532 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62947.444679 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64624.219447 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66537.011054 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64252.770682 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.070664 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001.486381 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.668896 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62525.097599 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 63351.490352 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63074.321708 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.334448 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62561.980200 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62753.451571 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62689.252619 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -987,52 +1011,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58815755 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021426 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021425 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432247 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432247 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1513 # Transaction distribution +system.toL2Bus.throughput 58816500 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021450 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021449 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432230 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432230 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265546 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1512 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80586 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80586 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831264 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423236 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15497 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52067 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3322064 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26578304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37416070 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21580 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64100814 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141271334 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 101600 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2179143758 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80593 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80593 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831311 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423002 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52276 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3322226 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26580608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37417965 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64105945 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141275262 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 99532 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2179112263 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872769954 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872836168 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1848854181 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1848885181 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10116966 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10174967 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30973250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31036489 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48762849 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13795996 # Transaction distribution -system.iobus.trans_dist::ReadResp 13795996 # Transaction distribution -system.iobus.trans_dist::WriteReq 2775 # Transaction distribution -system.iobus.trans_dist::WriteResp 2775 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11418 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3030 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48762826 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13805907 # Transaction distribution +system.iobus.trans_dist::ReadResp 13805907 # Transaction distribution +system.iobus.trans_dist::WriteReq 2774 # Transaction distribution +system.iobus.trans_dist::WriteResp 2774 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 719202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 718942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1048,18 +1072,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 734214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26863328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26863328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27597542 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15382 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 733938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26883424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26883424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27617362 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715532 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715269 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1075,14 +1099,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 738102 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107453312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107453312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108191414 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7974000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 737821 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107533696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107533696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108271517 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209194 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1515000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1094,7 +1118,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 360101000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 359973000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1126,35 +1150,35 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13431664000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13441712000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 731439000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 731164000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36823110000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36852557250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7991455 # DTB read hits -system.cpu0.dtb.read_misses 6184 # DTB read misses -system.cpu0.dtb.write_hits 6591541 # DTB write hits +system.cpu0.dtb.read_hits 7990938 # DTB read hits +system.cpu0.dtb.read_misses 6181 # DTB read misses +system.cpu0.dtb.write_hits 6591681 # DTB write hits system.cpu0.dtb.write_misses 1989 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5665 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 119 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7997639 # DTB read accesses -system.cpu0.dtb.write_accesses 6593530 # DTB write accesses +system.cpu0.dtb.read_accesses 7997119 # DTB read accesses +system.cpu0.dtb.write_accesses 6593670 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14582996 # DTB hits -system.cpu0.dtb.misses 8173 # DTB misses -system.cpu0.dtb.accesses 14591169 # DTB accesses -system.cpu0.itb.inst_hits 32325256 # ITB inst hits -system.cpu0.itb.inst_misses 3454 # ITB inst misses +system.cpu0.dtb.hits 14582619 # DTB hits +system.cpu0.dtb.misses 8170 # DTB misses +system.cpu0.dtb.accesses 14590789 # DTB accesses +system.cpu0.itb.inst_hits 32323173 # ITB inst hits +system.cpu0.itb.inst_misses 3455 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1170,400 +1194,400 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32328710 # ITB inst accesses -system.cpu0.itb.hits 32325256 # DTB hits -system.cpu0.itb.misses 3454 # DTB misses -system.cpu0.itb.accesses 32328710 # DTB accesses -system.cpu0.numCycles 113673861 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32326628 # ITB inst accesses +system.cpu0.itb.hits 32323173 # DTB hits +system.cpu0.itb.misses 3455 # DTB misses +system.cpu0.itb.accesses 32326628 # DTB accesses +system.cpu0.numCycles 113706934 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31847112 # Number of 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of memory refs -system.cpu0.num_load_insts 8359762 # Number of load instructions -system.cpu0.num_store_insts 6890312 # Number of store instructions -system.cpu0.num_idle_cycles 110868175.114613 # Number of idle cycles -system.cpu0.num_busy_cycles 2805685.885387 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024682 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975318 # Percentage of idle cycles +system.cpu0.committedInsts 31845607 # Number of instructions committed +system.cpu0.committedOps 42007795 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37151613 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses +system.cpu0.num_func_calls 1198507 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4245528 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37151613 # number of integer instructions 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0.020561 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014731 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016046 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076204 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020561 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014731 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016046 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076204 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020561 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13508.608805 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13496.709757 # average ReadReq miss latency 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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56157863000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442314990 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341314242 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14783629232 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817602490 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42123889742 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70941492232 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033793 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026760 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014101 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021325 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019463 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1733546761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3590440812 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5323987573 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1733546761 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3590440812 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5323987573 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27356277500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28781091750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56137369250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442174490 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339751582 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14781926072 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28798451990 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42120843332 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70919295322 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033820 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026749 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014103 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021316 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019469 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008033 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049937 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043150 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049859 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043028 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020218 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011523 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011523 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12227.125980 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12926.558181 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12698.318145 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33253.882507 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35539.841568 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34741.616574 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.301496 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11583.283747 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11427.249655 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011525 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011525 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.686678 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12959.606210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.544437 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33315.433109 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35310.030029 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34614.428054 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.665513 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11526.466466 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11387.033208 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1576,27 +1600,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096740 # DTB read hits -system.cpu1.dtb.read_misses 2075 # DTB read misses -system.cpu1.dtb.write_hits 1419315 # DTB write hits +system.cpu1.dtb.read_hits 2096419 # DTB read hits +system.cpu1.dtb.read_misses 2083 # DTB read misses +system.cpu1.dtb.write_hits 1418166 # DTB write hits system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1735 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098815 # DTB read accesses -system.cpu1.dtb.write_accesses 1419688 # DTB write accesses +system.cpu1.dtb.read_accesses 2098502 # DTB read accesses +system.cpu1.dtb.write_accesses 1418539 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3516055 # DTB hits -system.cpu1.dtb.misses 2448 # DTB misses -system.cpu1.dtb.accesses 3518503 # DTB accesses -system.cpu1.itb.inst_hits 8182654 # ITB inst hits -system.cpu1.itb.inst_misses 1200 # ITB inst misses +system.cpu1.dtb.hits 3514585 # DTB hits +system.cpu1.dtb.misses 2456 # DTB misses +system.cpu1.dtb.accesses 3517041 # DTB accesses +system.cpu1.itb.inst_hits 8182058 # ITB inst hits +system.cpu1.itb.inst_misses 1201 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1605,73 +1629,73 @@ system.cpu1.itb.flush_tlb 277 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 888 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 889 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8183854 # ITB inst accesses -system.cpu1.itb.hits 8182654 # DTB hits -system.cpu1.itb.misses 1200 # DTB misses -system.cpu1.itb.accesses 8183854 # DTB accesses -system.cpu1.numCycles 581318737 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8183259 # ITB inst accesses +system.cpu1.itb.hits 8182058 # DTB hits +system.cpu1.itb.misses 1201 # DTB misses +system.cpu1.itb.accesses 8183259 # DTB accesses +system.cpu1.numCycles 581387993 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7974693 # Number of instructions committed -system.cpu1.committedOps 10126531 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9058549 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1938 # Number of float alu accesses -system.cpu1.num_func_calls 304877 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1114107 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9058549 # number of integer instructions -system.cpu1.num_fp_insts 1938 # number of float instructions -system.cpu1.num_int_register_reads 52214198 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9844324 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1424 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_mem_refs 3684398 # number of memory refs -system.cpu1.num_load_insts 2190368 # Number of load instructions -system.cpu1.num_store_insts 1494030 # Number of store instructions -system.cpu1.num_idle_cycles 546218260.044225 # Number of idle cycles -system.cpu1.num_busy_cycles 35100476.955774 # Number of busy cycles -system.cpu1.not_idle_fraction 0.060381 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.939619 # Percentage of idle cycles +system.cpu1.committedInsts 7973391 # Number of instructions committed +system.cpu1.committedOps 10123180 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9055145 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses +system.cpu1.num_func_calls 304839 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1113920 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9055145 # number of integer instructions +system.cpu1.num_fp_insts 2019 # number of float instructions +system.cpu1.num_int_register_reads 52196104 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9841677 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written +system.cpu1.num_mem_refs 3682729 # number of memory refs +system.cpu1.num_load_insts 2189938 # Number of load instructions +system.cpu1.num_store_insts 1492791 # Number of store instructions +system.cpu1.num_idle_cycles 546287151.729317 # Number of idle cycles +system.cpu1.num_busy_cycles 35100841.270683 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060374 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939626 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4723221 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3843292 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 222521 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3120017 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2528037 # Number of BTB hits +system.cpu2.branchPred.lookups 4728615 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3846891 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223365 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3153803 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2531568 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 81.026385 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 412365 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21211 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.270328 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413323 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21760 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10969613 # DTB read hits -system.cpu2.dtb.read_misses 23045 # DTB read misses -system.cpu2.dtb.write_hits 3352330 # DTB write hits +system.cpu2.dtb.read_hits 10972958 # DTB read hits +system.cpu2.dtb.read_misses 22884 # DTB read misses +system.cpu2.dtb.write_hits 3353841 # DTB write hits system.cpu2.dtb.write_misses 6440 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2328 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2329 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 684 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10992658 # DTB read accesses -system.cpu2.dtb.write_accesses 3358770 # DTB write accesses +system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10995842 # DTB read accesses +system.cpu2.dtb.write_accesses 3360281 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14321943 # DTB hits -system.cpu2.dtb.misses 29485 # DTB misses -system.cpu2.dtb.accesses 14351428 # DTB accesses -system.cpu2.itb.inst_hits 4048520 # ITB inst hits -system.cpu2.itb.inst_misses 4581 # ITB inst misses +system.cpu2.dtb.hits 14326799 # DTB hits +system.cpu2.dtb.misses 29324 # DTB misses +system.cpu2.dtb.accesses 14356123 # DTB accesses +system.cpu2.itb.inst_hits 4052293 # ITB inst hits +system.cpu2.itb.inst_misses 4591 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1684,110 +1708,110 @@ system.cpu2.itb.flush_entries 1671 # Nu system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1028 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4053101 # ITB inst accesses -system.cpu2.itb.hits 4048520 # DTB hits -system.cpu2.itb.misses 4581 # DTB misses -system.cpu2.itb.accesses 4053101 # DTB accesses -system.cpu2.numCycles 88363580 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4056884 # ITB inst accesses +system.cpu2.itb.hits 4052293 # DTB hits +system.cpu2.itb.misses 4591 # DTB misses +system.cpu2.itb.accesses 4056884 # DTB accesses +system.cpu2.numCycles 88364936 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9342746 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32497136 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4723221 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2940402 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6855397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1756636 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50446 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18848050 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 925 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 34178 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 721824 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4047074 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289511 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37061318 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.053700 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.440521 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9352566 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32517206 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4728615 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2944891 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6861610 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1759869 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50868 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18844594 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 866 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32744 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721068 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 448 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4050852 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289827 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1989 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37074469 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.054164 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.440934 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30210914 81.52% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385385 1.04% 82.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 515477 1.39% 83.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 820134 2.21% 86.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 628486 1.70% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 342820 0.93% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1044433 2.82% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 229207 0.62% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2884462 7.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30218075 81.51% 81.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 386681 1.04% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516163 1.39% 83.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 819367 2.21% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 628808 1.70% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344228 0.93% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1045241 2.82% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229591 0.62% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2886315 7.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37061318 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053452 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367766 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9926500 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19460558 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6238388 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 279816 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1155131 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608208 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53066 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36958585 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178391 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1155131 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10476553 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6920166 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11076723 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5947862 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1483966 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34870863 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2458 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 328650 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 889849 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 96 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37358262 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159586833 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148423376 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3369 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26507725 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10850536 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 232822 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 209087 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3256835 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6623705 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3904787 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530493 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 775113 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32195808 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 505146 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34809127 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54913 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7172484 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19086467 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 147942 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37061318 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.939231 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.598560 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37074469 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053512 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367988 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9932859 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19459354 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6244628 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 279238 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1157490 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 609849 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53110 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36985250 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179754 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1157490 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10483306 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6921288 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11074515 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5953553 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1483425 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34895792 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 326661 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 892066 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 111 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37386016 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159700078 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148525933 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3408 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26513636 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10872379 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232480 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208815 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3253838 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6628841 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3905916 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 536820 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 771052 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32212739 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505163 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34823222 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55040 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7182108 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19097970 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148083 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37074469 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.939278 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.598547 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24455957 65.99% 65.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3833682 10.34% 76.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2322342 6.27% 82.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2005181 5.41% 88.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2795966 7.54% 95.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 971107 2.62% 98.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 498292 1.34% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144261 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34530 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24463826 65.99% 65.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3833492 10.34% 76.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2324654 6.27% 82.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2008652 5.42% 88.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2796278 7.54% 95.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 971248 2.62% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 496274 1.34% 99.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144890 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35155 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37061318 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37074469 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19660 1.28% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19545 1.28% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available @@ -1816,13 +1840,13 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1402550 91.51% 92.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110445 7.21% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1401661 91.55% 92.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109897 7.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61175 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19747110 56.73% 56.91% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 27980 0.08% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61115 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19755783 56.73% 56.91% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28013 0.08% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued @@ -1838,7 +1862,7 @@ system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Ty system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued @@ -1850,114 +1874,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11452276 32.90% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3520179 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11456328 32.90% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3521577 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34809127 # Type of FU issued -system.cpu2.iq.rate 0.393931 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1532656 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044030 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108288948 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39878610 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28070823 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7546 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3965 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3367 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36276582 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4026 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205280 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34823222 # Type of FU issued +system.cpu2.iq.rate 0.394084 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1531104 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043968 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108328678 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39905127 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28084625 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7572 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4019 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3368 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36289170 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4041 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206363 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1528845 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1875 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9489 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562920 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1533130 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9465 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562980 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5328051 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344229 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5327720 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344503 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1155131 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5244365 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 89322 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32783919 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60352 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6623705 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3904787 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362611 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 30261 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2481 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9489 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 106879 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89021 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195900 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33894861 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11182187 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 914266 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1157490 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5247900 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88519 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32800222 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60619 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6628841 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3905916 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362644 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29757 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2395 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9465 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107959 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89408 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197367 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33908136 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11185478 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 915086 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82965 # number of nop insts executed -system.cpu2.iew.exec_refs 14668868 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3706634 # Number of branches executed -system.cpu2.iew.exec_stores 3486681 # Number of stores executed -system.cpu2.iew.exec_rate 0.383584 # Inst execution rate -system.cpu2.iew.wb_sent 33494578 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28074190 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16115456 # num instructions producing a value -system.cpu2.iew.wb_consumers 29164308 # num instructions consuming a value +system.cpu2.iew.exec_nop 82320 # number of nop insts executed +system.cpu2.iew.exec_refs 14673656 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3709694 # Number of branches executed +system.cpu2.iew.exec_stores 3488178 # Number of stores executed +system.cpu2.iew.exec_rate 0.383728 # Inst execution rate +system.cpu2.iew.wb_sent 33508440 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28087993 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16121354 # num instructions producing a value +system.cpu2.iew.wb_consumers 29172590 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317712 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552575 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317864 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552620 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7126752 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357204 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170224 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35906001 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.707499 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.751012 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7137877 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357080 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171034 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35916785 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.707415 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.751354 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27147368 75.61% 75.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4230684 11.78% 87.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1251387 3.49% 90.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 639812 1.78% 92.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 559957 1.56% 94.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 318640 0.89% 95.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 417979 1.16% 96.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 311730 0.87% 97.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1028444 2.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27161260 75.62% 75.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4227698 11.77% 87.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1252285 3.49% 90.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 635084 1.77% 92.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 561790 1.56% 94.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 319405 0.89% 95.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 418201 1.16% 96.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 311340 0.87% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1029722 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35906001 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20561870 # Number of instructions committed -system.cpu2.commit.committedOps 25403458 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35916785 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20564616 # Number of instructions committed +system.cpu2.commit.committedOps 25408067 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8436727 # Number of memory references committed -system.cpu2.commit.loads 5094860 # Number of loads committed -system.cpu2.commit.membars 94449 # Number of memory barriers committed -system.cpu2.commit.branches 3185060 # Number of branches committed +system.cpu2.commit.refs 8438647 # Number of memory references committed +system.cpu2.commit.loads 5095711 # Number of loads committed +system.cpu2.commit.membars 94423 # Number of memory barriers committed +system.cpu2.commit.branches 3185422 # Number of branches committed system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22606405 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295605 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1028444 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 22610745 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295586 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1029722 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66885510 # The number of ROB reads -system.cpu2.rob.rob_writes 66259648 # The number of ROB writes -system.cpu2.timesIdled 359925 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51302262 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3553994827 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20506347 # Number of Instructions Simulated -system.cpu2.committedOps 25347935 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20506347 # Number of Instructions Simulated -system.cpu2.cpi 4.309084 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.309084 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232068 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232068 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157055367 # number of integer regfile reads -system.cpu2.int_regfile_writes 29889640 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22622 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9269321 # number of misc regfile reads -system.cpu2.misc_regfile_writes 242794 # number of misc regfile writes +system.cpu2.rob.rob_reads 66910934 # The number of ROB reads +system.cpu2.rob.rob_writes 66293514 # The number of ROB writes +system.cpu2.timesIdled 359960 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51290467 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553935024 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20509130 # Number of Instructions Simulated +system.cpu2.committedOps 25352581 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20509130 # Number of Instructions Simulated +system.cpu2.cpi 4.308566 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.308566 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232096 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232096 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157121826 # number of integer regfile reads +system.cpu2.int_regfile_writes 29906145 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22616 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20826 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9261107 # number of misc regfile reads +system.cpu2.misc_regfile_writes 242774 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1972,10 +1996,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1346583006000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1346583006000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1347589582250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1347589582250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 0865afb47..bd21d2c8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,18 +602,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -581,6 +647,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -643,6 +711,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -655,12 +724,14 @@ predType=tournament [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system @@ -668,15 +739,18 @@ sys=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -685,16 +759,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -703,22 +780,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -727,22 +808,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -751,10 +836,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -763,124 +850,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -889,10 +997,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -901,16 +1011,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -919,16 +1032,19 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -947,30 +1063,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -983,6 +1105,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1005,6 +1128,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1014,6 +1138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1036,6 +1161,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1043,6 +1169,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1054,6 +1181,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1080,6 +1208,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1091,19 +1220,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1113,6 +1246,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -1122,6 +1256,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1150,6 +1285,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -1159,8 +1295,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1172,6 +1340,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -1187,6 +1356,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -1201,6 +1372,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1210,6 +1382,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1231,8 +1404,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1241,6 +1416,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1251,6 +1427,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1261,6 +1438,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1271,6 +1449,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1285,6 +1464,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1298,6 +1478,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1315,6 +1496,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1327,6 +1509,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1338,6 +1521,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1348,6 +1532,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1360,6 +1545,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1373,6 +1559,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1383,6 +1570,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1393,6 +1581,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1403,6 +1592,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1415,6 +1605,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1429,6 +1620,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1441,6 +1633,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1455,6 +1648,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1465,6 +1659,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1475,6 +1670,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1485,6 +1681,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1493,6 +1690,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1501,6 +1699,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1510,11 +1709,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index cc97b6f9f..5fef90c5a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,166 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.549325 # Number of seconds simulated -sim_ticks 2549325180000 # Number of ticks simulated -final_tick 2549325180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.549345 # Number of seconds simulated +sim_ticks 2549345168000 # Number of ticks simulated +final_tick 2549345168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61075 # Simulator instruction rate (inst/s) -host_op_rate 78588 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581455626 # Simulator tick rate (ticks/s) -host_mem_usage 428832 # Number of bytes of host memory used -host_seconds 987.55 # Real time elapsed on the host -sim_insts 60314884 # Number of instructions simulated -sim_ops 77609482 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 48945 # Simulator instruction rate (inst/s) +host_op_rate 62980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2068782078 # Simulator tick rate (ticks/s) +host_mem_usage 448444 # Number of bytes of host memory used +host_seconds 1232.29 # Real time elapsed on the host +sim_insts 60314699 # Number of instructions simulated +sim_ops 77609228 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 507840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4720464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 291712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4372184 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 507840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 291712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785664 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521520 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494580 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801764 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 498624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4680272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 301248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4410392 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 498624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 301248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784640 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521380 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494720 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800740 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73791 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68321 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293464 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59151 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380380 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373645 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813176 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47506897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 678 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68918 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59135 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380345 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813160 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47506524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1851652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1715036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51388297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114427 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313633 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586265 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2668064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47506897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 195589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1835872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 118167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1730010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51387342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 195589 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 118167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484554 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596773 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586315 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47506524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2448485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2301301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54056362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293464 # Number of read requests accepted -system.physmem.writeReqs 813176 # Number of write requests accepted -system.physmem.readBursts 15293464 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813176 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978217536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 564160 # Total number of bytes read from write queue -system.physmem.bytesWritten 6910272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131005480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801764 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8815 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705189 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4711 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955865 # Per bank write bursts -system.physmem.perBankRdBursts::1 955523 # Per bank write bursts -system.physmem.perBankRdBursts::2 954611 # Per bank write bursts -system.physmem.perBankRdBursts::3 954852 # Per bank write bursts -system.physmem.perBankRdBursts::4 955764 # Per bank write bursts -system.physmem.perBankRdBursts::5 955945 # Per bank write bursts -system.physmem.perBankRdBursts::6 954843 # Per bank write bursts -system.physmem.perBankRdBursts::7 954680 # Per bank write bursts -system.physmem.perBankRdBursts::8 956251 # Per bank write bursts -system.physmem.perBankRdBursts::9 955822 # Per bank write bursts -system.physmem.perBankRdBursts::10 954302 # Per bank write bursts -system.physmem.perBankRdBursts::11 954022 # Per bank write bursts -system.physmem.perBankRdBursts::12 956218 # Per bank write bursts -system.physmem.perBankRdBursts::13 955977 # Per bank write bursts -system.physmem.perBankRdBursts::14 955052 # Per bank write bursts -system.physmem.perBankRdBursts::15 954922 # Per bank write bursts -system.physmem.perBankWrBursts::0 6685 # Per bank write bursts -system.physmem.perBankWrBursts::1 6462 # Per bank write bursts -system.physmem.perBankWrBursts::2 6616 # Per bank write bursts -system.physmem.perBankWrBursts::3 6625 # Per bank write bursts -system.physmem.perBankWrBursts::4 6578 # Per bank write bursts -system.physmem.perBankWrBursts::5 6834 # Per bank write bursts -system.physmem.perBankWrBursts::6 6825 # Per bank write bursts -system.physmem.perBankWrBursts::7 6778 # Per bank write bursts -system.physmem.perBankWrBursts::8 7112 # Per bank write bursts -system.physmem.perBankWrBursts::9 6876 # Per bank write bursts -system.physmem.perBankWrBursts::10 6540 # Per bank write bursts -system.physmem.perBankWrBursts::11 6189 # Per bank write bursts -system.physmem.perBankWrBursts::12 7142 # Per bank write bursts -system.physmem.perBankWrBursts::13 6759 # Per bank write bursts -system.physmem.perBankWrBursts::14 7042 # Per bank write bursts -system.physmem.perBankWrBursts::15 6910 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 195589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2432645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 118167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2316325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54054984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293442 # Number of read requests accepted +system.physmem.writeReqs 813160 # Number of write requests accepted +system.physmem.readBursts 15293442 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813160 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978220224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 560064 # Total number of bytes read from write queue +system.physmem.bytesWritten 6909248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131004072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800740 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8751 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705188 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4685 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955866 # Per bank write bursts +system.physmem.perBankRdBursts::1 955512 # Per bank write bursts +system.physmem.perBankRdBursts::2 954595 # Per bank write bursts +system.physmem.perBankRdBursts::3 954812 # Per bank write bursts +system.physmem.perBankRdBursts::4 955762 # Per bank write bursts +system.physmem.perBankRdBursts::5 955910 # Per bank write bursts +system.physmem.perBankRdBursts::6 954892 # Per bank write bursts +system.physmem.perBankRdBursts::7 954654 # Per bank write bursts +system.physmem.perBankRdBursts::8 956247 # Per bank write bursts +system.physmem.perBankRdBursts::9 955899 # Per bank write bursts +system.physmem.perBankRdBursts::10 954311 # Per bank write bursts +system.physmem.perBankRdBursts::11 954068 # Per bank write bursts +system.physmem.perBankRdBursts::12 956211 # Per bank write bursts +system.physmem.perBankRdBursts::13 955980 # Per bank write bursts +system.physmem.perBankRdBursts::14 955097 # Per bank write bursts +system.physmem.perBankRdBursts::15 954875 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6461 # Per bank write bursts +system.physmem.perBankWrBursts::2 6610 # Per bank write bursts +system.physmem.perBankWrBursts::3 6631 # Per bank write bursts +system.physmem.perBankWrBursts::4 6571 # Per bank write bursts +system.physmem.perBankWrBursts::5 6830 # Per bank write bursts +system.physmem.perBankWrBursts::6 6820 # Per bank write bursts +system.physmem.perBankWrBursts::7 6764 # Per bank write bursts +system.physmem.perBankWrBursts::8 7113 # Per bank write bursts +system.physmem.perBankWrBursts::9 6879 # Per bank write bursts +system.physmem.perBankWrBursts::10 6545 # Per bank write bursts +system.physmem.perBankWrBursts::11 6197 # Per bank write bursts +system.physmem.perBankWrBursts::12 7141 # Per bank write bursts +system.physmem.perBankWrBursts::13 6760 # Per bank write bursts +system.physmem.perBankWrBursts::14 7037 # Per bank write bursts +system.physmem.perBankWrBursts::15 6911 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2549324058500 # Total gap between requests +system.physmem.totGap 2549344036000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 42 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154606 # Read request sizes (log2) +system.physmem.readPktSize::6 154584 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59151 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1187642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1126920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1081304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3687011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2647213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2642028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2655762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 54010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59135 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1194358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1134175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1088302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3688965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2641659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2636525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2648641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52098 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -171,418 +159,411 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11344.953359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1015.074534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16830.192081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23626 27.21% 27.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14089 16.23% 43.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2724 3.14% 46.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2126 2.45% 49.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1310 1.51% 50.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1204 1.39% 51.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 811 0.93% 52.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1018 1.17% 54.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 572 0.66% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 583 0.67% 55.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 533 0.61% 55.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 603 0.69% 56.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 265 0.31% 57.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 147 0.17% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 578 0.67% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 113 0.13% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 129 0.15% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 237 0.27% 58.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 56 0.06% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 502 0.58% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 39 0.04% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 171 0.20% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 11 0.01% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 115 0.13% 59.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 15 0.02% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 109 0.13% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 18 0.02% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 54 0.06% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 24 0.03% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 490 0.56% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 7 0.01% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 154 0.18% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 14 0.02% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 32 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 95 0.11% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 14 0.02% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 9 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 155 0.18% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 16 0.02% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 408 0.47% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 96 0.11% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 10 0.01% 61.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 20 0.02% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.01% 61.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 86 0.10% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 6 0.01% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 21 0.02% 62.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 12 0.01% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 58 0.07% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 407 0.47% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 10 0.01% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 18 0.02% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 3 0.00% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 75 0.09% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 12 0.01% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 139 0.16% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 8 0.01% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 72 0.08% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 17 0.02% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 76 0.09% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 9 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 13 0.01% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 144 0.17% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 9 0.01% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 13 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.01% 64.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 6 0.01% 64.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 262 0.30% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 5 0.01% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 136 0.16% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 8 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 21 0.02% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 74 0.09% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 8 0.01% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 452 0.52% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 4 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 13 0.01% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 23 0.03% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 4 0.00% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 73 0.08% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 3 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 132 0.15% 65.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 243 0.28% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 128 0.15% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 66 0.08% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 67 0.08% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 450 0.52% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 67 0.08% 66.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 2 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 1 0.00% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 251 0.29% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 128 0.15% 67.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 66 0.08% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 387 0.45% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 67 0.08% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 121 0.14% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 66 0.08% 68.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 380 0.44% 68.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 37 0.04% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 69 0.08% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 65 0.07% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 389 0.45% 69.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 129 0.15% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 66 0.08% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 120 0.14% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 443 0.51% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 57 0.07% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 13 0.01% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 119 0.14% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 388 0.45% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 123 0.14% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 1 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 64 0.07% 71.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 66 0.08% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 526 0.61% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 68 0.08% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 64 0.07% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 122 0.14% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 391 0.45% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 120 0.14% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 15 0.02% 72.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 57 0.07% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 444 0.51% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 119 0.14% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 66 0.08% 73.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 129 0.15% 73.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 64 0.07% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 70 0.08% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 37 0.04% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 382 0.44% 74.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 65 0.07% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 119 0.14% 75.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 66 0.08% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 385 0.44% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 68 0.08% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 128 0.15% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 69 0.08% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 75.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 253 0.29% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 132 0.15% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 1 0.00% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 67 0.08% 76.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 450 0.52% 76.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 67 0.08% 77.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 129 0.15% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 137 0.16% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 129 0.15% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 67 0.08% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 67 0.08% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 448 0.52% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 1 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 66 0.08% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 134 0.15% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 253 0.29% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 68 0.08% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 129 0.15% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 68 0.08% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 384 0.44% 79.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 66 0.08% 79.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 119 0.14% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 64 0.07% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 380 0.44% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 37 0.04% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 72 0.08% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 65 0.07% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 385 0.44% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 129 0.15% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 64 0.07% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 119 0.14% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 443 0.51% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 56 0.06% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 13 0.01% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 119 0.14% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 1 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 389 0.45% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31815 1 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 124 0.14% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 66 0.08% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 66 0.08% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 65 0.07% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 125 0.14% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 390 0.45% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 119 0.14% 84.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 13 0.01% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 56 0.06% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 441 0.51% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 119 0.14% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 64 0.07% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 129 0.15% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 385 0.44% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 72 0.08% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 37 0.04% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 380 0.44% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 119 0.14% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 66 0.08% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 384 0.44% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 67 0.08% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 128 0.15% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 68 0.08% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 253 0.29% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 134 0.15% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 66 0.08% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 448 0.52% 88.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 68 0.08% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 1 0.00% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 66 0.08% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 129 0.15% 88.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 137 0.16% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 129 0.15% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 67 0.08% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 449 0.52% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 67 0.08% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 132 0.15% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 251 0.29% 90.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 67 0.08% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43392-43399 2 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 128 0.15% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 67 0.08% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 384 0.44% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 68 0.08% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 1 0.00% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44480-44487 1 0.00% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 119 0.14% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 66 0.08% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 383 0.44% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 41 0.05% 91.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 65 0.07% 91.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 385 0.44% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 129 0.15% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 64 0.07% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 119 0.14% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 440 0.51% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 58 0.07% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 14 0.02% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 120 0.14% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 388 0.45% 93.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 122 0.14% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 64 0.07% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 65 0.07% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5147 5.93% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11370.889515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1019.409545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16839.040635 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23447 27.06% 27.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14187 16.38% 43.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2756 3.18% 46.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2051 2.37% 48.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1336 1.54% 50.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1207 1.39% 51.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 834 0.96% 52.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1069 1.23% 54.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 542 0.63% 54.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 595 0.69% 55.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 544 0.63% 56.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 497 0.57% 56.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 259 0.30% 56.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 256 0.30% 57.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 151 0.17% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 457 0.53% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 109 0.13% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 146 0.17% 58.22% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::30720-30727 324 0.37% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 131 0.15% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 65 0.08% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 131 0.15% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 262 0.30% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 128 0.15% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 61 0.07% 82.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 772 0.89% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 61 0.07% 83.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 129 0.15% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 2 0.00% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 2 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 262 0.30% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 131 0.15% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 64 0.07% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 131 0.15% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 325 0.38% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 236 0.27% 84.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 2 0.00% 84.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 137 0.16% 85.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 198 0.23% 85.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36160-36167 1 0.00% 85.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 70 0.08% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 129 0.15% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 384 0.44% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 1 0.00% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 192 0.22% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 312 0.36% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 70 0.08% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 98 0.11% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 64 0.07% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 568 0.66% 87.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 55 0.06% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 1 0.00% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39495 1 0.00% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 182 0.21% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 257 0.30% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 1 0.00% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 136 0.16% 88.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 72 0.08% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 387 0.45% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41024-41031 1 0.00% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 73 0.08% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 135 0.16% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 1 0.00% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 257 0.30% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 183 0.21% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 55 0.06% 89.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 569 0.66% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 66 0.08% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 97 0.11% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 68 0.08% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 314 0.36% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 2 0.00% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 196 0.23% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 386 0.45% 91.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 132 0.15% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 65 0.08% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46016-46023 3 0.00% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 199 0.23% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 135 0.16% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 1 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 239 0.28% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 324 0.37% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 131 0.15% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 64 0.07% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 131 0.15% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 260 0.30% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 128 0.15% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48832-48839 1 0.00% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 61 0.07% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5274 6.09% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50816-50823 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49536-49543 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50311 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86834 # Bytes accessed per row activation -system.physmem.totQLat 369633946000 # Total ticks spent queuing -system.physmem.totMemAccLat 463601929750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76423245000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17544738750 # Total ticks spent accessing banks -system.physmem.avgQLat 24183.35 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.87 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::51200-51207 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86636 # Bytes accessed per row activation +system.physmem.totQLat 369559391250 # Total ticks spent queuing +system.physmem.totMemAccLat 463610140000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76423455000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17627293750 # Total ticks spent accessing banks +system.physmem.avgQLat 24178.40 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1153.26 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30331.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30331.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -592,24 +573,35 @@ system.physmem.busUtilRead 3.00 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15212610 # Number of row buffer hits during reads -system.physmem.writeRowHits 93178 # Number of row buffer hits during writes +system.physmem.readRowHits 15212838 # Number of row buffer hits during reads +system.physmem.writeRowHits 93174 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes -system.physmem.avgGap 158277.83 # Average gap between requests +system.physmem.avgGap 158279.45 # Average gap between requests system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54996997 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346113 # Transaction distribution -system.membus.trans_dist::ReadResp 16346116 # Transaction distribution +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54995612 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346068 # Transaction distribution +system.membus.trans_dist::ReadResp 16346071 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59151 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4708 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4711 # Transaction distribution -system.membus.trans_dist::ReadExReq 131399 # Transaction distribution -system.membus.trans_dist::ReadExResp 131399 # Transaction distribution +system.membus.trans_dist::Writeback 59135 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4685 # Transaction distribution +system.membus.trans_dist::ReadExReq 131422 # Transaction distribution +system.membus.trans_dist::ReadExResp 131422 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution @@ -617,261 +609,255 @@ system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885807 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272561 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550305 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550193 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696716 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19094701 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16694284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19092269 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140205229 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140205229 # Total data (bytes) +system.membus.tot_pkt_size::total 140202797 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140202797 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487741000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487346000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3601000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3636500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17567405000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17566569000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737923280 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4736419263 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34188515482 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34186627978 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 64379 # number of replacements -system.l2c.tags.tagsinuse 51427.622498 # Cycle average of tags in use -system.l2c.tags.total_refs 1904241 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129768 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.674195 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2512188924000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36951.825179 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.926736 # Average occupied blocks per requestor +system.l2c.tags.replacements 64357 # number of replacements +system.l2c.tags.tagsinuse 51453.251473 # Cycle average of tags in use +system.l2c.tags.total_refs 1905423 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129744 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.686020 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2512210729500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36987.198092 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.713113 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4986.850446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3336.949611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.947160 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3226.583152 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2894.539843 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563840 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000289 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4872.243485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3313.752357 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.584037 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3345.363294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2901.396724 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564380 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.076093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050918 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049234 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044167 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784723 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32603 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 505956 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 182118 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 205502 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435201 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits -system.l2c.Writeback_hits::total 608382 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 22 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 40 # number of 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overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1066,43 +1040,43 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58456334 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676393 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676395 # Transaction distribution +system.toL2Bus.throughput 58478558 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677542 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677544 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608382 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2974 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246144 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246144 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608494 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246169 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246169 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967115 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798220 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37803 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149157 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952295 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62908992 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85598765 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148816461 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148816461 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 207744 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964319701 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798582 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38031 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149645 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7954666 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62951744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85614957 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254244 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148876637 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148876637 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 205392 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4965399712 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4431802148 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4434611165 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4486267320 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4486677044 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24046904 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24152407 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86228845 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86557036 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48444532 # Throughput (bytes/s) +system.iobus.throughput 48444152 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution @@ -1212,40 +1186,40 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41492591518 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41494630022 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7178846 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5689563 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 376334 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4735029 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3823898 # Number of BTB hits +system.cpu0.branchPred.lookups 7183590 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5694303 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377290 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4721847 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3824688 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.757647 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 708733 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 80.999829 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 708757 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39349 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25686724 # DTB read hits -system.cpu0.dtb.read_misses 37672 # DTB read misses -system.cpu0.dtb.write_hits 5882199 # DTB write hits -system.cpu0.dtb.write_misses 9157 # DTB write misses +system.cpu0.dtb.read_hits 25676392 # DTB read hits +system.cpu0.dtb.read_misses 38073 # DTB read misses +system.cpu0.dtb.write_hits 5871403 # DTB write hits +system.cpu0.dtb.write_misses 9193 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5402 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1359 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 227 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5420 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25724396 # DTB read accesses -system.cpu0.dtb.write_accesses 5891356 # DTB write accesses +system.cpu0.dtb.perms_faults 585 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25714465 # DTB read accesses +system.cpu0.dtb.write_accesses 5880596 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31568923 # DTB hits -system.cpu0.dtb.misses 46829 # DTB misses -system.cpu0.dtb.accesses 31615752 # DTB accesses -system.cpu0.itb.inst_hits 5794960 # ITB inst hits -system.cpu0.itb.inst_misses 6979 # ITB inst misses +system.cpu0.dtb.hits 31547795 # DTB hits +system.cpu0.dtb.misses 47266 # DTB misses +system.cpu0.dtb.accesses 31595061 # DTB accesses +system.cpu0.itb.inst_hits 5793609 # ITB inst hits +system.cpu0.itb.inst_misses 6965 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1254,114 +1228,114 @@ system.cpu0.itb.flush_tlb 257 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2537 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2542 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1475 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5801939 # ITB inst accesses -system.cpu0.itb.hits 5794960 # DTB hits -system.cpu0.itb.misses 6979 # DTB misses -system.cpu0.itb.accesses 5801939 # DTB accesses -system.cpu0.numCycles 241329954 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5800574 # ITB inst accesses +system.cpu0.itb.hits 5793609 # DTB hits +system.cpu0.itb.misses 6965 # DTB misses +system.cpu0.itb.accesses 5800574 # DTB accesses +system.cpu0.numCycles 241355643 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15402359 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 44612176 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7178846 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4532631 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10046821 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2409329 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81802 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48777724 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1779 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1966 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 42894 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1416575 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 470 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5793020 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368373 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3163 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77432013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.722773 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.070911 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15408312 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 44581736 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7183590 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4533445 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10042154 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2412494 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81949 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48815807 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1726 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1993 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 42608 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1411972 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5791670 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368874 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3149 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77468964 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.722040 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.069743 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67393349 87.04% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 663167 0.86% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 850708 1.10% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1161944 1.50% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1070979 1.38% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 538004 0.69% 92.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1258402 1.63% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 372673 0.48% 94.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4122787 5.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67434698 87.05% 87.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 662922 0.86% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 849826 1.10% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1158615 1.50% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1071303 1.38% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 540404 0.70% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1264103 1.63% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 371341 0.48% 94.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4115752 5.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77432013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029747 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.184860 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16324291 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49901037 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9152885 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 482910 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1568783 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 985989 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 93507 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53239353 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 312067 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1568783 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17193647 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20516369 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 26371209 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8691714 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3088262 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50703360 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7236 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 484563 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2089605 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 237 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 52223867 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 231534090 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 214067803 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5431 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38086867 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14136999 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 416413 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 366902 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6391113 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9801074 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6698586 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1023553 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1394670 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47085778 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 981191 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61028996 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9766291 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24255892 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256976 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77432013 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.788162 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.509612 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77468964 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029764 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.184714 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16332862 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49931887 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9147459 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 483482 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1571127 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 985970 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 93586 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53203424 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 313882 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1571127 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17204608 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20551297 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 26349401 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8685161 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3105311 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50667470 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7242 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 502803 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2087731 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 194 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 52194379 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 231353972 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 213903823 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5361 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38031727 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14162651 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 415813 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 366209 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6409920 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9794680 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6688167 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1031152 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1299354 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47050561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 979447 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 60972564 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 88288 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9787230 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24359943 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256705 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77468964 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.787058 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.508592 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55649099 71.87% 71.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6737778 8.70% 80.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3435441 4.44% 85.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2925983 3.78% 88.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6185685 7.99% 96.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1437832 1.86% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 773159 1.00% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224755 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 62281 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55694568 71.89% 71.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6744950 8.71% 80.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3431902 4.43% 85.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2928703 3.78% 88.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6175861 7.97% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1433177 1.85% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 773017 1.00% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224018 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 62768 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77432013 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77468964 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29912 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30016 0.67% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available @@ -1390,504 +1364,504 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4221653 94.70% 95.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206360 4.63% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4221900 94.67% 95.34% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207684 4.66% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 165947 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28282024 46.34% 46.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46844 0.08% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1271 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26348641 43.17% 89.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6184237 10.13% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 165809 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28246973 46.33% 46.60% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46806 0.08% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1267 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26338371 43.20% 89.88% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6173305 10.12% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61028996 # Type of FU issued -system.cpu0.iq.rate 0.252886 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4457926 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073046 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 204069737 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57841875 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 42095336 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12029 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6474 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5396 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 65314591 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6384 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 305188 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 60972564 # Type of FU issued +system.cpu0.iq.rate 0.252625 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4459601 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073141 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 203996977 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57825737 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 42036875 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12074 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6420 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 65259915 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6441 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 303470 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2103037 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3902 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15671 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 837358 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2107176 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15490 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 838182 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17232684 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348213 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17232343 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348683 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1568783 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15829049 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 237688 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 48167223 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105126 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9801074 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6698586 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 691561 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54422 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4242 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15671 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 182031 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 143561 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 325592 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 59970791 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26024613 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1058205 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1571127 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15861030 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 237452 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 48130825 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105592 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9794680 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6688167 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 690516 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54721 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15490 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 181987 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144371 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 326358 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 59914186 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26012956 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1058378 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 100254 # number of nop insts executed -system.cpu0.iew.exec_refs 32151728 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5674244 # Number of branches executed -system.cpu0.iew.exec_stores 6127115 # Number of stores executed -system.cpu0.iew.exec_rate 0.248501 # Inst execution rate -system.cpu0.iew.wb_sent 59482820 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 42100732 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22797313 # num instructions producing a value -system.cpu0.iew.wb_consumers 41683102 # num instructions consuming a value +system.cpu0.iew.exec_nop 100817 # number of nop insts executed +system.cpu0.iew.exec_refs 32128938 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5674429 # Number of branches executed +system.cpu0.iew.exec_stores 6115982 # Number of stores executed +system.cpu0.iew.exec_rate 0.248240 # Inst execution rate +system.cpu0.iew.wb_sent 59424173 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 42042235 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22754717 # num instructions producing a value +system.cpu0.iew.wb_consumers 41618983 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.174453 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546920 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.174192 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546739 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9635326 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 724215 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 284304 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75863230 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.501725 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.477269 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9657152 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 722742 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 285161 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75897837 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.500741 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.473402 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 62300247 82.12% 82.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6632163 8.74% 90.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1905948 2.51% 93.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1063803 1.40% 94.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 963459 1.27% 96.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 539688 0.71% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 720050 0.95% 97.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 348558 0.46% 98.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1389314 1.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 62326931 82.12% 82.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6623929 8.73% 90.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1927651 2.54% 93.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1062809 1.40% 94.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 977806 1.29% 96.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 537572 0.71% 96.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 721191 0.95% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 348340 0.46% 98.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1371608 1.81% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75863230 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29321704 # Number of instructions committed -system.cpu0.commit.committedOps 38062462 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75897837 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29270698 # Number of instructions committed +system.cpu0.commit.committedOps 38005132 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13559265 # Number of memory references committed -system.cpu0.commit.loads 7698037 # Number of loads committed -system.cpu0.commit.membars 204059 # Number of memory barriers committed -system.cpu0.commit.branches 4889328 # Number of branches committed -system.cpu0.commit.fp_insts 5354 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33742241 # Number of committed integer instructions. -system.cpu0.commit.function_calls 497179 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1389314 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13537489 # Number of memory references committed +system.cpu0.commit.loads 7687504 # Number of loads committed +system.cpu0.commit.membars 203418 # Number of memory barriers committed +system.cpu0.commit.branches 4891612 # Number of branches committed +system.cpu0.commit.fp_insts 5306 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33685063 # Number of committed integer instructions. +system.cpu0.commit.function_calls 497791 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1371608 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 121250209 # The number of ROB reads -system.cpu0.rob.rob_writes 97007351 # The number of ROB writes -system.cpu0.timesIdled 906901 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 163897941 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2251401803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29254206 # Number of Instructions Simulated -system.cpu0.committedOps 37994964 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29254206 # Number of Instructions Simulated -system.cpu0.cpi 8.249410 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.249410 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.121221 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.121221 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 271506841 # number of integer regfile reads -system.cpu0.int_regfile_writes 42814380 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22646 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19918 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15055897 # number of misc regfile reads -system.cpu0.misc_regfile_writes 404161 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983492 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.574238 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10516196 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984004 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.687148 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6986136250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 318.901478 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 192.672760 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.622854 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.376314 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5235281 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5280915 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10516196 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5235281 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5280915 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10516196 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5235281 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5280915 # number of overall hits -system.cpu0.icache.overall_hits::total 10516196 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 557620 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 507749 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065369 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 557620 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 507749 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065369 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 557620 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 507749 # number of overall misses -system.cpu0.icache.overall_misses::total 1065369 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7715888650 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6834076460 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14549965110 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7715888650 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6834076460 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14549965110 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7715888650 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6834076460 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14549965110 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5792901 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5788664 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11581565 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5792901 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5788664 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11581565 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5792901 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5788664 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11581565 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096259 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087714 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.091988 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096259 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087714 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.091988 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096259 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087714 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.091988 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13837.180607 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13459.556710 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.207137 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13657.207137 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13657.207137 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6518 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 829 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 410 # number of cycles access was blocked +system.cpu0.rob.rob_reads 121269057 # The number of ROB reads +system.cpu0.rob.rob_writes 96938789 # The number of ROB writes +system.cpu0.timesIdled 907351 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 163886679 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2251360755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29203197 # Number of Instructions Simulated +system.cpu0.committedOps 37937631 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29203197 # Number of Instructions Simulated +system.cpu0.cpi 8.264699 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.264699 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.120997 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.120997 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 271224247 # number of integer regfile reads +system.cpu0.int_regfile_writes 42758050 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22657 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19930 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15040337 # number of misc regfile reads +system.cpu0.misc_regfile_writes 403311 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984140 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.573239 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10515740 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984652 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.679651 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7012159250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 319.827324 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.745915 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.624663 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.374504 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999166 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5233615 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5282125 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10515740 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5233615 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5282125 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10515740 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5233615 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5282125 # number of overall hits +system.cpu0.icache.overall_hits::total 10515740 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 557933 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 508279 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1066212 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 557933 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 508279 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1066212 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 557933 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 508279 # number of overall misses +system.cpu0.icache.overall_misses::total 1066212 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7711361387 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6850959748 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14562321135 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7711361387 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6850959748 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14562321135 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7711361387 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6850959748 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14562321135 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5791548 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5790404 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11581952 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5791548 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5790404 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11581952 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5791548 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5790404 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11581952 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096336 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087780 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092058 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096336 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087780 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092058 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096336 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087780 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.092058 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.303610 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13478.738543 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.997786 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.303610 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13478.738543 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13657.997786 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.303610 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13478.738543 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13657.997786 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6730 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 450 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 431 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.897561 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 829 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.614849 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 450 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38074 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 81323 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 38074 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 81323 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 38074 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 81323 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 514371 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469675 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984046 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 514371 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 469675 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984046 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 514371 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 469675 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984046 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6258994404 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5567069659 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11826064063 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258994404 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5567069659 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11826064063 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258994404 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5567069659 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11826064063 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43117 # number of ReadReq MSHR hits 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-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084967 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084967 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084967 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.795980 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for ReadReq accesses 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miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.918977 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643990 # number of replacements +system.cpu0.dcache.tags.replacements 644131 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.993324 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21534082 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644502 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.411971 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21534637 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644643 # Sample count of references to valid blocks. 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system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6836118 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6942659 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13778777 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3601868 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3659456 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261324 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114429 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 128738 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243167 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116989 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 130670 # number of StoreCondReq hits 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1863754 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711155 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5258794781 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6175311803 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11434106584 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76116558084 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 73496602051 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 149613160135 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106253499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82007996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188261495 # number of LoadLockedReq miss cycles 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StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247677 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12285387 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12465869 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24751256 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12285387 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12465869 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24751256 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045670 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057266 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051548 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.296802 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.282668 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289749 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045303 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052763 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000051 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000092 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150374 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.149509 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149938 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.150374 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.149509 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149938 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16074.813251 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14642.808913 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15268.378012 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50068.250403 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50967.669089 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50506.083198 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14289.066568 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13424.127680 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13898.966039 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15083.500000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43395.456864 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43395.456864 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 38322 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25151 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3482 # number of cycles access was blocked +system.cpu0.dcache.ReadReq_hits::cpu0.data 6830201 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6949651 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13779852 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3598843 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3661860 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7260703 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114028 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129247 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243275 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116593 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131076 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247669 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10429044 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10611511 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21040555 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10429044 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10611511 # number of overall hits +system.cpu0.dcache.overall_hits::total 21040555 # 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uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13713085264 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13059234413 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26772319677 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106071136245 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103026320251 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209097456496 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025358 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027786 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024970 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023736 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055086 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040661 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047508 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000051 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000092 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13978.974235 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13269.059484 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.899713 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46428.448104 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47251.379913 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46828.660302 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12580.254879 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11592.833121 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12136.336094 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106094158515 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103008489165 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209102647680 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025341 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027810 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026594 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024927 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055248 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047467 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000024 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13992.929912 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13244.737489 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13595.823194 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46213.552352 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47507.207423 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46845.248826 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12583.867511 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11609.743295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12145.907145 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1902,38 +1876,38 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7299586 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5849815 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 347289 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4589899 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3862662 # Number of BTB hits +system.cpu1.branchPred.lookups 7296861 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5846678 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347662 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4742078 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3857406 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.155708 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 691728 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34987 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.344212 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 691724 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35172 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25535708 # DTB read hits -system.cpu1.dtb.read_misses 37819 # DTB read misses -system.cpu1.dtb.write_hits 5832824 # DTB write hits -system.cpu1.dtb.write_misses 9748 # DTB write misses +system.cpu1.dtb.read_hits 25545961 # DTB read hits +system.cpu1.dtb.read_misses 37652 # DTB read misses +system.cpu1.dtb.write_hits 5843070 # DTB write hits +system.cpu1.dtb.write_misses 9833 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2100 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5607 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2149 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25573527 # DTB read accesses -system.cpu1.dtb.write_accesses 5842572 # DTB write accesses +system.cpu1.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25583613 # DTB read accesses +system.cpu1.dtb.write_accesses 5852903 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31368532 # DTB hits -system.cpu1.dtb.misses 47567 # DTB misses -system.cpu1.dtb.accesses 31416099 # DTB accesses -system.cpu1.itb.inst_hits 5790816 # ITB inst hits -system.cpu1.itb.inst_misses 7158 # ITB inst misses +system.cpu1.dtb.hits 31389031 # DTB hits +system.cpu1.dtb.misses 47485 # DTB misses +system.cpu1.dtb.accesses 31436516 # DTB accesses +system.cpu1.itb.inst_hits 5792513 # ITB inst hits +system.cpu1.itb.inst_misses 7242 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1942,284 +1916,284 @@ system.cpu1.itb.flush_tlb 255 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2684 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2667 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1580 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1547 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5797974 # ITB inst accesses -system.cpu1.itb.hits 5790816 # DTB hits -system.cpu1.itb.misses 7158 # DTB misses -system.cpu1.itb.accesses 5797974 # DTB accesses -system.cpu1.numCycles 235384601 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5799755 # ITB inst accesses +system.cpu1.itb.hits 5792513 # DTB hits +system.cpu1.itb.misses 7242 # DTB misses +system.cpu1.itb.accesses 5799755 # DTB accesses +system.cpu1.numCycles 235437063 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14589178 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46084175 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7299586 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4554390 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10179964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2322435 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82610 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48394674 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1151 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1760 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 51069 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1300436 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5788667 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 351586 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2955 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76205210 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.749083 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.107109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14594322 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46143705 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7296861 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4549130 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10187153 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2325105 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 84075 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48390355 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1006 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1773 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 50802 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1299927 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5790405 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352119 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3045 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76215873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.749895 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.108619 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66032287 86.65% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 647062 0.85% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 866139 1.14% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1142625 1.50% 90.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1039142 1.36% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 573208 0.75% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1303078 1.71% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 377648 0.50% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4224021 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66035998 86.64% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 646269 0.85% 87.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 866115 1.14% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1144603 1.50% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1038380 1.36% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570616 0.75% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1298592 1.70% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 378941 0.50% 94.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4236359 5.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76205210 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031011 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.195782 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15588837 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49317422 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9252055 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 521656 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1523167 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 986244 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 83403 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54452083 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 278013 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1523167 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16469267 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19674049 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 26510190 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8818021 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3208448 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51956781 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13421 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 604219 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2079670 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 451 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54191440 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237039699 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 219510796 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4998 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 40313487 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13877953 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 415796 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 370913 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6599828 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9995387 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6641278 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 924791 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1180275 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48354458 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1004264 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62036555 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93414 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9463744 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23885542 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 245582 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76205210 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814072 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.522064 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76215873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030993 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.195992 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15595502 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49311936 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9258524 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 522439 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1525385 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 986467 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 83299 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54522655 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 277301 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1525385 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16476975 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19655955 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 26515105 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8823591 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3216801 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 52024243 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13429 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 607553 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2083322 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 488 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54254654 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237368382 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 219812592 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5012 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 40368418 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13886236 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 416636 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 371803 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6618695 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10010762 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6654363 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 928897 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1221940 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48420965 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1005597 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62096685 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94311 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9477685 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23931706 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245448 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76215873 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814747 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.522121 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53886192 70.71% 70.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6968313 9.14% 79.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3603419 4.73% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3067011 4.02% 88.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6180907 8.11% 96.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1416351 1.86% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 790440 1.04% 99.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 228268 0.30% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64309 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53862159 70.67% 70.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6987914 9.17% 79.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3609115 4.74% 84.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3073312 4.03% 88.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6185840 8.12% 96.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1415029 1.86% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 789705 1.04% 99.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 228522 0.30% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64277 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76205210 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76215873 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29954 0.68% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 6 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4154847 94.70% 95.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 202692 4.62% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 30122 0.69% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4155854 94.74% 95.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200598 4.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 197719 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29431617 47.44% 47.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46723 0.08% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 843 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26206761 42.24% 90.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6152865 9.92% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 197857 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29468242 47.46% 47.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46687 0.08% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 846 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26218549 42.22% 90.07% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6164475 9.93% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62036555 # Type of FU issued -system.cpu1.iq.rate 0.263554 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4387499 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070724 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 204795562 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58831312 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43493604 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11047 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6062 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4926 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66220464 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5871 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 319800 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62096685 # Type of FU issued +system.cpu1.iq.rate 0.263751 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4386578 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070641 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 204926211 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58913069 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43552448 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11222 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6050 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4957 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66279422 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5984 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 320383 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2036379 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2915 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15518 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 769053 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2041284 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2958 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15466 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 770955 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16877667 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 333288 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16877302 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 331906 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1523167 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14985510 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 225691 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49480647 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96107 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9995387 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6641278 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 719443 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50947 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6143 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15518 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 171517 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 135143 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 306660 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 61000330 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25886068 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1036225 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1525385 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14957873 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 224833 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49549209 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 95185 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 10010762 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6654363 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 720304 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50705 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4281 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15466 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 171203 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 135670 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 306873 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 61058870 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25897367 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1037815 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 121925 # number of nop insts executed -system.cpu1.iew.exec_refs 31986182 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5823905 # Number of branches executed -system.cpu1.iew.exec_stores 6100114 # Number of stores executed -system.cpu1.iew.exec_rate 0.259152 # Inst execution rate -system.cpu1.iew.wb_sent 60530443 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43498530 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24164344 # num instructions producing a value -system.cpu1.iew.wb_consumers 44485345 # num instructions consuming a value +system.cpu1.iew.exec_nop 122647 # number of nop insts executed +system.cpu1.iew.exec_refs 32008147 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5821795 # Number of branches executed +system.cpu1.iew.exec_stores 6110780 # Number of stores executed +system.cpu1.iew.exec_rate 0.259343 # Inst execution rate +system.cpu1.iew.wb_sent 60589807 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43557405 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24211075 # num instructions producing a value +system.cpu1.iew.wb_consumers 44594441 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.184798 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543198 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.185007 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.542917 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9351616 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 758682 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 265186 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74682043 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.531552 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.520144 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9363446 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 760149 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 265641 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74690488 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.532256 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.520816 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60574973 81.11% 81.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6925092 9.27% 90.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1956264 2.62% 93.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1088628 1.46% 94.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1022152 1.37% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 532797 0.71% 96.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 718663 0.96% 97.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378466 0.51% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1485008 1.99% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60561931 81.08% 81.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6932594 9.28% 90.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1961063 2.63% 92.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1092193 1.46% 94.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1024970 1.37% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 536622 0.72% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 713910 0.96% 97.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 380912 0.51% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1486293 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74682043 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31143561 # Number of instructions committed -system.cpu1.commit.committedOps 39697401 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74690488 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31194382 # Number of instructions committed +system.cpu1.commit.committedOps 39754477 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13831233 # Number of memory references committed -system.cpu1.commit.loads 7959008 # Number of loads committed -system.cpu1.commit.membars 199700 # Number of memory barriers committed -system.cpu1.commit.branches 5073252 # Number of branches committed -system.cpu1.commit.fp_insts 4858 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 35121772 # Number of committed integer instructions. -system.cpu1.commit.function_calls 494294 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1485008 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13852886 # Number of memory references committed +system.cpu1.commit.loads 7969478 # Number of loads committed +system.cpu1.commit.membars 200339 # Number of memory barriers committed +system.cpu1.commit.branches 5070949 # Number of branches committed +system.cpu1.commit.fp_insts 4906 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 35178713 # Number of committed integer instructions. +system.cpu1.commit.function_calls 493679 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1486293 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 121317994 # The number of ROB reads -system.cpu1.rob.rob_writes 99664484 # The number of ROB writes -system.cpu1.timesIdled 865516 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159179391 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2318646728 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31060678 # Number of Instructions Simulated -system.cpu1.committedOps 39614518 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 31060678 # Number of Instructions Simulated -system.cpu1.cpi 7.578218 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.578218 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.131957 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.131957 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 276434717 # number of integer regfile reads -system.cpu1.int_regfile_writes 44854574 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22375 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19728 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15285924 # number of misc regfile reads -system.cpu1.misc_regfile_writes 428613 # number of misc regfile writes +system.cpu1.rob.rob_reads 121392021 # The number of ROB reads +system.cpu1.rob.rob_writes 99804752 # The number of ROB writes +system.cpu1.timesIdled 864703 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159221190 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2318646914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31111502 # Number of Instructions Simulated +system.cpu1.committedOps 39671597 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 31111502 # Number of Instructions Simulated +system.cpu1.cpi 7.567525 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.567525 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132144 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132144 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 276724007 # number of integer regfile reads +system.cpu1.int_regfile_writes 44911737 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22398 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19708 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15283998 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429459 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2234,10 +2208,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518441783518 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518441783518 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518454987022 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518454987022 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 78712e3a3..927b487de 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,22 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -112,6 +121,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -134,18 +144,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -156,6 +169,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -178,14 +192,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -204,18 +221,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -227,6 +247,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -248,17 +269,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -277,30 +301,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -313,6 +343,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -335,6 +366,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -344,6 +376,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -366,6 +399,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -373,6 +407,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -384,6 +419,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -410,6 +446,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -421,19 +458,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -443,6 +484,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -452,6 +494,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -480,6 +523,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -489,8 +533,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -502,6 +578,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -517,6 +594,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -531,6 +610,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -540,6 +620,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -561,8 +642,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -571,6 +654,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -581,6 +665,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -591,6 +676,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -601,6 +687,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -615,6 +702,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -628,6 +716,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -645,6 +734,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -657,6 +747,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -668,6 +759,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -678,6 +770,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -690,6 +783,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -703,6 +797,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -713,6 +808,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -723,6 +819,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -733,6 +830,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -745,6 +843,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -759,6 +858,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -771,6 +871,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -785,6 +886,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -795,6 +897,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -805,6 +908,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -815,6 +919,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -823,6 +928,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -831,6 +937,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -840,11 +947,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 87a0dc109..98143dc12 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,145 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.631415 # Number of seconds simulated -sim_ticks 2631415171500 # Number of ticks simulated -final_tick 2631415171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629717 # Number of seconds simulated +sim_ticks 2629717216500 # Number of ticks simulated +final_tick 2629717216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 471038 # Simulator instruction rate (inst/s) -host_op_rate 599389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20585916294 # Simulator tick rate (ticks/s) -host_mem_usage 424736 # Number of bytes of host memory used -host_seconds 127.83 # Real time elapsed on the host -sim_insts 60210883 # Number of instructions simulated -sim_ops 76617506 # Number of ops (including micro ops) simulated +host_inst_rate 340896 # Simulator instruction rate (inst/s) +host_op_rate 433786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14888327014 # Simulator tick rate (ticks/s) +host_mem_usage 445372 # Number of bytes of host memory used +host_seconds 176.63 # Real time elapsed on the host +sim_insts 60212334 # Number of instructions simulated +sim_ops 76619433 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 278752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4724944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 298016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4661584 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4336188 # Number of bytes read from this memory -system.physmem.bytes_read::total 134022064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 278752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704484 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1530592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1485560 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706648 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 406404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4399060 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 298016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704420 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3689984 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1527272 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1489008 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73861 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10859 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 72871 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67782 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690904 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 382648 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 371390 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811702 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47220316 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6366 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68770 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690901 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57656 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381818 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372252 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811726 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47250805 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 105932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1795590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1772656 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 161788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1647854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50931554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 105932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 161788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402476 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 581661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 564548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2548685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47220316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 154543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1672826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50964230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 154543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267869 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1403187 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 580774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566224 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550184 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1403187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47250805 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 105932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2377252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2353430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 161788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2212402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53480239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690904 # Number of read requests accepted -system.physmem.writeReqs 811702 # Number of write requests accepted -system.physmem.readBursts 15690904 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811702 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004216000 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 154543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2239050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53514414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690901 # Number of read requests accepted +system.physmem.writeReqs 811726 # Number of write requests accepted +system.physmem.readBursts 15690901 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811726 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004215808 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6838848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134022064 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706648 # Total written bytes from the system interface side +system.physmem.bytesWritten 6837952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706264 # Total written bytes from the system interface side system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704845 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 704883 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4518 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980392 # Per bank write bursts system.physmem.perBankRdBursts::1 980205 # Per bank write bursts system.physmem.perBankRdBursts::2 980222 # Per bank write bursts -system.physmem.perBankRdBursts::3 980428 # Per bank write bursts +system.physmem.perBankRdBursts::3 980431 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts -system.physmem.perBankRdBursts::5 980709 # Per bank write bursts -system.physmem.perBankRdBursts::6 980611 # Per bank write bursts -system.physmem.perBankRdBursts::7 980420 # Per bank write bursts +system.physmem.perBankRdBursts::5 980708 # Per bank write bursts +system.physmem.perBankRdBursts::6 980610 # Per bank write bursts +system.physmem.perBankRdBursts::7 980424 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts -system.physmem.perBankRdBursts::11 979555 # Per bank write bursts -system.physmem.perBankRdBursts::12 980153 # Per bank write bursts -system.physmem.perBankRdBursts::13 980095 # Per bank write bursts -system.physmem.perBankRdBursts::14 980165 # Per bank write bursts +system.physmem.perBankRdBursts::11 979558 # Per bank write bursts +system.physmem.perBankRdBursts::12 980154 # Per bank write bursts +system.physmem.perBankRdBursts::13 980093 # Per bank write bursts +system.physmem.perBankRdBursts::14 980155 # Per bank write bursts system.physmem.perBankRdBursts::15 980109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6734 # Per bank write bursts -system.physmem.perBankWrBursts::1 6600 # Per bank write bursts -system.physmem.perBankWrBursts::2 6608 # Per bank write bursts -system.physmem.perBankWrBursts::3 6671 # Per bank write bursts -system.physmem.perBankWrBursts::4 6747 # Per bank write bursts -system.physmem.perBankWrBursts::5 7057 # Per bank write bursts -system.physmem.perBankWrBursts::6 7034 # Per bank write bursts -system.physmem.perBankWrBursts::7 6884 # Per bank write bursts -system.physmem.perBankWrBursts::8 7000 # Per bank write bursts -system.physmem.perBankWrBursts::9 6825 # Per bank write bursts +system.physmem.perBankWrBursts::0 6731 # Per bank write bursts +system.physmem.perBankWrBursts::1 6599 # Per bank write bursts +system.physmem.perBankWrBursts::2 6610 # Per bank write bursts +system.physmem.perBankWrBursts::3 6672 # Per bank write bursts +system.physmem.perBankWrBursts::4 6746 # Per bank write bursts +system.physmem.perBankWrBursts::5 7052 # Per bank write bursts +system.physmem.perBankWrBursts::6 7033 # Per bank write bursts +system.physmem.perBankWrBursts::7 6881 # Per bank write bursts +system.physmem.perBankWrBursts::8 7002 # Per bank write bursts +system.physmem.perBankWrBursts::9 6827 # Per bank write bursts system.physmem.perBankWrBursts::10 6323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6129 # Per bank write bursts +system.physmem.perBankWrBursts::11 6122 # Per bank write bursts system.physmem.perBankWrBursts::12 6612 # Per bank write bursts -system.physmem.perBankWrBursts::13 6395 # Per bank write bursts -system.physmem.perBankWrBursts::14 6622 # Per bank write bursts +system.physmem.perBankWrBursts::13 6399 # Per bank write bursts +system.physmem.perBankWrBursts::14 6618 # Per bank write bursts system.physmem.perBankWrBursts::15 6616 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2631410752000 # Total gap between requests +system.physmem.totGap 2629712785000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6700 # Read request sizes (log2) +system.physmem.readPktSize::2 6706 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152172 # Read request sizes (log2) +system.physmem.readPktSize::6 152163 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754038 # Write request sizes (log2) +system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57664 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1280991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1124435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1124568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3790382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2700913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2699740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2717442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 51875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 37 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57656 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1290849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1134741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1135188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3791353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2690884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2690157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2706986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 51561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 56279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -155,28 +167,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4689 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -187,301 +199,302 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11200.204894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1031.239605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16762.903946 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23441 25.97% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14726 16.31% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2829 3.13% 45.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2153 2.39% 47.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1359 1.51% 49.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1176 1.30% 50.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 955 1.06% 51.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1145 1.27% 52.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 612 0.68% 53.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 559 0.62% 54.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 621 0.69% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 534 0.59% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 322 0.36% 55.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 268 0.30% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 218 0.24% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 586 0.65% 57.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 164 0.18% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 127 0.14% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 130 0.14% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 257 0.28% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 89 0.10% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 142 0.16% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 48 0.05% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 45 0.05% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 41 0.05% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 166 0.18% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 19 0.02% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 18 0.02% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 150 0.17% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 341 0.38% 61.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 19 0.02% 61.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 17 0.02% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 76 0.08% 61.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 15 0.02% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 8 0.01% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 16 0.02% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 76 0.08% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 11 0.01% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 6 0.01% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 22 0.02% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 3 0.00% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 382 0.42% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 6 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 146 0.16% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 2 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 137 0.15% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 197 0.22% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 7 0.01% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 32 0.04% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 137 0.15% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 6 0.01% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 2 0.00% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 6 0.01% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 337 0.37% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 1 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 1 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 130 0.14% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 1 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 71 0.08% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 129 0.14% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 75 0.08% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 261 0.29% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 1 0.00% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 1 0.00% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 62 0.07% 64.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 15 0.02% 64.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 204 0.23% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 122 0.14% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 133 0.15% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 389 0.43% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 64 0.07% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 120 0.13% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 252 0.28% 65.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 133 0.15% 65.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 13 0.01% 66.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 68 0.08% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 520 0.58% 66.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 68 0.08% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 11 0.01% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 136 0.15% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 250 0.28% 67.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 121 0.13% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 68 0.08% 67.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 388 0.43% 67.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 132 0.15% 68.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 121 0.13% 68.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 2 0.00% 68.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 55 0.06% 68.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 259 0.29% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 71 0.08% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 69 0.08% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.14% 68.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 328 0.36% 69.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 133 0.15% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 193 0.21% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 136 0.15% 69.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 377 0.42% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 11 0.01% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 64 0.07% 70.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 322 0.36% 70.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 132 0.15% 70.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 68 0.08% 70.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 129 0.14% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 391 0.43% 71.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 67 0.07% 71.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 129 0.14% 71.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 641 0.71% 72.34% # Bytes accessed per row activation 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Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23393 25.86% 25.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14737 16.29% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2929 3.24% 45.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2185 2.42% 47.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1403 1.55% 49.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1153 1.27% 50.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 940 1.04% 51.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1175 1.30% 52.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 610 0.67% 53.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 557 0.62% 54.26% # Bytes accessed per row activation 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0.01% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 271 0.30% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 14 0.02% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 4 0.00% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 136 0.15% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 11 0.01% 63.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 341 0.38% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 2 0.00% 64.26% # Bytes accessed per row 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261 0.29% 66.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 193 0.21% 66.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 9 0.01% 66.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 455 0.50% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 64 0.07% 67.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 5 0.01% 67.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 257 0.28% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10183 1 0.00% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 265 0.29% 67.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 124 0.14% 68.09% # Bytes accessed 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-system.physmem.bytesPerActivate::48896-48903 131 0.15% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5359 5.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90271 # Bytes accessed per row activation -system.physmem.totQLat 377292466250 # Total ticks spent queuing -system.physmem.totMemAccLat 474547986250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454375000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18801145000 # Total ticks spent accessing banks -system.physmem.avgQLat 24045.34 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1198.22 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 73 0.08% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 459 0.51% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 3 0.00% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 69 0.08% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48448-48455 1 0.00% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 129 0.14% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 129 0.14% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5220 5.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90454 # Bytes accessed per row activation +system.physmem.totQLat 377144928750 # Total ticks spent queuing +system.physmem.totMemAccLat 474552728750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454360000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18953440000 # Total ticks spent accessing banks +system.physmem.avgQLat 24035.94 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1207.93 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30243.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30243.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage @@ -489,268 +502,256 @@ system.physmem.busUtilRead 2.98 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing -system.physmem.readRowHits 15616441 # Number of row buffer hits during reads -system.physmem.writeRowHits 91020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.18 # Row buffer hit rate for writes -system.physmem.avgGap 159454.26 # Average gap between requests +system.physmem.readRowHits 15616330 # Number of row buffer hits during reads +system.physmem.writeRowHits 90931 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.11 # Row buffer hit rate for writes +system.physmem.avgGap 159351.16 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54391586 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743633 # Transaction distribution -system.membus.trans_dist::ReadResp 16743633 # Transaction distribution -system.membus.trans_dist::WriteReq 763392 # Transaction distribution -system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57664 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131346 # Transaction distribution -system.membus.trans_dist::ReadExResp 131346 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 2.39 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54426353 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743636 # Transaction distribution +system.membus.trans_dist::ReadResp 16743636 # Transaction distribution +system.membus.trans_dist::WriteReq 763424 # Transaction distribution +system.membus.trans_dist::WriteResp 763424 # Transaction distribution +system.membus.trans_dist::Writeback 57656 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4518 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4518 # Transaction distribution +system.membus.trans_dist::ReadExReq 131342 # Transaction distribution +system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892518 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892570 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279432 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343440 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343496 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870589 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471520 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18869661 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143126845 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143126845 # Total data (bytes) +system.membus.tot_pkt_size::total 143125917 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143125917 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1220589500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225680000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3747000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3756000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18118484000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171618500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4951896724 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4990533473 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35075499000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35075577250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 62057 # number of replacements -system.l2c.tags.tagsinuse 51615.015118 # Cycle average of tags in use -system.l2c.tags.total_refs 1699237 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127445 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.333101 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2576505750500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38217.986822 # Average occupied blocks per requestor +system.l2c.tags.replacements 62046 # number of replacements +system.l2c.tags.tagsinuse 51605.865819 # Cycle average of tags in use +system.l2c.tags.total_refs 1699437 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127429 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.336344 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574782383500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38213.733489 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2603.292629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3037.110347 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2749.245070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3097.480060 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4418.327235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3338.297198 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583160 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4271.539066 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3273.867246 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583095 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.039723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046343 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.041950 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.047264 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.067418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050938 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787583 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9914 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3649 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 415311 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183212 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10008 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3517 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 429187 # number of ReadReq hits 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10051 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 432141 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187290 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242055 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596450 # number of Writeback hits +system.l2c.Writeback_hits::total 596450 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56696 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57849 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114545 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9914 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3649 # number of 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-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58702.597502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58617.684463 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -902,45 +903,45 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52751818 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471631 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471631 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596380 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2913 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2913 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247521 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247521 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725079 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753474 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20108 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549204 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54752376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83781573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138642313 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138642313 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 169620 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808134500 # Layer occupancy (ticks) +system.toL2Bus.throughput 52790683 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471881 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471881 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763424 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763424 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596450 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247508 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247508 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725145 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20211 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50526 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549672 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83791781 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28748 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138654661 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138654661 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169908 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808598000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865505750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865648250 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420696776 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4421117527 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12940000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13024000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30620250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30647250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48128720 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715358 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715358 # Transaction distribution +system.iobus.throughput 48159799 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution system.iobus.trans_dist::WriteResp 8167 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -962,12 +963,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -989,14 +990,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646645 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646645 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646653 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1042,141 +1043,141 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374819000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42584048000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42583673750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7352406 # DTB read hits -system.cpu0.dtb.read_misses 6766 # DTB read misses -system.cpu0.dtb.write_hits 5599485 # DTB write hits -system.cpu0.dtb.write_misses 1847 # DTB write misses -system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7421376 # DTB read hits +system.cpu0.dtb.read_misses 6854 # DTB read misses +system.cpu0.dtb.write_hits 5628030 # DTB write hits +system.cpu0.dtb.write_misses 1815 # DTB write misses +system.cpu0.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6337 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 131 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 151 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7359172 # DTB read accesses -system.cpu0.dtb.write_accesses 5601332 # DTB write accesses +system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7428230 # DTB read accesses +system.cpu0.dtb.write_accesses 5629845 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12951891 # DTB hits -system.cpu0.dtb.misses 8613 # DTB misses -system.cpu0.dtb.accesses 12960504 # DTB accesses -system.cpu0.itb.inst_hits 30170189 # ITB inst hits -system.cpu0.itb.inst_misses 3579 # ITB inst misses +system.cpu0.dtb.hits 13049406 # DTB hits +system.cpu0.dtb.misses 8669 # DTB misses +system.cpu0.dtb.accesses 13058075 # DTB accesses +system.cpu0.itb.inst_hits 30610107 # ITB inst hits +system.cpu0.itb.inst_misses 3562 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2748 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30173768 # ITB inst accesses -system.cpu0.itb.hits 30170189 # DTB hits -system.cpu0.itb.misses 3579 # DTB misses -system.cpu0.itb.accesses 30173768 # DTB accesses -system.cpu0.numCycles 2629696361 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30613669 # ITB inst accesses +system.cpu0.itb.hits 30610107 # DTB hits +system.cpu0.itb.misses 3562 # DTB misses +system.cpu0.itb.accesses 30613669 # DTB accesses +system.cpu0.numCycles 2628235952 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29597158 # Number of instructions committed -system.cpu0.committedOps 37762240 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33970200 # Number of integer alu accesses +system.cpu0.committedInsts 29990580 # Number of instructions committed +system.cpu0.committedOps 38158663 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34282971 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses -system.cpu0.num_func_calls 1050225 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3920547 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33970200 # number of integer instructions +system.cpu0.num_func_calls 1059870 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3968282 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34282971 # number of integer instructions system.cpu0.num_fp_insts 4584 # number of float instructions -system.cpu0.num_int_register_reads 194623734 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36521551 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3225 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1362 # number of times the floating registers were written -system.cpu0.num_mem_refs 13522491 # number of memory refs -system.cpu0.num_load_insts 7673972 # Number of load instructions -system.cpu0.num_store_insts 5848519 # Number of store instructions -system.cpu0.num_idle_cycles 2290697984.129271 # Number of idle cycles -system.cpu0.num_busy_cycles 338998376.870729 # Number of busy cycles -system.cpu0.not_idle_fraction 0.128912 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.871088 # Percentage of idle cycles +system.cpu0.num_int_register_reads 196555242 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36964020 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3346 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1240 # number of times the floating registers were written +system.cpu0.num_mem_refs 13622094 # number of memory refs +system.cpu0.num_load_insts 7743834 # Number of load instructions +system.cpu0.num_store_insts 5878260 # Number of store instructions +system.cpu0.num_idle_cycles 2282805163.828333 # Number of idle cycles +system.cpu0.num_busy_cycles 345430788.171666 # Number of busy cycles +system.cpu0.not_idle_fraction 0.131431 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.868569 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856199 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.856725 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60648231 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856711 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.791937 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20135568250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 208.641443 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 302.215282 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.407503 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.590264 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997767 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29750188 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30898043 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60648231 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29750188 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30898043 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60648231 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29750188 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30898043 # number of overall hits -system.cpu0.icache.overall_hits::total 60648231 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 420001 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 436711 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856712 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 420001 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 436711 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856712 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 420001 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 436711 # number of overall misses -system.cpu0.icache.overall_misses::total 856712 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5711192500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6097938000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11809130500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5711192500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6097938000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11809130500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5711192500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6097938000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11809130500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30170189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 31334754 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61504943 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30170189 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 31334754 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61504943 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30170189 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 31334754 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61504943 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013921 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013937 # miss rate for ReadReq accesses +system.cpu0.icache.tags.replacements 856230 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.853093 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60649685 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856742 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.791072 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20173406250 # Cycle when the warmup percentage was hit. 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# average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13963.325861 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13784.247799 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13784.247799 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13784.247799 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13647.206662 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.046955 # average 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-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046706 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12895.795169 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.308764 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12849.005588 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44322.826008 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42637.383226 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43495.354996 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11400.450082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12363.877700 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11855.189250 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596450 # number of writebacks +system.cpu0.dcache.writebacks::total 596450 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182495 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186610 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369105 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126878 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 123539 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250417 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6016 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5563 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11579 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309373 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 310149 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619522 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309373 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 310149 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619522 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2359626750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2381686500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741313250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5588242867 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5334624365 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10922867232 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69088500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68209750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137298250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7947869617 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7716310865 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15664180482 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7947869617 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7716310865 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15664180482 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91489795250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90582792250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072587500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13259276491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12977158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236434491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104749071741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103559950250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208309021991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027230 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024775 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024203 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048296 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046732 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12929.815885 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.909276 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12845.432194 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44044.222537 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43181.702661 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43618.712915 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11484.125665 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12261.324825 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11857.522239 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1432,68 +1433,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7647205 # DTB read hits -system.cpu1.dtb.read_misses 7298 # DTB read misses -system.cpu1.dtb.write_hits 5633094 # DTB write hits -system.cpu1.dtb.write_misses 1843 # DTB write misses -system.cpu1.dtb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7578699 # DTB read hits +system.cpu1.dtb.read_misses 7251 # DTB read misses +system.cpu1.dtb.write_hits 5604812 # DTB write hits +system.cpu1.dtb.write_misses 1846 # DTB write misses +system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6730 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6708 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7654503 # DTB read accesses -system.cpu1.dtb.write_accesses 5634937 # DTB write accesses +system.cpu1.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7585950 # DTB read accesses +system.cpu1.dtb.write_accesses 5606658 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13280299 # DTB hits -system.cpu1.dtb.misses 9141 # DTB misses -system.cpu1.dtb.accesses 13289440 # DTB accesses -system.cpu1.itb.inst_hits 31334771 # ITB inst hits -system.cpu1.itb.inst_misses 3728 # ITB inst misses +system.cpu1.dtb.hits 13183511 # DTB hits +system.cpu1.dtb.misses 9097 # DTB misses +system.cpu1.dtb.accesses 13192608 # DTB accesses +system.cpu1.itb.inst_hits 30896338 # ITB inst hits +system.cpu1.itb.inst_misses 3789 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2858 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2857 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31338499 # ITB inst accesses -system.cpu1.itb.hits 31334771 # DTB hits -system.cpu1.itb.misses 3728 # DTB misses -system.cpu1.itb.accesses 31338499 # DTB accesses -system.cpu1.numCycles 2633133982 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30900127 # ITB inst accesses +system.cpu1.itb.hits 30896338 # DTB hits +system.cpu1.itb.misses 3789 # DTB misses +system.cpu1.itb.accesses 30900127 # DTB accesses +system.cpu1.numCycles 2631198481 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30613725 # Number of instructions committed -system.cpu1.committedOps 38855266 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34913201 # Number of integer alu accesses +system.cpu1.committedInsts 30221754 # Number of instructions committed +system.cpu1.committedOps 38460770 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34602143 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses -system.cpu1.num_func_calls 1090107 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4028756 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34913201 # number of integer instructions +system.cpu1.num_func_calls 1080538 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3981203 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34602143 # number of integer instructions system.cpu1.num_fp_insts 5685 # number of float instructions -system.cpu1.num_int_register_reads 200222637 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37674133 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4268 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written -system.cpu1.num_mem_refs 13877284 # number of memory refs -system.cpu1.num_load_insts 7989860 # Number of load instructions -system.cpu1.num_store_insts 5887424 # Number of store instructions -system.cpu1.num_idle_cycles 2288817928.029144 # Number of idle cycles -system.cpu1.num_busy_cycles 344316053.970855 # Number of busy cycles -system.cpu1.not_idle_fraction 0.130763 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.869237 # Percentage of idle cycles +system.cpu1.num_int_register_reads 198301383 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37233535 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4147 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1540 # number of times the floating registers were written +system.cpu1.num_mem_refs 13778426 # number of memory refs +system.cpu1.num_load_insts 7920474 # Number of load instructions +system.cpu1.num_store_insts 5857952 # Number of store instructions +system.cpu1.num_idle_cycles 2292395060.642381 # Number of idle cycles +system.cpu1.num_busy_cycles 338803420.357619 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128764 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871236 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1510,10 +1511,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1557205456000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1557205456000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557221573750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557221573750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index c0ebf9d4a..c331380ec 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table +eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -38,6 +41,7 @@ system_port=system.membus.slave[1] [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt +eventq_index=0 oem_id= revision=2 rsdt=Null @@ -48,6 +52,7 @@ type=X86ACPIXSDT creator_id= creator_revision=0 entries= +eventq_index=0 oem_id= oem_revision=0 oem_table_id= @@ -56,6 +61,7 @@ oem_table_id= type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 @@ -66,6 +72,7 @@ slave=system.iobus.master[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 @@ -75,6 +82,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -106,6 +114,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -167,6 +177,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -175,6 +186,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -190,6 +202,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -212,18 +225,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -234,6 +250,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -256,6 +273,7 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=1024 @@ -263,15 +281,18 @@ size=1024 type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -280,16 +301,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -298,22 +322,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -322,22 +350,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -346,10 +378,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -358,124 +392,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -484,10 +539,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -496,16 +553,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -514,10 +574,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -528,6 +590,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -550,12 +613,14 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -566,16 +631,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -586,6 +654,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -608,6 +677,7 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=1024 @@ -617,6 +687,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -639,12 +710,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -654,44 +727,52 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 entries3 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +eventq_index=0 [system.e820_table.entries0] type=X86E820Entry addr=0 +eventq_index=0 range_type=1 size=654336 [system.e820_table.entries1] type=X86E820Entry addr=654336 +eventq_index=0 range_type=2 size=394240 [system.e820_table.entries2] type=X86E820Entry addr=1048576 +eventq_index=0 range_type=1 size=133169152 [system.e820_table.entries3] type=X86E820Entry addr=4294901760 +eventq_index=0 range_type=2 size=65536 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 +eventq_index=0 imcr_present=true spec_rev=4 @@ -699,6 +780,7 @@ spec_rev=4 type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +eventq_index=0 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= @@ -711,6 +793,7 @@ spec_rev=4 type=X86IntelMPProcessor bootstrap=true enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=0 @@ -722,6 +805,7 @@ stepping=0 type=X86IntelMPIOAPIC address=4273995776 enable=true +eventq_index=0 id=1 version=17 @@ -729,16 +813,19 @@ version=17 type=X86IntelMPBus bus_id=0 bus_type=ISA +eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 bus_type=PCI +eventq_index=0 [system.intel_mp_table.base_entries04] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=16 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 @@ -749,6 +836,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -759,6 +847,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=2 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -769,6 +858,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -779,6 +869,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=1 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -789,6 +880,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -799,6 +891,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=3 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -809,6 +902,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -819,6 +913,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=4 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -829,6 +924,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -839,6 +935,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=5 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -849,6 +946,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -859,6 +957,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=6 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -869,6 +968,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -879,6 +979,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=7 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -889,6 +990,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -899,6 +1001,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=8 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -909,6 +1012,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -919,6 +1023,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=9 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -929,6 +1034,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -939,6 +1045,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=10 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -949,6 +1056,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -959,6 +1067,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=11 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -969,6 +1078,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -979,6 +1089,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=12 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -989,6 +1100,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -999,6 +1111,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=13 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1009,6 +1122,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -1019,6 +1133,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=14 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1028,16 +1143,19 @@ trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 +eventq_index=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -1051,6 +1169,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1073,6 +1192,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1080,6 +1200,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1091,6 +1212,7 @@ slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side sy [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1107,13 +1229,15 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +eventq_index=0 intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -1132,6 +1256,7 @@ pio=system.iobus.master[12] type=Uart8250 children=terminal clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -1141,13 +1266,7 @@ pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.pc.com_1.terminal] -type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1156,6 +1275,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -1173,6 +1293,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -1190,6 +1311,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -1207,6 +1329,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -1224,6 +1347,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -1242,6 +1366,7 @@ pio=system.iobus.master[11] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.pc @@ -1254,6 +1379,7 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 +eventq_index=0 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -1266,6 +1392,7 @@ speaker=system.pc.south_bridge.speaker type=Cmos children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -1275,10 +1402,12 @@ pio=system.iobus.master[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.dma1] type=I8237 clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -1307,6 +1436,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1316,8 +1446,40 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=128 Revision=0 Status=640 @@ -1329,6 +1491,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=4 @@ -1345,19 +1508,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1365,102 +1531,120 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 clk_domain=system.clk_domain +eventq_index=0 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1475,6 +1659,7 @@ children=keyboard_int_pin mouse_int_pin clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 +eventq_index=0 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 @@ -1484,14 +1669,17 @@ pio=system.iobus.master[5] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic1] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1502,11 +1690,13 @@ pio=system.iobus.master[6] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic2] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1517,11 +1707,13 @@ pio=system.iobus.master[7] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pit] type=I8254 children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1530,10 +1722,12 @@ pio=system.iobus.master[8] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.speaker] type=PcSpeaker clk_domain=system.clk_domain +eventq_index=0 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1552,6 +1746,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1563,19 +1758,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable children=structures +eventq_index=0 major_version=2 minor_version=5 structures=system.smbios_table.structures @@ -1586,6 +1785,7 @@ characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 +eventq_index=0 major=0 minor=0 release_date=06/08/2008 @@ -1596,5 +1796,6 @@ version= [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 8fd17006a..f9f231b7b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133932 # Number of seconds simulated -sim_ticks 5133932129000 # Number of ticks simulated -final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133933 # Number of seconds simulated +sim_ticks 5133933067000 # Number of ticks simulated +final_tick 5133933067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157497 # Simulator instruction rate (inst/s) -host_op_rate 311329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1982921852 # Simulator tick rate (ticks/s) -host_mem_usage 759792 # Number of bytes of host memory used -host_seconds 2589.07 # Real time elapsed on the host -sim_insts 407772261 # Number of instructions simulated -sim_ops 806052921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory +host_inst_rate 121984 # Simulator instruction rate (inst/s) +host_op_rate 241126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1535878817 # Simulator tick rate (ticks/s) +host_mem_usage 781700 # Number of bytes of host memory used +host_seconds 3342.67 # Real time elapsed on the host +sim_insts 407751929 # Number of instructions simulated +sim_ops 806002693 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2437184 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory -system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory -system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1029376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10746496 # Number of bytes read from this memory +system.physmem.bytes_read::total 14217280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1029376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1029376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9492672 # Number of bytes written to this memory +system.physmem.bytes_written::total 9492672 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38081 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16084 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167914 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222145 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148323 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148323 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 474721 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2093229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2769276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1849006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1849006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1849006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 474721 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222430 # Number of read requests accepted -system.physmem.writeReqs 148587 # Number of write requests accepted -system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue -system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 200504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2093229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4618282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222145 # Number of read requests accepted +system.physmem.writeReqs 148323 # Number of write requests accepted +system.physmem.readBursts 222145 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148323 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14211648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.bytesWritten 9492416 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14217280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9492672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14853 # Per bank write bursts -system.physmem.perBankRdBursts::1 13635 # Per bank write bursts -system.physmem.perBankRdBursts::2 14415 # Per bank write bursts -system.physmem.perBankRdBursts::3 13770 # Per bank write bursts -system.physmem.perBankRdBursts::4 14136 # Per bank write bursts -system.physmem.perBankRdBursts::5 13341 # Per bank write bursts -system.physmem.perBankRdBursts::6 13755 # Per bank write bursts -system.physmem.perBankRdBursts::7 13953 # Per bank write bursts -system.physmem.perBankRdBursts::8 13590 # Per bank write bursts -system.physmem.perBankRdBursts::9 13369 # Per bank write bursts -system.physmem.perBankRdBursts::10 13469 # Per bank write bursts -system.physmem.perBankRdBursts::11 13962 # Per bank write bursts -system.physmem.perBankRdBursts::12 14252 # Per bank write bursts -system.physmem.perBankRdBursts::13 14454 # Per bank write bursts -system.physmem.perBankRdBursts::14 13844 # Per bank write bursts -system.physmem.perBankRdBursts::15 13571 # Per bank write bursts -system.physmem.perBankWrBursts::0 10225 # Per bank write bursts -system.physmem.perBankWrBursts::1 9089 # Per bank write bursts -system.physmem.perBankWrBursts::2 9605 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1715 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14970 # Per bank write bursts +system.physmem.perBankRdBursts::1 13960 # Per bank write bursts +system.physmem.perBankRdBursts::2 14769 # Per bank write bursts +system.physmem.perBankRdBursts::3 13764 # Per bank write bursts +system.physmem.perBankRdBursts::4 13644 # Per bank write bursts +system.physmem.perBankRdBursts::5 13392 # Per bank write bursts +system.physmem.perBankRdBursts::6 13407 # Per bank write bursts +system.physmem.perBankRdBursts::7 13589 # Per bank write bursts +system.physmem.perBankRdBursts::8 13408 # Per bank write bursts +system.physmem.perBankRdBursts::9 13258 # Per bank write bursts +system.physmem.perBankRdBursts::10 13821 # Per bank write bursts +system.physmem.perBankRdBursts::11 13878 # Per bank write bursts +system.physmem.perBankRdBursts::12 14332 # Per bank write bursts +system.physmem.perBankRdBursts::13 14527 # Per bank write bursts +system.physmem.perBankRdBursts::14 13749 # Per bank write bursts +system.physmem.perBankRdBursts::15 13589 # Per bank write bursts +system.physmem.perBankWrBursts::0 10370 # Per bank write bursts +system.physmem.perBankWrBursts::1 9405 # Per bank write bursts +system.physmem.perBankWrBursts::2 9871 # Per bank write bursts system.physmem.perBankWrBursts::3 9165 # Per bank write bursts -system.physmem.perBankWrBursts::4 9475 # Per bank write bursts -system.physmem.perBankWrBursts::5 8866 # Per bank write bursts -system.physmem.perBankWrBursts::6 9032 # Per bank write bursts -system.physmem.perBankWrBursts::7 9363 # Per bank write bursts -system.physmem.perBankWrBursts::8 8843 # Per bank write bursts -system.physmem.perBankWrBursts::9 8764 # Per bank write bursts -system.physmem.perBankWrBursts::10 9099 # Per bank write bursts -system.physmem.perBankWrBursts::11 9352 # Per bank write bursts -system.physmem.perBankWrBursts::12 9596 # Per bank write bursts -system.physmem.perBankWrBursts::13 9639 # Per bank write bursts -system.physmem.perBankWrBursts::14 9447 # Per bank write bursts -system.physmem.perBankWrBursts::15 9010 # Per bank write bursts +system.physmem.perBankWrBursts::4 9017 # Per bank write bursts +system.physmem.perBankWrBursts::5 8953 # Per bank write bursts +system.physmem.perBankWrBursts::6 8740 # Per bank write bursts +system.physmem.perBankWrBursts::7 8992 # Per bank write bursts +system.physmem.perBankWrBursts::8 8721 # Per bank write bursts +system.physmem.perBankWrBursts::9 8568 # Per bank write bursts +system.physmem.perBankWrBursts::10 9309 # Per bank write bursts +system.physmem.perBankWrBursts::11 9216 # Per bank write bursts +system.physmem.perBankWrBursts::12 9686 # Per bank write bursts +system.physmem.perBankWrBursts::13 9800 # Per bank write bursts +system.physmem.perBankWrBursts::14 9415 # Per bank write bursts +system.physmem.perBankWrBursts::15 9091 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 5133932076000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 5133933013500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222430 # Read request sizes (log2) +system.physmem.readPktSize::6 222145 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148587 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148323 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 174666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1072 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 555 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -139,266 +139,264 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 6022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 7022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 7020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 7083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 7644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 7121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 7236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 68754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.735608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 150.882581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1084.800437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 30893 44.93% 44.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 10573 15.38% 60.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 6859 9.98% 70.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 4406 6.41% 76.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2663 3.87% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2166 3.15% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1652 2.40% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1226 1.78% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1018 1.48% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 978 1.42% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 656 0.95% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 637 0.93% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 446 0.65% 93.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 438 0.64% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 344 0.50% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 542 0.79% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 252 0.37% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 218 0.32% 95.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 163 0.24% 96.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 136 0.20% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 158 0.23% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 420 0.61% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 150 0.22% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 127 0.18% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 107 0.16% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 87 0.13% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 64 0.09% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 17 0.02% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 43 0.06% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 19 0.03% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 31 0.05% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 40 0.06% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 10 0.01% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 16 0.02% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 31 0.05% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 10 0.01% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 13 0.02% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 31 0.05% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 4 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 6 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 27 0.04% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 9 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 12 0.02% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 28 0.04% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 7 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 25 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-system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 3 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 3 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 5 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 25 0.04% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 6 0.01% 99.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 3 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 8 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 3 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 4 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 4 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 10 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation -system.physmem.totQLat 5163279754 # Total ticks spent queuing -system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers -system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks -system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 68754 # Bytes accessed per row activation +system.physmem.totQLat 5103462500 # Total ticks spent queuing +system.physmem.totMemAccLat 9310522500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1110285000 # Total ticks spent in databus transfers +system.physmem.totBankLat 3096775000 # Total ticks spent accessing banks +system.physmem.avgQLat 22982.67 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13945.86 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41928.53 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s @@ -408,71 +406,71 @@ system.physmem.busUtil 0.04 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing -system.physmem.readRowHits 193089 # Number of row buffer hits during reads -system.physmem.writeRowHits 108689 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes -system.physmem.avgGap 13837457.79 # Average gap between requests -system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 8.57 # Average write queue length when enqueuing +system.physmem.readRowHits 193293 # Number of row buffer hits during reads +system.physmem.writeRowHits 108329 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes +system.physmem.avgGap 13857966.18 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 5101771 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662370 # Transaction distribution -system.membus.trans_dist::ReadResp 662362 # Transaction distribution -system.membus.trans_dist::WriteReq 13778 # Transaction distribution -system.membus.trans_dist::WriteResp 13778 # Transaction distribution -system.membus.trans_dist::Writeback 148587 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution -system.membus.trans_dist::ReadExReq 179504 # Transaction distribution -system.membus.trans_dist::ReadExResp 179502 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 8 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25543633 # Total data (bytes) -system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks) +system.membus.throughput 5095991 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662317 # Transaction distribution +system.membus.trans_dist::ReadResp 662311 # Transaction distribution +system.membus.trans_dist::WriteReq 13762 # Transaction distribution +system.membus.trans_dist::WriteResp 13762 # Transaction distribution +system.membus.trans_dist::Writeback 148323 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2201 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1734 # Transaction distribution +system.membus.trans_dist::ReadExReq 179351 # Transaction distribution +system.membus.trans_dist::ReadExResp 179346 # Transaction distribution +system.membus.trans_dist::MessageReq 1642 # Transaction distribution +system.membus.trans_dist::MessageResp 1642 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 474374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720496 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1856159 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18286080 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20078023 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5423872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5423872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25508463 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25508463 # Total data (bytes) +system.membus.snoop_data_through_bus 654016 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250556000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583258500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1605908499 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3150989153 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429464748 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47576 # number of replacements -system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.103980 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 4992951939000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103980 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses @@ -483,14 +481,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47631 system.iocache.demand_misses::total 47631 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151022435 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151022435 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11480088301 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11480088301 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11631110736 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11631110736 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11631110736 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11631110736 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -507,19 +505,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165776.547750 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165776.547750 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245721.068086 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 245721.068086 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 244192.033256 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 244192.033256 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 172788 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10383 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.641433 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -533,14 +531,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 103624935 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 103624935 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9049102305 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9049102305 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9152727240 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9152727240 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -549,18 +547,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113748.556531 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 113748.556531 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193687.977419 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 193687.977419 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -570,16 +568,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 638153 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225567 # Transaction distribution -system.iobus.trans_dist::ReadResp 225567 # Transaction distribution -system.iobus.trans_dist::WriteReq 57606 # Transaction distribution -system.iobus.trans_dist::WriteResp 57606 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.throughput 638147 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225559 # Transaction distribution +system.iobus.trans_dist::ReadResp 225559 # Transaction distribution +system.iobus.trans_dist::WriteReq 57591 # Transaction distribution +system.iobus.trans_dist::WriteResp 57591 # Transaction distribution +system.iobus.trans_dist::MessageReq 1642 # Transaction distribution +system.iobus.trans_dist::MessageResp 1642 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -595,15 +593,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569584 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -619,20 +617,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276232 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276202 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276202 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3916600 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -662,153 +660,153 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424364988 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53080252 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85592238 # Number of BP lookups -system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits +system.cpu.branchPred.lookups 85602749 # Number of BP lookups +system.cpu.branchPred.condPredicted 85602749 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 882967 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79146839 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77528417 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions. -system.cpu.numCycles 453841851 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.955165 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1444593 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180696 # Number of incorrect RAS predictions. +system.cpu.numCycles 453810576 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25587128 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422793434 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85602749 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78973010 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162653475 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3995125 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 108453 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71359520 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87857 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8489508 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 384110 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2391 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262908725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.175877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411274 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100670178 38.29% 38.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1530444 0.58% 38.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71820335 27.32% 66.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 896426 0.34% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1566584 0.60% 67.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2396730 0.91% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1019321 0.39% 68.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1330214 0.51% 68.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81678493 31.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262908725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188631 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931652 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29469022 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68533895 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158500921 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3336716 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3068171 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832628882 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3068171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32166033 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43333689 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12473461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158788115 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13079256 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829706187 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21464 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6056720 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5143219 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991368832 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800529447 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1106981108 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 114 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963921381 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27447449 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 454679 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29562257 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16738170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9831898 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1099509 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 931888 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824922108 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1185282 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820965230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 150616 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19266581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29327510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 130776 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262908725 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.122625 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.401229 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76541753 29.11% 29.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15760378 5.99% 35.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10546081 4.01% 39.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7369618 2.80% 41.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75729447 28.80% 70.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3748882 1.43% 72.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72293205 27.50% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 772480 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 146881 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262908725 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 349560 33.18% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1967 0.19% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548780 52.08% 85.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153094 14.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 307236 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793474466 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149866 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124488 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -835,283 +833,283 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17682042 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9227132 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued -system.cpu.iq.rate 1.808871 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820965230 # Type of FU issued +system.cpu.iq.rate 1.809048 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1053642 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001283 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906151693 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845384400 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817050943 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 198 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821711543 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694469 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2748093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19141 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11819 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1409863 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931395 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11998 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3068171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31463417 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2151711 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826107390 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 248376 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16738170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9831898 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 690155 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620159 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12279 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11819 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498534 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508074 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1006608 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819554351 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17378079 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1410878 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed -system.cpu.iew.exec_branches 83090404 # Number of branches executed -system.cpu.iew.exec_stores 9036920 # Number of stores executed -system.cpu.iew.exec_rate 1.805776 # Inst execution rate -system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638560375 # num instructions producing a value -system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value +system.cpu.iew.exec_refs 26421028 # number of memory reference insts executed +system.cpu.iew.exec_branches 83090233 # Number of branches executed +system.cpu.iew.exec_stores 9042949 # Number of stores executed +system.cpu.iew.exec_rate 1.805939 # Inst execution rate +system.cpu.iew.wb_sent 819150966 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817050997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638575855 # num instructions producing a value +system.cpu.iew.wb_consumers 1043882621 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800423 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611731 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19994665 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054506 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892807 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259840554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.101913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863847 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88304488 33.98% 33.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11858711 4.56% 38.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3833949 1.48% 40.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74748511 28.77% 68.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2384583 0.92% 69.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1475819 0.57% 70.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 859128 0.33% 70.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70844564 27.26% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5530801 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407772261 # Number of instructions committed -system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259840554 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407751929 # Number of instructions committed +system.cpu.commit.committedOps 806002693 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22412414 # Number of memory references committed -system.cpu.commit.loads 13990896 # Number of loads committed -system.cpu.commit.membars 474709 # Number of memory barriers committed -system.cpu.commit.branches 82160310 # Number of branches committed +system.cpu.commit.refs 22412111 # Number of memory references committed +system.cpu.commit.loads 13990076 # Number of loads committed +system.cpu.commit.membars 474663 # Number of memory barriers committed +system.cpu.commit.branches 82157264 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734896243 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155289 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734852381 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155163 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5530801 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080212949 # The number of ROB reads -system.cpu.rob.rob_writes 1654925831 # The number of ROB writes -system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407772261 # Number of Instructions Simulated -system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated -system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads -system.cpu.int_regfile_writes 653799671 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads -system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes -system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads -system.cpu.misc_regfile_writes 402440 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1080228878 # The number of ROB reads +system.cpu.rob.rob_writes 1655077473 # The number of ROB writes +system.cpu.timesIdled 1260592 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190901851 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9814061063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407751929 # Number of Instructions Simulated +system.cpu.committedOps 806002693 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407751929 # Number of Instructions Simulated +system.cpu.cpi 1.112958 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112958 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898507 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898507 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088763208 # number of integer regfile reads +system.cpu.int_regfile_writes 653821136 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.cc_regfile_reads 415622850 # number of cc regfile reads +system.cpu.cc_regfile_writes 321492626 # number of cc regfile writes +system.cpu.misc_regfile_reads 264082516 # number of misc regfile reads +system.cpu.misc_regfile_writes 402300 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53661983 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3016761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3016231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1581663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288041 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916491 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19443 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154439 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8213573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61324288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207594695 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 616960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5463872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 274999815 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274973191 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 523840 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4039348922 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 624000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1440815600 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3139539816 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 14707994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 103656142 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 959142 # number of replacements -system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 957724 # number of replacements +system.cpu.icache.tags.tagsinuse 509.254964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7477774 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 958236 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.803687 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits -system.cpu.icache.overall_hits::total 7468451 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses -system.cpu.icache.overall_misses::total 1013022 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 509.254964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994639 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994639 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7477774 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7477774 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7477774 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7477774 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7477774 # number of overall hits +system.cpu.icache.overall_hits::total 7477774 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1011731 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1011731 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1011731 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1011731 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1011731 # number of overall misses +system.cpu.icache.overall_misses::total 1011731 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14180716030 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14180716030 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14180716030 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14180716030 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14180716030 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14180716030 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8489505 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8489505 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8489505 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8489505 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8489505 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8489505 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119174 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.119174 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.119174 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.119174 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.119174 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.119174 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.290921 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14016.290921 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14016.290921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14016.290921 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5333 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.827027 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53298 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53298 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53298 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53298 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53298 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53298 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959724 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 959724 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 959724 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 959724 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 959724 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 959724 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11694537694 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11694537694 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11694537694 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11694537694 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11694537694 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11694537694 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113155 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for 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rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112880 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12202.638365 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12202.638365 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8004 # number of 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ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20417 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 20417 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20417 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 20417 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9803 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9803 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9803 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9803 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9803 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9803 # number of overall misses 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system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30787 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30787 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30787 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30787 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.288907 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.288907 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.288888 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.288888 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.288888 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.288888 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11450.696762 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11450.696762 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11450.696762 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30220 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30220 # number of demand (read+write) accesses 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average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11138.044170 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11138.044170 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1120,78 +1118,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast 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-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 84047009 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 84047009 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 84047009 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 84047009 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 84047009 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.288907 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.288907 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency 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rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.324388 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9137.331327 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 68011 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 14.842846 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 91726 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 68027 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.348376 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.842846 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.927678 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.927678 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91726 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 91726 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91726 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 91726 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91726 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 91726 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69066 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 69066 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69066 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 69066 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69066 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 69066 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 860977213 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 860977213 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 860977213 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 860977213 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 860977213 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 860977213 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160792 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 160792 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160792 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 160792 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160792 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 160792 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429536 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429536 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429536 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429536 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429536 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429536 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12466.006617 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12466.006617 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12466.006617 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1200,146 +1198,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 21216 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21216 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69066 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69066 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69066 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 69066 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69066 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 69066 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 722730929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 722730929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 722730929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 722730929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 722730929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 722730929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429536 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429536 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429536 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10464.351910 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1657437 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.988912 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18989388 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1657949 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.453542 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1656829 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997280 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18997986 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657341 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.462931 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.988912 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999978 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999978 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10890920 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10890920 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8095777 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8095777 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18986697 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18986697 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18986697 # number of overall hits -system.cpu.dcache.overall_hits::total 18986697 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2234479 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2234479 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316198 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316198 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2550677 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2550677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2550677 # number of overall misses -system.cpu.dcache.overall_misses::total 2550677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33004921637 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33004921637 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12257889032 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12257889032 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45262810669 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45262810669 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45262810669 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45262810669 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13125399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13125399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8411975 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8411975 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21537374 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21537374 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21537374 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21537374 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170241 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170241 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037589 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037589 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118430 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118430 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118430 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118430 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14770.745949 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14770.745949 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38766.497676 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38766.497676 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17745.410598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17745.410598 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 397669 # number of cycles access was blocked +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997280 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10898836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10898836 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8096443 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8096443 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18995279 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18995279 # number of demand (read+write) hits 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number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42042 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42262 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.458851 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.364465 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558744 # number of writebacks -system.cpu.dcache.writebacks::total 1558744 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864490 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 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overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29198836917 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364613500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364613500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538583500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538583500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903197000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903197000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate 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accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66856.655436 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69205.271768 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68485.890487 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.383721 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.383721 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.769844 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.769844 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16084 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168869 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185019 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5166251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 312500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1091253760 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2471371556 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3568104067 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15558435 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15558435 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7786682845 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7786682845 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5166251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1091253760 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10258054401 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11354786912 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5166251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1091253760 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10258054401 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11354786912 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250274500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250274500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370476500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370476500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620751000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620751000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026273 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.819617 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.819617 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461479 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461479 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068862 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068862 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67847.162397 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68719.838612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68468.598373 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10700.436726 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10700.436726 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58587.895543 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58587.895543 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 404746deb..4079b1ad3 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table +eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -38,6 +41,7 @@ system_port=system.membus.slave[1] [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt +eventq_index=0 oem_id= revision=2 rsdt=Null @@ -48,6 +52,7 @@ type=X86ACPIXSDT creator_id= creator_revision=0 entries= +eventq_index=0 oem_id= oem_revision=0 oem_table_id= @@ -56,6 +61,7 @@ oem_table_id= type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 @@ -66,6 +72,7 @@ slave=system.iobus.master[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 @@ -75,6 +82,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -87,6 +95,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -118,6 +127,7 @@ icache_port=system.cpu0.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu0.dcache] type=BaseCache @@ -125,6 +135,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -147,18 +158,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.toL2Bus.slave[3] @@ -169,6 +183,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -191,12 +206,14 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=X86LocalApic clk_domain=system.cpu0.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -207,22 +224,26 @@ pio=system.membus.master[1] [system.cpu0.isa] type=X86ISA +eventq_index=0 [system.cpu0.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -234,6 +255,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -255,32 +277,38 @@ workload= [system.cpu1.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system [system.cpu1.isa] type=X86ISA +eventq_index=0 [system.cpu1.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -311,6 +339,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -373,6 +403,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -385,12 +416,14 @@ predType=tournament [system.cpu2.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu2.dtb.walker [system.cpu2.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system @@ -398,15 +431,18 @@ system=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -415,16 +451,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -433,22 +472,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -457,22 +500,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -481,10 +528,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -493,124 +542,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -619,10 +689,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -631,16 +703,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -649,69 +724,82 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu2.isa] type=X86ISA +eventq_index=0 [system.cpu2.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu2.itb.walker [system.cpu2.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 entries3 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +eventq_index=0 [system.e820_table.entries0] type=X86E820Entry addr=0 +eventq_index=0 range_type=1 size=654336 [system.e820_table.entries1] type=X86E820Entry addr=654336 +eventq_index=0 range_type=2 size=394240 [system.e820_table.entries2] type=X86E820Entry addr=1048576 +eventq_index=0 range_type=1 size=133169152 [system.e820_table.entries3] type=X86E820Entry addr=4294901760 +eventq_index=0 range_type=2 size=65536 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 +eventq_index=0 imcr_present=true spec_rev=4 @@ -719,6 +807,7 @@ spec_rev=4 type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +eventq_index=0 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= @@ -731,6 +820,7 @@ spec_rev=4 type=X86IntelMPProcessor bootstrap=true enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=0 @@ -742,6 +832,7 @@ stepping=0 type=X86IntelMPIOAPIC address=4273995776 enable=true +eventq_index=0 id=1 version=17 @@ -749,16 +840,19 @@ version=17 type=X86IntelMPBus bus_id=0 bus_type=ISA +eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 bus_type=PCI +eventq_index=0 [system.intel_mp_table.base_entries04] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=16 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 @@ -769,6 +863,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -779,6 +874,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=2 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -789,6 +885,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -799,6 +896,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=1 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -809,6 +907,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -819,6 +918,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=3 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -829,6 +929,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -839,6 +940,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=4 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -849,6 +951,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -859,6 +962,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=5 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -869,6 +973,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -879,6 +984,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=6 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -889,6 +995,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -899,6 +1006,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=7 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -909,6 +1017,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -919,6 +1028,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=8 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -929,6 +1039,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -939,6 +1050,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=9 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -949,6 +1061,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -959,6 +1072,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=10 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -969,6 +1083,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -979,6 +1094,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=11 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -989,6 +1105,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -999,6 +1116,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=12 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1009,6 +1127,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -1019,6 +1138,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=13 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1029,6 +1149,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -1039,6 +1160,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=14 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1048,16 +1170,19 @@ trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 +eventq_index=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -1071,6 +1196,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1093,6 +1219,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1102,6 +1229,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1124,6 +1252,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1131,6 +1260,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1142,6 +1272,7 @@ slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1158,13 +1289,15 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +eventq_index=0 intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -1183,6 +1316,7 @@ pio=system.iobus.master[12] type=Uart8250 children=terminal clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -1192,13 +1326,7 @@ pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.pc.com_1.terminal] -type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1207,6 +1335,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -1224,6 +1353,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -1241,6 +1371,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -1258,6 +1389,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -1275,6 +1407,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -1293,6 +1426,7 @@ pio=system.iobus.master[11] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.pc @@ -1305,6 +1439,7 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 +eventq_index=0 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -1317,6 +1452,7 @@ speaker=system.pc.south_bridge.speaker type=Cmos children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -1326,10 +1462,12 @@ pio=system.iobus.master[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.dma1] type=I8237 clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -1358,6 +1496,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1367,8 +1506,40 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=128 Revision=0 Status=640 @@ -1380,6 +1551,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=4 @@ -1396,19 +1568,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1416,102 +1591,120 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 clk_domain=system.clk_domain +eventq_index=0 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1526,6 +1719,7 @@ children=keyboard_int_pin mouse_int_pin clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 +eventq_index=0 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 @@ -1535,14 +1729,17 @@ pio=system.iobus.master[5] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic1] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1553,11 +1750,13 @@ pio=system.iobus.master[6] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic2] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1568,11 +1767,13 @@ pio=system.iobus.master[7] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pit] type=I8254 children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1581,10 +1782,12 @@ pio=system.iobus.master[8] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.speaker] type=PcSpeaker clk_domain=system.clk_domain +eventq_index=0 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1603,6 +1806,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1614,19 +1818,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable children=structures +eventq_index=0 major_version=2 minor_version=5 structures=system.smbios_table.structures @@ -1637,6 +1845,7 @@ characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 +eventq_index=0 major=0 minor=0 release_date=06/08/2008 @@ -1648,6 +1857,7 @@ version= [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1657,5 +1867,6 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index e884e1c2d..2b6efde37 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137942 # Number of seconds simulated -sim_ticks 5137941673500 # Number of ticks simulated -final_tick 5137941673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137456 # Number of seconds simulated +sim_ticks 5137456264000 # Number of ticks simulated +final_tick 5137456264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248874 # Simulator instruction rate (inst/s) -host_op_rate 494699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5246911955 # Simulator tick rate (ticks/s) -host_mem_usage 994832 # Number of bytes of host memory used -host_seconds 979.23 # Real time elapsed on the host -sim_insts 243705182 # Number of instructions simulated -sim_ops 484425104 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2466368 # Number of bytes read from this memory +host_inst_rate 176189 # Simulator instruction rate (inst/s) +host_op_rate 350219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3709429360 # Simulator tick rate (ticks/s) +host_mem_usage 1030148 # Number of bytes of host memory used +host_seconds 1384.97 # Real time elapsed on the host +sim_insts 244016231 # Number of instructions simulated +sim_ops 485043652 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2422400 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 426944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5894144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1789248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 385728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2633280 # Number of bytes read from this memory -system.physmem.bytes_read::total 13744640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 426944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 385728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 959872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9091584 # Number of bytes written to this memory -system.physmem.bytes_written::total 9091584 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38537 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 383808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5693376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 137536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1729152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 448384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2947264 # Number of bytes read from this memory +system.physmem.bytes_read::total 13764480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 383808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 137536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 448384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9086592 # Number of bytes written to this memory +system.physmem.bytes_written::total 9086592 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37850 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6671 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 92096 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 27957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6027 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41145 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214760 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142056 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142056 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 480030 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 5997 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 88959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 27018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 46051 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141978 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141978 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 471517 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 83096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1147180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 28650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 348242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 75074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 512517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2675126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 83096 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 28650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 75074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 186820 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1769499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1769499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1769499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 480030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1108209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 336577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 87277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 573682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2679240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 87277 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1768695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1768695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1768695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 471517 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 83096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1147180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 28650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 75074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 512517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4444625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 100936 # Number of read requests accepted -system.physmem.writeReqs 78380 # Number of write requests accepted -system.physmem.readBursts 100936 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 78380 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6458816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue -system.physmem.bytesWritten 5015040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6459904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5016320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 74708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1108209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 336577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 87277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 573682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4447935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 102292 # Number of read requests accepted +system.physmem.writeReqs 78374 # Number of write requests accepted +system.physmem.readBursts 102292 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 78374 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6544384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2304 # Total number of bytes read from write queue +system.physmem.bytesWritten 5015936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6546688 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5015936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 699 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5898 # Per bank write bursts -system.physmem.perBankRdBursts::1 6403 # Per bank write bursts -system.physmem.perBankRdBursts::2 6411 # Per bank write bursts -system.physmem.perBankRdBursts::3 6523 # Per bank write bursts -system.physmem.perBankRdBursts::4 6306 # Per bank write bursts -system.physmem.perBankRdBursts::5 6840 # Per bank write bursts -system.physmem.perBankRdBursts::6 6199 # Per bank write bursts -system.physmem.perBankRdBursts::7 6896 # Per bank write bursts -system.physmem.perBankRdBursts::8 5528 # Per bank write bursts -system.physmem.perBankRdBursts::9 5898 # Per bank write bursts -system.physmem.perBankRdBursts::10 6128 # Per bank write bursts -system.physmem.perBankRdBursts::11 6570 # Per bank write bursts -system.physmem.perBankRdBursts::12 6317 # Per bank write bursts -system.physmem.perBankRdBursts::13 6334 # Per bank write bursts -system.physmem.perBankRdBursts::14 6542 # Per bank write bursts -system.physmem.perBankRdBursts::15 6126 # Per bank write bursts -system.physmem.perBankWrBursts::0 4721 # Per bank write bursts -system.physmem.perBankWrBursts::1 4902 # Per bank write bursts -system.physmem.perBankWrBursts::2 4923 # Per bank write bursts -system.physmem.perBankWrBursts::3 5159 # Per bank write bursts -system.physmem.perBankWrBursts::4 5192 # Per bank write bursts -system.physmem.perBankWrBursts::5 5457 # Per bank write bursts -system.physmem.perBankWrBursts::6 4843 # Per bank write bursts -system.physmem.perBankWrBursts::7 5797 # Per bank write bursts -system.physmem.perBankWrBursts::8 4085 # Per bank write bursts -system.physmem.perBankWrBursts::9 4367 # Per bank write bursts -system.physmem.perBankWrBursts::10 4807 # Per bank write bursts -system.physmem.perBankWrBursts::11 4903 # Per bank write bursts -system.physmem.perBankWrBursts::12 4884 # Per bank write bursts -system.physmem.perBankWrBursts::13 4699 # Per bank write bursts -system.physmem.perBankWrBursts::14 5116 # Per bank write bursts -system.physmem.perBankWrBursts::15 4505 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 862 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6805 # Per bank write bursts +system.physmem.perBankRdBursts::1 7244 # Per bank write bursts +system.physmem.perBankRdBursts::2 6375 # Per bank write bursts +system.physmem.perBankRdBursts::3 6857 # Per bank write bursts +system.physmem.perBankRdBursts::4 6927 # Per bank write bursts +system.physmem.perBankRdBursts::5 6780 # Per bank write bursts +system.physmem.perBankRdBursts::6 5925 # Per bank write bursts +system.physmem.perBankRdBursts::7 6310 # Per bank write bursts +system.physmem.perBankRdBursts::8 5868 # Per bank write bursts +system.physmem.perBankRdBursts::9 5795 # Per bank write bursts +system.physmem.perBankRdBursts::10 5783 # Per bank write bursts +system.physmem.perBankRdBursts::11 6231 # Per bank write bursts +system.physmem.perBankRdBursts::12 6160 # Per bank write bursts +system.physmem.perBankRdBursts::13 6316 # Per bank write bursts +system.physmem.perBankRdBursts::14 6211 # Per bank write bursts +system.physmem.perBankRdBursts::15 6669 # Per bank write bursts +system.physmem.perBankWrBursts::0 5462 # Per bank write bursts +system.physmem.perBankWrBursts::1 5811 # Per bank write bursts +system.physmem.perBankWrBursts::2 4880 # Per bank write bursts +system.physmem.perBankWrBursts::3 5445 # Per bank write bursts +system.physmem.perBankWrBursts::4 5542 # Per bank write bursts +system.physmem.perBankWrBursts::5 5461 # Per bank write bursts +system.physmem.perBankWrBursts::6 4520 # Per bank write bursts +system.physmem.perBankWrBursts::7 4685 # Per bank write bursts +system.physmem.perBankWrBursts::8 4152 # Per bank write bursts +system.physmem.perBankWrBursts::9 4422 # Per bank write bursts +system.physmem.perBankWrBursts::10 4208 # Per bank write bursts +system.physmem.perBankWrBursts::11 4507 # Per bank write bursts +system.physmem.perBankWrBursts::12 4889 # Per bank write bursts +system.physmem.perBankWrBursts::13 4664 # Per bank write bursts +system.physmem.perBankWrBursts::14 4834 # Per bank write bursts +system.physmem.perBankWrBursts::15 4892 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 5136941479000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5136272146500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 100936 # Read request sizes (log2) +system.physmem.readPktSize::6 102292 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 78380 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 75816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 78374 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -163,226 +163,227 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.217991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.094116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1121.662575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16547 46.47% 46.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5535 15.54% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3551 9.97% 71.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2213 6.22% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1334 3.75% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1101 3.09% 85.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 807 2.27% 87.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 584 1.64% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 515 1.45% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 517 1.45% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 309 0.87% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 309 0.87% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 205 0.58% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 200 0.56% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 177 0.50% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 272 0.76% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 139 0.39% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 84 0.24% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 95 0.27% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 94 0.26% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 81 0.23% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 178 0.50% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 83 0.23% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 58 0.16% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 45 0.13% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 38 0.11% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 29 0.08% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 19 0.05% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 15 0.04% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 14 0.04% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 11 0.03% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 8 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 6 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 8 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 5 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 8 0.02% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 3 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 5 0.01% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 6 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 6 0.02% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 4 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 3 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 3 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 20 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.41% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::12608-12611 2 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 3 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 12 0.03% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 6 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 10 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 3 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 5 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 9 0.03% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 8 0.02% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 29 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35607 # Bytes accessed per row activation -system.physmem.totQLat 2741683498 # Total ticks spent queuing -system.physmem.totMemAccLat 4643457248 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 504595000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1397178750 # Total ticks spent accessing banks -system.physmem.avgQLat 27167.17 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13844.56 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 37207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.623700 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.064630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1005.971949 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16908 45.44% 45.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5765 15.49% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3845 10.33% 71.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2398 6.45% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1477 3.97% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1206 3.24% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 882 2.37% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 634 1.70% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 564 1.52% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 479 1.29% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 331 0.89% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 285 0.77% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 209 0.56% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 204 0.55% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 197 0.53% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 303 0.81% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 153 0.41% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 117 0.31% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 75 0.20% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 61 0.16% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 106 0.28% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 199 0.53% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 97 0.26% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.23% 98.32% # Bytes accessed per row activation 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0.02% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 13 0.03% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 4 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 4 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.15% # Bytes accessed per row activation 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0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 2 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.41% # Bytes accessed per row activation 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0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 5 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 2 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 2 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 4 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.02% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 3 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 11 0.03% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 14 0.04% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 22 0.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37207 # Bytes accessed per row activation +system.physmem.totQLat 2596442750 # Total ticks spent queuing +system.physmem.totMemAccLat 4566061500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 511280000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1458338750 # Total ticks spent accessing banks +system.physmem.avgQLat 25391.59 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14261.64 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46011.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44653.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -390,322 +391,318 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.11 # Average write queue length when enqueuing -system.physmem.readRowHits 85240 # Number of row buffer hits during reads -system.physmem.writeRowHits 58432 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes -system.physmem.avgGap 28647423.98 # Average gap between requests -system.physmem.pageHitRate 80.13 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6427951 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 423177 # Transaction distribution -system.membus.trans_dist::ReadResp 423176 # Transaction distribution -system.membus.trans_dist::WriteReq 6474 # Transaction distribution -system.membus.trans_dist::WriteResp 6474 # Transaction distribution -system.membus.trans_dist::Writeback 78380 # Transaction distribution -system.membus.trans_dist::UpgradeReq 714 # Transaction distribution -system.membus.trans_dist::UpgradeResp 714 # Transaction distribution -system.membus.trans_dist::ReadExReq 80216 # Transaction distribution -system.membus.trans_dist::ReadExResp 80216 # Transaction distribution -system.membus.trans_dist::MessageReq 892 # Transaction distribution -system.membus.trans_dist::MessageResp 892 # Transaction distribution -system.membus.trans_dist::BadAddressError 1 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 310648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497624 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 207711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1015985 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 78748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 78748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1096517 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159467 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995245 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8228608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9383320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 3247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12634504 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32719620 # Total data (bytes) -system.membus.snoop_data_through_bus 306816 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 163512000 # Layer occupancy (ticks) +system.physmem.readRowHits 86197 # Number of row buffer hits during reads +system.physmem.writeRowHits 57226 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes +system.physmem.avgGap 28429655.53 # Average gap between requests +system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.13 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6440814 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 424797 # Transaction distribution +system.membus.trans_dist::ReadResp 424797 # Transaction distribution +system.membus.trans_dist::WriteReq 7056 # Transaction distribution +system.membus.trans_dist::WriteResp 7056 # Transaction distribution +system.membus.trans_dist::Writeback 78374 # Transaction distribution +system.membus.trans_dist::UpgradeReq 877 # Transaction distribution +system.membus.trans_dist::UpgradeResp 877 # Transaction distribution +system.membus.trans_dist::ReadExReq 80570 # Transaction distribution +system.membus.trans_dist::ReadExResp 80570 # Transaction distribution +system.membus.trans_dist::MessageReq 957 # Transaction distribution +system.membus.trans_dist::MessageResp 957 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 221000 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1030868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 68894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1101676 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160435 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995417 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8741760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9897612 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2820864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2820864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12722304 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32756791 # Total data (bytes) +system.membus.snoop_data_through_bus 332608 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 164980499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315210000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315323500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1784000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1914000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 830204748 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 859913497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 892000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1595294481 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1658568572 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 252511249 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 223775499 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 103855 # number of replacements -system.l2c.tags.tagsinuse 64822.347448 # Cycle average of tags in use -system.l2c.tags.total_refs 3646219 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167877 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.719586 # Average number of references to valid blocks. +system.l2c.tags.replacements 103968 # number of replacements +system.l2c.tags.tagsinuse 64819.095791 # Cycle average of tags in use +system.l2c.tags.total_refs 3669692 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168243 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.811855 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51292.264352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121895 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1278.615227 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4499.945934 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 292.458405 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1505.357985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.212632 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1370.507166 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4576.860668 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.782658 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51211.809516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121912 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1304.363790 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4492.907273 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 251.742289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1518.622796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.780510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.958868 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1352.233300 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4674.555536 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.781430 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019510 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068664 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004463 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020912 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.069837 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989111 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 19693 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10326 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 346717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 513928 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10907 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 155624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 223811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 47020 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 9087 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 331652 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 566093 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2240790 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.019903 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.068556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003841 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000180 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 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ReadReq mshr uncacheable latency @@ -849,39 +846,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.094274 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.092731 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000200819009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094274 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005892 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5000213887009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092731 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005796 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005796 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129801048 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129801048 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6845673540 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6845673540 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6975474588 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6975474588 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6975474588 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6975474588 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135882017 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 135882017 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5955673280 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5955673280 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6091555297 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6091555297 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6091555297 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6091555297 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -890,56 +887,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142638.514286 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142638.514286 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 146525.546661 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 146525.546661 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 146451.282553 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 146451.282553 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 105453 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 149485.167217 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 149485.167217 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 127475.883562 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 127475.883562 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127895.930987 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127895.930987 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 91729 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6453 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5124 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.341702 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 17.901835 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 724 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 27280 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 27280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 28004 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 28004 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 28004 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 28004 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92126548 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 92126548 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 5426189542 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5426189542 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5518316090 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5518316090 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.795604 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.795604 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.583904 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.583904 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.587949 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.587949 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127246.613260 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127246.613260 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 198907.241276 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 198907.241276 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 754 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 754 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24064 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 24064 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 24818 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 24818 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 24818 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 24818 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96648017 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96648017 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4703544282 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4703544282 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4800192299 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4800192299 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.829483 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.829483 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.515068 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.515068 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.521069 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.521069 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 128180.393899 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128180.393899 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195459.785655 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 195459.785655 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -953,459 +950,458 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52188015 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1787129 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1786595 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6474 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6474 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 905502 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 665 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 665 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 176137 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 148862 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 991248 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3625702 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34347 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 125379 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4776676 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31718784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120252184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 463592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152554720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268001344 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 137632 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5049278590 # Layer occupancy (ticks) +system.toL2Bus.throughput 52370833 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1836862 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1836332 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 7056 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 7056 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 922959 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 811 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 811 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 181042 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 156978 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1050040 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3684115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 38115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 140219 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4912489 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 33600320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 122621708 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 135720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 527336 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 156885084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268925359 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 127504 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5157428290 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 882000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1008000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2232669307 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2365130940 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4714355905 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4803653283 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19343965 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 21171206 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 67521559 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 74417261 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1276093 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 150466 # Transaction distribution -system.iobus.trans_dist::ReadResp 150466 # Transaction distribution -system.iobus.trans_dist::WriteReq 32862 # Transaction distribution -system.iobus.trans_dist::WriteResp 32862 # Transaction distribution -system.iobus.trans_dist::MessageReq 892 # Transaction distribution -system.iobus.trans_dist::MessageResp 892 # Transaction distribution +system.iobus.throughput 1276721 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 150736 # Transaction distribution +system.iobus.trans_dist::ReadResp 150736 # Transaction distribution +system.iobus.trans_dist::WriteReq 30161 # Transaction distribution +system.iobus.trans_dist::WriteResp 30161 # Transaction distribution +system.iobus.trans_dist::MessageReq 957 # Transaction distribution +system.iobus.trans_dist::MessageResp 957 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4556 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 500 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 580 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15082 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 310648 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 56008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 56008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1784 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1784 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 368440 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 312158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49636 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49636 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 363708 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3380 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 17 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143595 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1000 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1160 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7541 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 159467 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1782176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1782176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1945211 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6556491 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2113460 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 160435 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1576592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1576592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1740855 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6559098 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2255722 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3772000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4948000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143596000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143539000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 394000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 458000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11170000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11248000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 248070339 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 218954798 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 305066000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306061000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 32957751 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 29747501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 892000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 957000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1184263733 # number of cpu cycles simulated +system.cpu0.numCycles 1152461068 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72124506 # Number of instructions committed -system.cpu0.committedOps 146682326 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134713165 # Number of integer alu accesses +system.cpu0.committedInsts 71542662 # Number of instructions committed +system.cpu0.committedOps 145644721 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 133686522 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 981373 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14229217 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134713165 # number of integer instructions +system.cpu0.num_func_calls 963574 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14130614 # number of instructions that are conditional controls +system.cpu0.num_int_insts 133686522 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 247622256 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115606613 # number of times the integer registers were written +system.cpu0.num_int_register_reads 245609809 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114802156 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83816060 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55907358 # number of times the CC registers were written -system.cpu0.num_mem_refs 14049102 # number of memory refs -system.cpu0.num_load_insts 10253492 # Number of load instructions -system.cpu0.num_store_insts 3795610 # Number of store instructions -system.cpu0.num_idle_cycles 1123870108.492543 # Number of idle cycles -system.cpu0.num_busy_cycles 60393624.507457 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050997 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949003 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 83145706 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55494396 # number of times the CC registers were written +system.cpu0.num_mem_refs 13834339 # number of memory refs +system.cpu0.num_load_insts 10142209 # Number of load instructions +system.cpu0.num_store_insts 3692130 # Number of store instructions +system.cpu0.num_idle_cycles 1095316733.110107 # Number of idle cycles +system.cpu0.num_busy_cycles 57144334.889893 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049585 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950415 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 848510 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.789516 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129618382 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 849022 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 152.667872 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147463418500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 302.993641 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 130.368033 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 77.427843 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.591784 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.254625 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.151226 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997636 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 87771297 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39145197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2701888 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129618382 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87771297 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39145197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2701888 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129618382 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87771297 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39145197 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2701888 # number of overall hits -system.cpu0.icache.overall_hits::total 129618382 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 353389 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 157925 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 356099 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 867413 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 353389 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 157925 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 356099 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 867413 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 353389 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 157925 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 356099 # number of overall misses -system.cpu0.icache.overall_misses::total 867413 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2216316250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5093590204 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7309906454 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2216316250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5093590204 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7309906454 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2216316250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5093590204 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7309906454 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 88124686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39303122 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3057987 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130485795 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 88124686 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39303122 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3057987 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130485795 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 88124686 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39303122 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3057987 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130485795 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004010 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004018 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116449 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006648 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004010 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004018 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116449 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006648 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004010 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004018 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116449 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006648 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14033.979737 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14303.859893 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8427.250288 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8427.250288 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8427.250288 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4049 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 857108 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.816977 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128607019 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 857620 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 149.958046 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147466681500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 303.791229 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 134.865519 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 72.160229 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.593342 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.263409 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.140938 # Average percentage of cache occupancy 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375629 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 375629 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17363 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17363 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 392992 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 392992 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 392992 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 392992 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 227972 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 589816 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 817788 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 58525 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99219 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 157744 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 286497 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 689035 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 975532 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 286497 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 689035 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 975532 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2789367492 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8524003053 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11313370545 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2071430220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3281431451 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5352861671 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4860797712 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11805434504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16666232216 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4860797712 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11805434504 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16666232216 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30612926500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33246502500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63859429000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 519657500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 815190500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1334848000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31132584000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34061693000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65194277000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.084932 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.117207 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061741 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034718 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032833 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018787 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.045076 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045076 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12235.570561 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14451.969857 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13834.111707 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35393.937975 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33072.611607 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33933.852768 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1416,306 +1412,306 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606010326 # number of cpu cycles simulated +system.cpu1.numCycles 2606011326 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35502902 # Number of instructions committed -system.cpu1.committedOps 69019443 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64128875 # Number of integer alu accesses +system.cpu1.committedInsts 35164948 # Number of instructions committed +system.cpu1.committedOps 68413270 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63529188 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 466888 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6511590 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64128875 # number of integer instructions +system.cpu1.num_func_calls 457891 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6471423 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63529188 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 118555351 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55341107 # number of times the integer registers were written +system.cpu1.num_int_register_reads 117257194 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54850904 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36337345 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27074895 # number of times the CC registers were written -system.cpu1.num_mem_refs 4724906 # number of memory refs -system.cpu1.num_load_insts 2973846 # Number of load instructions -system.cpu1.num_store_insts 1751060 # Number of store instructions -system.cpu1.num_idle_cycles 2477242501.972853 # Number of idle cycles -system.cpu1.num_busy_cycles 128767824.027147 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049412 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950588 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 36014934 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26882843 # number of times the CC registers were written +system.cpu1.num_mem_refs 4560424 # number of memory refs +system.cpu1.num_load_insts 2872895 # Number of load instructions +system.cpu1.num_store_insts 1687529 # Number of store instructions +system.cpu1.num_idle_cycles 2475874291.383945 # Number of idle cycles +system.cpu1.num_busy_cycles 130137034.616055 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049937 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950063 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28668505 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28668505 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 293936 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26313496 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25716329 # Number of BTB hits +system.cpu2.branchPred.lookups 29049356 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29049356 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 330189 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26516680 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25920061 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.730568 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 531231 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 59742 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154176343 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.750024 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 553809 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 66194 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157465018 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9183670 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141279801 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28668505 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26247560 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54165747 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1372429 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 60595 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24017130 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 2633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7414 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 19025 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3057990 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 134510 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1720 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 88520588 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.147296 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.411069 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10014190 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 143120520 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29049356 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26473870 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54776048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1540394 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 78659 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 25463388 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 3574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6100 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 25165 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 454 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3264432 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 152504 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2125 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 91560833 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.080398 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.405930 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 34483261 38.96% 38.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 569039 0.64% 39.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23712203 26.79% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 303942 0.34% 66.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 596203 0.67% 67.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 791828 0.89% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 321684 0.36% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 518300 0.59% 69.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27224128 30.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 36927513 40.33% 40.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 611138 0.67% 41.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23812381 26.01% 67.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 328703 0.36% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 619714 0.68% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 832275 0.91% 68.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 355282 0.39% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 540716 0.59% 69.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27533111 30.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 88520588 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185946 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.916352 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10629848 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 22917593 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 30946726 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1286674 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1067388 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 277843876 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 5 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1067388 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11607450 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13707721 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4125990 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 31086433 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5253313 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 276918591 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6816 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2458805 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2129053 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 330941436 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 602250525 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 370032440 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321416172 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9525262 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 139074 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 139963 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11350220 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6069912 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3334552 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 325084 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 284462 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275324678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 401766 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273874447 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 58026 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6719880 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10332541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 51920 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 88520588 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.093907 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.392477 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 91560833 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184481 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.908904 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 11521398 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 24357574 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 32837645 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1316376 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1196608 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 281192085 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 11 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1196608 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12539536 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14626708 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4503596 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 32964525 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5398696 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280154725 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 7234 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2491982 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2219031 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 334708153 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 610319016 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 374834819 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 324049688 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10658465 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 153621 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 154561 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11685330 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6409686 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3556417 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 350066 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 288206 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 278401976 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 420214 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 276663998 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 65469 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7519016 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11586940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 57670 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 91560833 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.021641 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.405034 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 25429283 28.73% 28.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6033030 6.82% 35.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3870306 4.37% 39.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2690716 3.04% 42.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25010151 28.25% 71.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1323131 1.49% 72.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23827077 26.92% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 285216 0.32% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 51678 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 27548029 30.09% 30.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6302445 6.88% 36.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 4040687 4.41% 41.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2809709 3.07% 44.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25166051 27.49% 71.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1389542 1.52% 73.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23947180 26.15% 99.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 301462 0.33% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 55728 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 88520588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 91560833 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 120453 33.21% 33.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 124 0.03% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 190037 52.39% 85.63% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 52134 14.37% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 136321 35.17% 35.17% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 124 0.03% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 194124 50.09% 85.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 56993 14.71% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 69880 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264196051 96.47% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 53857 0.02% 96.51% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 45427 0.02% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6378380 2.33% 98.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3130852 1.14% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 81905 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 266468718 96.31% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56660 0.02% 96.37% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48242 0.02% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6674536 2.41% 98.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3333937 1.21% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273874447 # Type of FU issued -system.cpu2.iq.rate 1.776371 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 362748 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001325 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 636728050 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 282449613 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272560977 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 75 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 276663998 # Type of FU issued +system.cpu2.iq.rate 1.756987 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387562 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 645385259 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 286345237 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 275267423 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 106 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274167280 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 35 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 638144 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 276969613 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 42 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 657734 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 933920 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 7005 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3826 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 481474 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1052819 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4672 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 529632 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656274 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10618 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656268 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10631 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9024497 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 812904 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275726444 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 67814 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6069912 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3334552 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 224273 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 631637 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3885 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3826 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 167894 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164610 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 332504 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273407129 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6276348 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 467317 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1196608 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9811775 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 820688 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 278822190 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 75669 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6409704 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3556417 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 239796 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 634227 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4101 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4672 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 184871 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 190702 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 375573 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 276137017 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6556879 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 526981 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9343774 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27815177 # Number of branches executed -system.cpu2.iew.exec_stores 3067426 # Number of stores executed -system.cpu2.iew.exec_rate 1.773340 # Inst execution rate -system.cpu2.iew.wb_sent 273265355 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272560999 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212629872 # num instructions producing a value -system.cpu2.iew.wb_consumers 347702126 # num instructions consuming a value +system.cpu2.iew.exec_refs 9821909 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28090459 # Number of branches executed +system.cpu2.iew.exec_stores 3265030 # Number of stores executed +system.cpu2.iew.exec_rate 1.753640 # Inst execution rate +system.cpu2.iew.wb_sent 275979435 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 275267445 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 214496489 # num instructions producing a value +system.cpu2.iew.wb_consumers 350700107 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.767852 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611529 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.748118 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611624 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7002811 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 349846 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 295934 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 87453200 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.072767 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.870996 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7834345 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 362544 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 332977 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 90364225 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 2.998816 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.871519 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30168588 34.50% 34.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4310788 4.93% 39.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1198483 1.37% 40.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24616834 28.15% 68.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 847666 0.97% 69.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 576601 0.66% 70.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 339942 0.39% 70.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23302626 26.65% 97.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2091672 2.39% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 32381210 35.83% 35.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4545159 5.03% 40.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1281676 1.42% 42.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24783522 27.43% 69.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 890698 0.99% 70.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 597656 0.66% 71.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 358639 0.40% 71.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23381642 25.87% 97.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2144023 2.37% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 87453200 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136077774 # Number of instructions committed -system.cpu2.commit.committedOps 268723335 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 90364225 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137308621 # Number of instructions committed +system.cpu2.commit.committedOps 270985661 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7989069 # Number of memory references committed -system.cpu2.commit.loads 5135991 # Number of loads committed -system.cpu2.commit.membars 163538 # Number of memory barriers committed -system.cpu2.commit.branches 27499066 # Number of branches committed +system.cpu2.commit.refs 8383670 # Number of memory references committed +system.cpu2.commit.loads 5356885 # Number of loads committed +system.cpu2.commit.membars 165489 # Number of memory barriers committed +system.cpu2.commit.branches 27738642 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245318960 # Number of committed integer instructions. -system.cpu2.commit.function_calls 428759 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2091672 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 247503684 # Number of committed integer instructions. +system.cpu2.commit.function_calls 442390 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2144023 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 361063162 # The number of ROB reads -system.cpu2.rob.rob_writes 552523197 # The number of ROB writes -system.cpu2.timesIdled 466136 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65655755 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4909695924 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136077774 # Number of Instructions Simulated -system.cpu2.committedOps 268723335 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136077774 # Number of Instructions Simulated -system.cpu2.cpi 1.133002 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.133002 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882611 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882611 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 363659019 # number of integer regfile reads -system.cpu2.int_regfile_writes 218348978 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads +system.cpu2.rob.rob_reads 367011505 # The number of ROB reads +system.cpu2.rob.rob_writes 558841004 # The number of ROB writes +system.cpu2.timesIdled 481956 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65904185 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4905068069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137308621 # Number of Instructions Simulated +system.cpu2.committedOps 270985661 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 137308621 # Number of Instructions Simulated +system.cpu2.cpi 1.146796 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.146796 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.871994 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.871994 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 367544012 # number of integer regfile reads +system.cpu2.int_regfile_writes 220503659 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72990 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138971726 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107072573 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88484504 # number of misc regfile reads -system.cpu2.misc_regfile_writes 124462 # number of misc regfile writes +system.cpu2.cc_regfile_reads 140406201 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108013944 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89640596 # number of misc regfile reads +system.cpu2.misc_regfile_writes 136839 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |