diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref')
12 files changed, 15237 insertions, 14614 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index bc7291548..9c4d04cdf 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.905240 # Number of seconds simulated -sim_ticks 1905239522500 # Number of ticks simulated -final_tick 1905239522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.905651 # Number of seconds simulated +sim_ticks 1905651402000 # Number of ticks simulated +final_tick 1905651402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125426 # Simulator instruction rate (inst/s) -host_op_rate 125426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4213194084 # Simulator tick rate (ticks/s) -host_mem_usage 351852 # Number of bytes of host memory used -host_seconds 452.21 # Real time elapsed on the host -sim_insts 56718526 # Number of instructions simulated -sim_ops 56718526 # Number of ops (including micro ops) simulated +host_inst_rate 124387 # Simulator instruction rate (inst/s) +host_op_rate 124387 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4179760275 # Simulator tick rate (ticks/s) +host_mem_usage 352908 # Number of bytes of host memory used +host_seconds 455.92 # Real time elapsed on the host +sim_insts 56710998 # Number of instructions simulated +sim_ops 56710998 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 764480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24384256 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 214080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 925440 # Number of bytes read from this memory -system.physmem.bytes_read::total 28937600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 764480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 214080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7885248 # Number of bytes written to this memory -system.physmem.bytes_written::total 7885248 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 381004 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14460 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452150 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123207 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123207 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 401251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12798525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1390557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 112364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 485734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15188432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 401251 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 112364 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4138717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4138717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4138717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 401251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12798525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1390557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 112364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 485734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19327149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 452150 # Number of read requests accepted -system.physmem.writeReqs 123207 # Number of write requests accepted -system.physmem.readBursts 452150 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123207 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28929984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 7883136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28937600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7885248 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 897600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24800576 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 431296 # Number of bytes read from this memory +system.physmem.bytes_read::total 28857792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 897600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7816896 # Number of bytes written to this memory +system.physmem.bytes_written::total 7816896 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14025 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387509 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6739 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450903 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122139 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122139 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 471020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13014225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1390391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 226325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15143269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 471020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41309 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4101955 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4101955 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4101955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 471020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13014225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1390391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 226325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19245224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450903 # Number of read requests accepted +system.physmem.writeReqs 122139 # Number of write requests accepted +system.physmem.readBursts 450903 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122139 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28848704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue +system.physmem.bytesWritten 7815360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28857792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7816896 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 5017 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28700 # Per bank write bursts -system.physmem.perBankRdBursts::1 28863 # Per bank write bursts -system.physmem.perBankRdBursts::2 29008 # Per bank write bursts -system.physmem.perBankRdBursts::3 28541 # Per bank write bursts -system.physmem.perBankRdBursts::4 28135 # Per bank write bursts -system.physmem.perBankRdBursts::5 28059 # Per bank write bursts -system.physmem.perBankRdBursts::6 27918 # Per bank write bursts -system.physmem.perBankRdBursts::7 27861 # Per bank write bursts -system.physmem.perBankRdBursts::8 27885 # Per bank write bursts -system.physmem.perBankRdBursts::9 28003 # Per bank write bursts -system.physmem.perBankRdBursts::10 27955 # Per bank write bursts -system.physmem.perBankRdBursts::11 28030 # Per bank write bursts -system.physmem.perBankRdBursts::12 28165 # Per bank write bursts -system.physmem.perBankRdBursts::13 28514 # Per bank write bursts -system.physmem.perBankRdBursts::14 28239 # Per bank write bursts -system.physmem.perBankRdBursts::15 28155 # Per bank write bursts -system.physmem.perBankWrBursts::0 8383 # Per bank write bursts -system.physmem.perBankWrBursts::1 8222 # Per bank write bursts -system.physmem.perBankWrBursts::2 8291 # Per bank write bursts -system.physmem.perBankWrBursts::3 7900 # Per bank write bursts -system.physmem.perBankWrBursts::4 7506 # Per bank write bursts -system.physmem.perBankWrBursts::5 7518 # Per bank write bursts -system.physmem.perBankWrBursts::6 7426 # Per bank write bursts -system.physmem.perBankWrBursts::7 7231 # Per bank write bursts -system.physmem.perBankWrBursts::8 7193 # Per bank write bursts -system.physmem.perBankWrBursts::9 7295 # Per bank write bursts -system.physmem.perBankWrBursts::10 7315 # Per bank write bursts -system.physmem.perBankWrBursts::11 7381 # Per bank write bursts -system.physmem.perBankWrBursts::12 7680 # Per bank write bursts -system.physmem.perBankWrBursts::13 8142 # Per bank write bursts -system.physmem.perBankWrBursts::14 8013 # Per bank write bursts -system.physmem.perBankWrBursts::15 7678 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4858 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28020 # Per bank write bursts +system.physmem.perBankRdBursts::1 28240 # Per bank write bursts +system.physmem.perBankRdBursts::2 28746 # Per bank write bursts +system.physmem.perBankRdBursts::3 28309 # Per bank write bursts +system.physmem.perBankRdBursts::4 27973 # Per bank write bursts +system.physmem.perBankRdBursts::5 28180 # Per bank write bursts +system.physmem.perBankRdBursts::6 28116 # Per bank write bursts +system.physmem.perBankRdBursts::7 27456 # Per bank write bursts +system.physmem.perBankRdBursts::8 27700 # Per bank write bursts +system.physmem.perBankRdBursts::9 28070 # Per bank write bursts +system.physmem.perBankRdBursts::10 27744 # Per bank write bursts +system.physmem.perBankRdBursts::11 28151 # Per bank write bursts +system.physmem.perBankRdBursts::12 28476 # Per bank write bursts +system.physmem.perBankRdBursts::13 28764 # Per bank write bursts +system.physmem.perBankRdBursts::14 28477 # Per bank write bursts +system.physmem.perBankRdBursts::15 28339 # Per bank write bursts +system.physmem.perBankWrBursts::0 7807 # Per bank write bursts +system.physmem.perBankWrBursts::1 7750 # Per bank write bursts +system.physmem.perBankWrBursts::2 8222 # Per bank write bursts +system.physmem.perBankWrBursts::3 7743 # Per bank write bursts +system.physmem.perBankWrBursts::4 7390 # Per bank write bursts +system.physmem.perBankWrBursts::5 7636 # Per bank write bursts +system.physmem.perBankWrBursts::6 7609 # Per bank write bursts +system.physmem.perBankWrBursts::7 6913 # Per bank write bursts +system.physmem.perBankWrBursts::8 6944 # Per bank write bursts +system.physmem.perBankWrBursts::9 7275 # Per bank write bursts +system.physmem.perBankWrBursts::10 7157 # Per bank write bursts +system.physmem.perBankWrBursts::11 7547 # Per bank write bursts +system.physmem.perBankWrBursts::12 7916 # Per bank write bursts +system.physmem.perBankWrBursts::13 8234 # Per bank write bursts +system.physmem.perBankWrBursts::14 8082 # Per bank write bursts +system.physmem.perBankWrBursts::15 7890 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 1905235063000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1905651381000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 452150 # Read request sizes (log2) +system.physmem.readPktSize::6 450903 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123207 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 319865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3977 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122139 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 319686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 41704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -158,360 +158,358 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 51367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 630.908404 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 404.510586 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 424.248985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 9707 18.90% 18.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6974 13.58% 32.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3124 6.08% 38.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1892 3.68% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1518 2.96% 45.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 943 1.84% 47.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 823 1.60% 48.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 886 1.72% 50.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25500 49.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 51367 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7232 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 62.502074 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2469.163441 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 7229 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 550.416718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 337.147598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 420.487836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14710 22.08% 22.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11156 16.75% 38.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5022 7.54% 46.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2851 4.28% 50.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2435 3.66% 54.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1624 2.44% 56.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1521 2.28% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1728 2.59% 61.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25564 38.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66611 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7169 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 62.875994 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2479.971838 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 7166 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7232 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.031803 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.787924 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.763450 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6148 85.01% 85.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.48% 85.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 69 0.95% 86.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 422 5.84% 92.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 144 1.99% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 50 0.69% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 33 0.46% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 29 0.40% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 50 0.69% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 33 0.46% 96.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 22 0.30% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 30 0.41% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 23 0.32% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 33 0.46% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.04% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.14% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 7 0.10% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 5 0.07% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.03% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 3 0.04% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 4 0.06% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 6 0.08% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 7 0.10% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 5 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 2 0.03% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 2 0.03% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 9 0.12% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 8 0.11% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 6 0.08% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 4 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 3 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 4 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7232 # Writes before turning the bus around for reads -system.physmem.totQLat 10473139750 # Total ticks spent queuing -system.physmem.totMemAccLat 18209837250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2260155000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5476542500 # Total ticks spent accessing banks -system.physmem.avgQLat 23169.07 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 12115.41 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 7169 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7169 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.033756 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.809188 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.694603 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5699 79.50% 79.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 43 0.60% 80.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 713 9.95% 90.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 256 3.57% 93.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 102 1.42% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 22 0.31% 95.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 28 0.39% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 86 1.20% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 18 0.25% 97.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 42 0.59% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 15 0.21% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 21 0.29% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 11 0.15% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 10 0.14% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.04% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 26 0.36% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.03% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.03% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.01% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.01% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.06% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.04% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 6 0.08% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 3 0.04% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 5 0.07% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 11 0.15% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 5 0.07% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 4 0.06% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 7 0.10% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 11 0.15% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7169 # Writes before turning the bus around for reads +system.physmem.totQLat 8930594750 # Total ticks spent queuing +system.physmem.totMemAccLat 17382363500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2253805000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19812.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40284.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38562.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.83 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.68 # Average write queue length when enqueuing -system.physmem.readRowHits 407908 # Number of row buffer hits during reads -system.physmem.writeRowHits 99848 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.04 # Row buffer hit rate for writes -system.physmem.avgGap 3311396.34 # Average gap between requests -system.physmem.pageHitRate 88.27 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19386335 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296672 # Transaction distribution -system.membus.trans_dist::ReadResp 296448 # Transaction distribution -system.membus.trans_dist::WriteReq 13044 # Transaction distribution -system.membus.trans_dist::WriteResp 13044 # Transaction distribution -system.membus.trans_dist::Writeback 123207 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9628 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5545 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5017 # Transaction distribution -system.membus.trans_dist::ReadExReq 163957 # Transaction distribution -system.membus.trans_dist::ReadExResp 163513 # Transaction distribution -system.membus.trans_dist::BadAddressError 224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40492 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 924104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 448 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 965044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124646 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124646 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1089690 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73787 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31516032 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31589819 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306816 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36896635 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36896635 # Total data (bytes) -system.membus.snoop_data_through_bus 38976 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 37949499 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.90 # Average write queue length when enqueuing +system.physmem.readRowHits 407659 # Number of row buffer hits during reads +system.physmem.writeRowHits 98604 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes +system.physmem.avgGap 3325500.37 # Average gap between requests +system.physmem.pageHitRate 88.37 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1804524317000 # Time in different power states +system.physmem.memoryStateTime::REF 63633700000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 37488657000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 19303809 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296468 # Transaction distribution +system.membus.trans_dist::ReadResp 296393 # Transaction distribution +system.membus.trans_dist::WriteReq 13039 # Transaction distribution +system.membus.trans_dist::WriteResp 13039 # Transaction distribution +system.membus.trans_dist::Writeback 122139 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9699 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5540 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4861 # Transaction distribution +system.membus.trans_dist::ReadExReq 162690 # Transaction distribution +system.membus.trans_dist::ReadExResp 162297 # Transaction distribution +system.membus.trans_dist::BadAddressError 75 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920381 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 960997 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1085644 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73690 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31367808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31441498 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36748378 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36748378 # Total data (bytes) +system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 37884500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1621348498 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1609423248 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 283500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 94500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3837196476 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3824980631 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376708248 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376652994 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 345233 # number of replacements -system.l2c.tags.tagsinuse 65245.285653 # Cycle average of tags in use -system.l2c.tags.total_refs 2551644 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410415 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.217229 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7106352750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53519.548176 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4149.494238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5612.081999 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1358.843164 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 605.318076 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816643 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.085634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.020734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009236 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995564 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2472 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5440 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5794 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51245 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994598 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26808140 # Number of tag accesses -system.l2c.tags.data_accesses 26808140 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 890534 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 623023 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 181208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 171976 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1866741 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 807199 # number of Writeback hits -system.l2c.Writeback_hits::total 807199 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 179 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 196 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 375 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 42 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 156975 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 15152 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172127 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 890534 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 779998 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 181208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 187128 # number of demand (read+write) hits -system.l2c.demand_hits::total 2038868 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 890534 # number of overall hits -system.l2c.overall_hits::cpu0.data 779998 # number of overall hits -system.l2c.overall_hits::cpu1.inst 181208 # number of overall hits -system.l2c.overall_hits::cpu1.data 187128 # number of overall hits -system.l2c.overall_hits::total 2038868 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11953 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272223 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3356 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1782 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289314 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3186 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 726 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3912 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 379 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 428 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 807 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109189 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13070 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122259 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11953 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 381412 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3356 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 14852 # number of demand (read+write) misses -system.l2c.demand_misses::total 411573 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11953 # number of overall misses -system.l2c.overall_misses::cpu0.data 381412 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3356 # number of overall misses -system.l2c.overall_misses::cpu1.data 14852 # number of overall misses -system.l2c.overall_misses::total 411573 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 917004250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17843471250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 269423486 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 137552496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19167451482 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1326945 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 933461 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2260406 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 265489 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2039412 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2304901 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9056624622 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1307071580 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10363696202 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 917004250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26900095872 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 269423486 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1444624076 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29531147684 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 917004250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26900095872 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 269423486 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1444624076 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29531147684 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 902487 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 895246 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 184564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 173758 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2156055 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 807199 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 807199 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3365 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 922 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4287 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 421 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.tags.replacements 343977 # number of replacements +system.l2c.tags.tagsinuse 65252.773158 # Cycle average of tags in use +system.l2c.tags.total_refs 2582565 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 408968 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.314834 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7103141750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53523.190376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5304.878115 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6147.677864 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 207.477812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 69.548991 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.816699 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080946 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.093806 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995678 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64991 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3387 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4556 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4338 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52483 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991684 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27108862 # Number of tag accesses +system.l2c.tags.data_accesses 27108862 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 867616 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 736617 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 210128 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 67910 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1882271 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 822208 # number of Writeback hits +system.l2c.Writeback_hits::total 822208 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 261 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 430 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 154436 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 25581 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180017 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 867616 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 891053 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 210128 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 93491 # number of demand (read+write) hits +system.l2c.demand_hits::total 2062288 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 867616 # number of overall hits +system.l2c.overall_hits::cpu0.data 891053 # number of overall hits +system.l2c.overall_hits::cpu1.inst 210128 # number of overall hits +system.l2c.overall_hits::cpu1.data 93491 # number of overall hits +system.l2c.overall_hits::total 2062288 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 14035 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273392 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1238 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 452 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2673 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1056 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3729 # 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number of overall misses +system.l2c.overall_misses::cpu1.inst 1238 # number of overall misses +system.l2c.overall_misses::cpu1.data 6794 # number of overall misses +system.l2c.overall_misses::total 410154 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1067454245 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17881620237 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 96862500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 35356999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 19081293981 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 964468 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 4567794 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 5532262 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 972461 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114995 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1087456 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9393947733 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 639497214 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10033444947 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1067454245 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 27275567970 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 96862500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 674854213 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 29114738928 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1067454245 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 27275567970 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 96862500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 674854213 # number of overall miss cycles +system.l2c.overall_miss_latency::total 29114738928 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 881651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1010009 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 211366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 68362 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2171388 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 822208 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 822208 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2842 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1317 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4159 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 455 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 458 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 879 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 266164 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28222 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 294386 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 902487 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1161410 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 184564 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 201980 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2450441 # 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Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.475429 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029714 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029714 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712295759000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.491978 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030749 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030749 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -671,14 +669,14 @@ system.iocache.demand_misses::tsunami.ide 41727 # n system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21363133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21363133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 13166015946 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 13166015946 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13187379079 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13187379079 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13187379079 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13187379079 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21492883 # 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number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses @@ -721,14 +719,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41727 system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12262133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12262133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11002982450 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 11002982450 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 11015244583 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 11015244583 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 11015244583 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 11015244583 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12390883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12390883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10336377204 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10336377204 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10348768087 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10348768087 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10348768087 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10348768087 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -737,14 +735,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70069.331429 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70069.331429 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264800.309251 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 264800.309251 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263983.621708 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 263983.621708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263983.621708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 263983.621708 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -758,35 +756,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12197818 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10301308 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 323625 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8091894 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5160475 # Number of BTB hits +system.cpu0.branchPred.lookups 12477942 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10513633 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 331474 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8127728 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5283638 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 63.773389 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 773216 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29770 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.007564 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 797741 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28790 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8724392 # DTB read hits -system.cpu0.dtb.read_misses 30821 # DTB read misses -system.cpu0.dtb.read_acv 561 # DTB read access violations -system.cpu0.dtb.read_accesses 667825 # DTB read accesses -system.cpu0.dtb.write_hits 5867379 # DTB write hits -system.cpu0.dtb.write_misses 8333 # DTB write misses -system.cpu0.dtb.write_acv 362 # DTB write access violations -system.cpu0.dtb.write_accesses 233878 # DTB write accesses -system.cpu0.dtb.data_hits 14591771 # DTB hits -system.cpu0.dtb.data_misses 39154 # DTB misses -system.cpu0.dtb.data_acv 923 # DTB access violations -system.cpu0.dtb.data_accesses 901703 # DTB accesses -system.cpu0.itb.fetch_hits 1047253 # ITB hits -system.cpu0.itb.fetch_misses 31067 # ITB misses -system.cpu0.itb.fetch_acv 998 # ITB acv -system.cpu0.itb.fetch_accesses 1078320 # ITB accesses +system.cpu0.dtb.read_hits 8879185 # DTB read hits +system.cpu0.dtb.read_misses 30734 # DTB read misses +system.cpu0.dtb.read_acv 556 # DTB read access violations +system.cpu0.dtb.read_accesses 627584 # DTB read accesses +system.cpu0.dtb.write_hits 5815647 # DTB write hits +system.cpu0.dtb.write_misses 8173 # DTB write misses +system.cpu0.dtb.write_acv 357 # DTB write access violations +system.cpu0.dtb.write_accesses 210225 # DTB write accesses +system.cpu0.dtb.data_hits 14694832 # DTB hits +system.cpu0.dtb.data_misses 38907 # DTB misses +system.cpu0.dtb.data_acv 913 # DTB access violations +system.cpu0.dtb.data_accesses 837809 # DTB accesses +system.cpu0.itb.fetch_hits 998260 # ITB hits +system.cpu0.itb.fetch_misses 27519 # ITB misses +system.cpu0.itb.fetch_acv 894 # ITB acv +system.cpu0.itb.fetch_accesses 1025779 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -799,269 +797,304 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112262549 # number of cpu cycles simulated +system.cpu0.numCycles 116074371 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25337690 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 62232975 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12197818 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5933691 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11660813 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1669062 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34963299 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31852 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 204835 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 245581 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7519019 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 220862 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 73507816 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.846617 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.186991 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25123779 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63882467 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12477942 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6081379 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12010156 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1699076 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37307525 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 195411 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 352959 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7722540 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223615 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 76113904 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.839301 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.177052 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 61847003 84.14% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 769960 1.05% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1463561 1.99% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676221 0.92% 88.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2490968 3.39% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 505392 0.69% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 543861 0.74% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 933568 1.27% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4277282 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64103748 84.22% 84.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 767865 1.01% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1567652 2.06% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 704812 0.93% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2586726 3.40% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 521075 0.68% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 575522 0.76% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 832581 1.09% 94.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4453923 5.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 73507816 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.108654 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.554352 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26369028 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34601594 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10599753 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 908827 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1028613 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 489342 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35202 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61098455 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 108348 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1028613 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27370799 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12650473 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18559497 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9975684 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3922748 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 57686354 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6807 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 465136 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1446625 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 38461887 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 70023385 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 69867874 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 145011 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33864047 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4597832 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1504040 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 221397 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10820518 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9135753 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6149920 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1079808 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 706714 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 51077926 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1853906 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 49994907 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 110749 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5661802 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2962344 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1252355 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 73507816 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.680130 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328001 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 76113904 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.107500 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.550358 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26378411 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36826325 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10921760 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 930988 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1056419 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 512680 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35852 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62713959 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 107463 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1056419 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27400432 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14971568 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18343259 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10229394 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4112830 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59339079 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7155 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 639099 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1437135 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39727133 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72236857 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72098194 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 129082 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34929896 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4797229 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1458801 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 212309 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11241570 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9288070 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6084553 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1139915 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 737819 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52640864 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1816659 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51478960 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92665 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5869250 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3045578 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1230018 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 76113904 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.676341 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.327493 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 51188064 69.64% 69.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10233888 13.92% 83.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4604901 6.26% 89.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2962380 4.03% 93.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2331848 3.17% 97.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1189595 1.62% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 642601 0.87% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 303208 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 51331 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53257398 69.97% 69.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10376788 13.63% 83.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4704231 6.18% 89.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3091331 4.06% 93.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2445214 3.21% 97.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1217468 1.60% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 651050 0.86% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 318171 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52253 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 73507816 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 76113904 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 67972 10.01% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 320913 47.27% 57.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 290070 42.72% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 82049 12.02% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 319124 46.77% 58.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 281213 41.21% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34052559 68.11% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 53588 0.11% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 16727 0.03% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.26% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9088781 18.18% 86.44% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5934753 11.87% 98.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 842846 1.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35464091 68.89% 68.90% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56550 0.11% 69.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15746 0.03% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9235082 17.94% 86.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5882526 11.43% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 819301 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 49994907 # Type of FU issued -system.cpu0.iq.rate 0.445339 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 678955 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013580 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 173664474 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 58303886 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48932524 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 622859 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 301167 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 293964 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 50344041 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326051 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 531595 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51478960 # Type of FU issued +system.cpu0.iq.rate 0.443500 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 682386 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013256 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 179291609 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60070073 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50439032 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 555265 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 269219 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 261959 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51867113 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 290448 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 544569 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1104780 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2697 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 11676 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 443054 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1116578 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3845 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12782 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 445374 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13921 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 147330 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18457 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 142389 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1028613 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8821962 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 743484 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 56052726 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 628552 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9135753 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6149920 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1633160 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 601804 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5465 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 11676 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 157790 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 354691 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 512481 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49615767 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8780349 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 379139 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1056419 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10732956 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 797506 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57687159 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 618379 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9288070 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6084553 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1600267 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 582946 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5458 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12782 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164537 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 351989 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 516526 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51092894 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8933351 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 386065 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3120894 # number of nop insts executed -system.cpu0.iew.exec_refs 14670742 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7826693 # Number of branches executed -system.cpu0.iew.exec_stores 5890393 # Number of stores executed -system.cpu0.iew.exec_rate 0.441962 # Inst execution rate -system.cpu0.iew.wb_sent 49317778 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 49226488 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24274382 # num instructions producing a value -system.cpu0.iew.wb_consumers 32670143 # num instructions consuming a value +system.cpu0.iew.exec_nop 3229636 # number of nop insts executed +system.cpu0.iew.exec_refs 14770817 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8136394 # Number of branches executed +system.cpu0.iew.exec_stores 5837466 # Number of stores executed +system.cpu0.iew.exec_rate 0.440174 # Inst execution rate +system.cpu0.iew.wb_sent 50791046 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50700991 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25278333 # num instructions producing a value +system.cpu0.iew.wb_consumers 34060542 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.438494 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.743014 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.436797 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742159 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6126865 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 601551 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 478401 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 72479203 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.687487 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.606917 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6334928 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 586641 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 480870 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75057485 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.682787 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.597640 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 53761554 74.18% 74.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7891628 10.89% 85.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4152119 5.73% 90.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2321486 3.20% 93.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1304265 1.80% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 530677 0.73% 96.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 447192 0.62% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 447640 0.62% 97.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1622642 2.24% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55774455 74.31% 74.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8026658 10.69% 85.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4417430 5.89% 90.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2392691 3.19% 94.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1323184 1.76% 95.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 562724 0.75% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 473653 0.63% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 433129 0.58% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1653561 2.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 72479203 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49828537 # Number of instructions committed -system.cpu0.commit.committedOps 49828537 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75057485 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51248256 # Number of instructions committed +system.cpu0.commit.committedOps 51248256 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13737839 # Number of memory references committed -system.cpu0.commit.loads 8030973 # Number of loads committed -system.cpu0.commit.membars 204358 # Number of memory barriers committed -system.cpu0.commit.branches 7461649 # Number of branches committed -system.cpu0.commit.fp_insts 291974 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46136165 # Number of committed integer instructions. -system.cpu0.commit.function_calls 636945 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1622642 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13810671 # Number of memory references committed +system.cpu0.commit.loads 8171492 # Number of loads committed +system.cpu0.commit.membars 199624 # Number of memory barriers committed +system.cpu0.commit.branches 7741114 # Number of branches committed +system.cpu0.commit.fp_insts 259898 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47457125 # Number of committed integer instructions. +system.cpu0.commit.function_calls 657479 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2951389 5.76% 5.76% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33388118 65.15% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55525 0.11% 71.02% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.02% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 15746 0.03% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1879 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8371116 16.33% 87.39% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5645183 11.02% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 819300 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 51248256 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1653561 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 126610557 # The number of ROB reads -system.cpu0.rob.rob_writes 112939421 # The number of ROB writes -system.cpu0.timesIdled 1039659 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38754733 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698211471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46979170 # Number of Instructions Simulated -system.cpu0.committedOps 46979170 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 46979170 # Number of Instructions Simulated -system.cpu0.cpi 2.389624 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.389624 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.418476 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.418476 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65113755 # number of integer regfile reads -system.cpu0.int_regfile_writes 35503571 # number of integer regfile writes -system.cpu0.fp_regfile_reads 144629 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146446 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1885764 # number of misc regfile reads -system.cpu0.misc_regfile_writes 851290 # number of misc regfile writes +system.cpu0.rob.rob_reads 130790454 # The number of ROB reads +system.cpu0.rob.rob_writes 116222813 # The number of ROB writes +system.cpu0.timesIdled 1101169 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 39960467 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3695221845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48300626 # Number of Instructions Simulated +system.cpu0.committedOps 48300626 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 48300626 # Number of Instructions Simulated +system.cpu0.cpi 2.403165 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.403165 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.416118 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.416118 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67219449 # number of integer regfile reads +system.cpu0.int_regfile_writes 36695614 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128632 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130173 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1801385 # number of misc regfile reads +system.cpu0.misc_regfile_writes 820377 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1093,83 +1126,83 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110236199 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2184890 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2184651 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13044 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13044 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 807199 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9705 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5617 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15322 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 337408 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295861 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1805066 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3017885 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 369158 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 600045 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5792154 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57759168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 115626954 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 11812096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23360753 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 208558971 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 208548411 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1477952 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4893610631 # Layer occupancy (ticks) +system.toL2Bus.throughput 111416521 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2199115 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2199023 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13039 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13039 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 822208 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9837 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5613 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15450 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 343877 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302328 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1763397 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369225 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 422759 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 294489 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5849870 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56425664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130205428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13527424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10778278 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 210936794 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 210926490 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1394560 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4971595549 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4065813860 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3972568555 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5358512161 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5889953047 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 831641640 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 951834487 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 971081953 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1435731 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 54596 # Transaction distribution -system.iobus.trans_dist::WriteResp 54596 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11886 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 507907991 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 1435370 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 54591 # Transaction distribution +system.iobus.trans_dist::WriteResp 54591 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11870 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40466 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123946 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47544 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123920 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 73787 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 73690 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2735411 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2735411 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11236000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2735314 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2735314 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11225000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1181,7 +1214,7 @@ system.iobus.reqLayer23.occupancy 13505000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1189,267 +1222,268 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 379995831 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380163081 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27448000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27427000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43184752 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43193006 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 901902 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.676111 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6573395 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 902414 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.284234 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26905725250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.676111 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995461 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995461 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8421597 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8421597 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6573395 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6573395 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6573395 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6573395 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6573395 # number of overall hits -system.cpu0.icache.overall_hits::total 6573395 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945623 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945623 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945623 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945623 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945623 # number of overall misses -system.cpu0.icache.overall_misses::total 945623 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13224491137 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13224491137 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13224491137 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13224491137 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13224491137 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13224491137 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7519018 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7519018 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7519018 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7519018 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7519018 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7519018 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125764 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125764 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125764 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125764 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125764 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125764 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13984.950807 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13984.950807 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13984.950807 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13984.950807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13984.950807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13984.950807 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3461 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 139 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 881127 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.683312 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6795719 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 881636 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.708078 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26872936250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.683312 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995475 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995475 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8604286 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8604286 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6795719 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6795719 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6795719 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6795719 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6795719 # number of overall hits +system.cpu0.icache.overall_hits::total 6795719 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 926821 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 926821 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 926821 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 926821 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 926821 # number of overall misses +system.cpu0.icache.overall_misses::total 926821 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13137729759 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13137729759 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13137729759 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13137729759 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13137729759 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13137729759 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7722540 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7722540 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7722540 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7722540 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7722540 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7722540 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120015 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.120015 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120015 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.120015 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120015 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.120015 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14175.045407 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14175.045407 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3568 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 70 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.034722 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 139 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.629139 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43044 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43044 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43044 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43044 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43044 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43044 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 902579 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 902579 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 902579 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 902579 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 902579 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 902579 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10909532635 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10909532635 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10909532635 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10909532635 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10909532635 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10909532635 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.120039 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.120039 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.120039 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12087.066766 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12087.066766 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12087.066766 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45075 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45075 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45075 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45075 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45075 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45075 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 881746 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 881746 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 881746 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 881746 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 881746 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 881746 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814665187 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814665187 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814665187 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10814665187 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814665187 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10814665187 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114178 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.114178 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.114178 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1164537 # number of replacements -system.cpu0.dcache.tags.tagsinuse 498.695388 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10555909 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1165049 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.060485 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26173000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.695388 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.974014 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.974014 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1281204 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.636705 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10489009 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1281716 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.183567 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26139000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.636705 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987572 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.987572 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56283368 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56283368 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6422745 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6422745 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3752316 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3752316 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172180 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172180 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 196241 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 196241 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10175061 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10175061 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10175061 # number of overall hits -system.cpu0.dcache.overall_hits::total 10175061 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1468970 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1468970 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1742020 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1742020 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20433 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20433 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2875 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2875 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3210990 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3210990 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3210990 # number of overall misses -system.cpu0.dcache.overall_misses::total 3210990 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38326965830 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 38326965830 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76755016444 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 76755016444 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 286872989 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 286872989 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20380878 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20380878 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 115081982274 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 115081982274 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 115081982274 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 115081982274 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7891715 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7891715 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5494336 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5494336 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192613 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 192613 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 199116 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199116 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13386051 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13386051 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13386051 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13386051 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186141 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.186141 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317057 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.317057 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.106083 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.106083 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014439 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014439 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239876 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.239876 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239876 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.239876 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26091.047353 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26091.047353 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44060.927225 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44060.927225 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14039.690158 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14039.690158 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7089.001043 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7089.001043 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35840.031353 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35840.031353 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35840.031353 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35840.031353 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2903843 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 789 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48428 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 56677841 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56677841 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6448265 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6448265 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3678309 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3678309 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 163487 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 163487 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188240 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 188240 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10126574 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10126574 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10126574 # number of overall hits +system.cpu0.dcache.overall_hits::total 10126574 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1590441 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1590441 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1755180 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1755180 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20486 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20486 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2716 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2716 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3345621 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3345621 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3345621 # number of overall misses +system.cpu0.dcache.overall_misses::total 3345621 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40624107085 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40624107085 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78713383276 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 78713383276 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 300049994 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 300049994 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20153405 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20153405 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 119337490361 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 119337490361 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8038706 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8038706 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5433489 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5433489 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183973 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183973 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190956 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 190956 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13472195 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13472195 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13472195 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13472195 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197848 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197848 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323030 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323030 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111353 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111353 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014223 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014223 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248335 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248335 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248335 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248335 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7420.252209 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7420.252209 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35669.757681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35669.757681 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2966485 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 566 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48680 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.962067 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 112.714286 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.938476 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 80.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 644423 # number of writebacks -system.cpu0.dcache.writebacks::total 644423 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 578811 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 578811 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1469624 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1469624 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4269 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4269 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2048435 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2048435 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2048435 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2048435 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 890159 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 890159 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272396 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 272396 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16164 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16164 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2875 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2875 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1162555 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1162555 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1162555 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1162555 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25660783347 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25660783347 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11256320137 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11256320137 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175450760 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175450760 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14630122 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14630122 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36917103484 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 36917103484 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36917103484 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 36917103484 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 999097000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 999097000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1765340999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1765340999 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2764437999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2764437999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.112797 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.112797 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049578 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049578 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083920 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083920 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014439 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014439 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086848 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086848 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086848 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086848 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28827.190813 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28827.190813 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41323.367953 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41323.367953 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10854.414749 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10854.414749 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5088.738087 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5088.738087 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31755.145764 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31755.145764 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31755.145764 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31755.145764 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 754427 # number of writebacks +system.cpu0.dcache.writebacks::total 754427 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 586151 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 586151 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1480465 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1480465 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4562 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4562 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2066616 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2066616 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2066616 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2066616 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1004290 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1004290 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274715 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 274715 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15924 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15924 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2716 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2716 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1279005 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1279005 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1279005 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1279005 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27273016452 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27273016452 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11562486348 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11562486348 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175781505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175781505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14720595 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14720595 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38835502800 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38835502800 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38835502800 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38835502800 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459363000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459363000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2145424499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2145424499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3604787499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3604787499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124932 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124932 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050560 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050560 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086556 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086556 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014223 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014223 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094937 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094937 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5419.953976 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5419.953976 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1457,35 +1491,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2770041 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2267711 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 80921 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1482926 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 969002 # Number of BTB hits +system.cpu1.branchPred.lookups 2485884 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2055798 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 72106 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1444173 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 831190 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.343921 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 198874 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 6522 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.554739 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 170291 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7410 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2016743 # DTB read hits -system.cpu1.dtb.read_misses 9789 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 278621 # DTB read accesses -system.cpu1.dtb.write_hits 1132288 # DTB write hits -system.cpu1.dtb.write_misses 1938 # DTB write misses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_accesses 105909 # DTB write accesses -system.cpu1.dtb.data_hits 3149031 # DTB hits -system.cpu1.dtb.data_misses 11727 # DTB misses -system.cpu1.dtb.data_acv 43 # DTB access violations -system.cpu1.dtb.data_accesses 384530 # DTB accesses -system.cpu1.itb.fetch_hits 369710 # ITB hits -system.cpu1.itb.fetch_misses 5636 # ITB misses -system.cpu1.itb.fetch_acv 119 # ITB acv -system.cpu1.itb.fetch_accesses 375346 # ITB accesses +system.cpu1.dtb.read_hits 1846757 # DTB read hits +system.cpu1.dtb.read_misses 10485 # DTB read misses +system.cpu1.dtb.read_acv 25 # DTB read access violations +system.cpu1.dtb.read_accesses 320297 # DTB read accesses +system.cpu1.dtb.write_hits 1188866 # DTB write hits +system.cpu1.dtb.write_misses 1998 # DTB write misses +system.cpu1.dtb.write_acv 67 # DTB write access violations +system.cpu1.dtb.write_accesses 130212 # DTB write accesses +system.cpu1.dtb.data_hits 3035623 # DTB hits +system.cpu1.dtb.data_misses 12483 # DTB misses +system.cpu1.dtb.data_acv 92 # DTB access violations +system.cpu1.dtb.data_accesses 450509 # DTB accesses +system.cpu1.itb.fetch_hits 420713 # ITB hits +system.cpu1.itb.fetch_misses 6600 # ITB misses +system.cpu1.itb.fetch_acv 223 # ITB acv +system.cpu1.itb.fetch_accesses 427313 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1498,519 +1532,553 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 18798992 # number of cpu cycles simulated +system.cpu1.numCycles 14964653 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5357256 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13511342 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2770041 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1167876 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2476292 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 427198 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 8263333 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26082 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 54640 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 162618 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1630522 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50477 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 16624070 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.812758 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.170685 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5680448 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 11756636 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2485884 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1001481 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2105616 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 381271 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 5937724 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 62153 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48156 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1420733 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 48517 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14103634 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.833589 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.209447 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 14147778 85.10% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 131100 0.79% 85.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 332329 2.00% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 198517 1.19% 89.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 395957 2.38% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 132924 0.80% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 159356 0.96% 93.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 93423 0.56% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1032686 6.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11998018 85.07% 85.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 134082 0.95% 86.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 225201 1.60% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 169062 1.20% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 292225 2.07% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 115066 0.82% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 124219 0.88% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 190666 1.35% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 855095 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 16624070 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.147351 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.718727 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5556172 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8353280 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2307081 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 131115 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 276421 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 130911 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7501 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 13245951 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 18855 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 276421 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5775463 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2664230 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 4961239 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2147700 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 799015 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 12421307 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 241 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 220838 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 145988 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 8355946 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 15113763 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 15073339 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 35607 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7070748 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1285198 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 385003 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 30758 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2314294 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2123178 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1208247 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 244787 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 150121 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 10996175 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 428151 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10636944 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 28046 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1617836 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 831016 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 312637 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 16624070 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.639852 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.326685 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14103634 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.166117 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.785627 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5621005 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6169812 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1969307 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 106628 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 236881 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 108171 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6940 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11535490 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 20476 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 236881 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5819966 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 414819 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5141752 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1873919 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 616295 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10688130 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 72 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 55241 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 150444 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7038513 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12788456 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12730882 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 51827 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5999158 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1039355 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 430985 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 39680 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1897434 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1953635 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1261748 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 176061 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 98445 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9382355 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 465021 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9121330 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28823 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1378008 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 697882 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 334259 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14103634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.646736 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.322598 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 12087523 72.71% 72.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1967089 11.83% 84.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 877391 5.28% 89.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 655455 3.94% 93.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 567827 3.42% 97.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 232884 1.40% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 149324 0.90% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 75580 0.45% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10997 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10102268 71.63% 71.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1834449 13.01% 84.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 778460 5.52% 90.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 526095 3.73% 93.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 451675 3.20% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 203961 1.45% 98.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 130101 0.92% 99.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 68435 0.49% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8190 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 16624070 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14103634 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 16676 8.84% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 99378 52.65% 61.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 72683 38.51% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3122 1.64% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 102805 54.10% 55.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 84113 44.26% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7118581 66.92% 66.96% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 18880 0.18% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 9739 0.09% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2093745 19.68% 86.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1155572 10.86% 97.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 235150 2.21% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5686452 62.34% 62.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 15839 0.17% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.55% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10725 0.12% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1931464 21.18% 83.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1211908 13.29% 97.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 259653 2.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10636944 # Type of FU issued -system.cpu1.iq.rate 0.565825 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 188737 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017744 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 37986289 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 12982235 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10383881 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 128452 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 62754 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 61527 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10755461 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 66702 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 101929 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9121330 # Type of FU issued +system.cpu1.iq.rate 0.609525 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 190040 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020835 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 32366807 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11130082 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8856102 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 198350 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 96900 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 93876 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9204439 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 103405 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 88797 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 306426 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 815 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 2923 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 138344 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 277499 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1209 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1676 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 126244 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 4845 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 18286 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 334 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 13648 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 276421 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2089253 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 85247 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 12015910 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 137996 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2123178 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1208247 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 388932 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 10076 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1666 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 2923 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 39900 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 91880 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 131780 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10541126 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2031671 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 95818 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 236881 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 252351 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 39276 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10330457 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 142523 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1953635 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1261748 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 421576 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 32385 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1813 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1676 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 32559 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 96048 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 128607 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9031900 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1864128 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 89430 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 591584 # number of nop insts executed -system.cpu1.iew.exec_refs 3170643 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1658996 # Number of branches executed -system.cpu1.iew.exec_stores 1138972 # Number of stores executed -system.cpu1.iew.exec_rate 0.560728 # Inst execution rate -system.cpu1.iew.wb_sent 10475567 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 10445408 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5214693 # num instructions producing a value -system.cpu1.iew.wb_consumers 7314185 # num instructions consuming a value +system.cpu1.iew.exec_nop 483081 # number of nop insts executed +system.cpu1.iew.exec_refs 3060773 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1345265 # Number of branches executed +system.cpu1.iew.exec_stores 1196645 # Number of stores executed +system.cpu1.iew.exec_rate 0.603549 # Inst execution rate +system.cpu1.iew.wb_sent 8976284 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8949978 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4203498 # num instructions producing a value +system.cpu1.iew.wb_consumers 5915948 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.555637 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712956 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.598075 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710537 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1685534 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 115514 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 123376 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 16347649 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.627728 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.542862 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1403439 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 130762 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 120016 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13866753 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.637072 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.578145 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12457643 76.20% 76.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1697144 10.38% 86.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 844179 5.16% 91.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 419187 2.56% 94.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 268727 1.64% 95.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 133453 0.82% 96.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 126834 0.78% 97.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 88227 0.54% 98.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 312255 1.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10553407 76.11% 76.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1550482 11.18% 87.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 573583 4.14% 91.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 351937 2.54% 93.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 252477 1.82% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 99182 0.72% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 104002 0.75% 97.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 102635 0.74% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 279048 2.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 16347649 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10261869 # Number of instructions committed -system.cpu1.commit.committedOps 10261869 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13866753 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8834118 # Number of instructions committed +system.cpu1.commit.committedOps 8834118 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2886655 # Number of memory references committed -system.cpu1.commit.loads 1816752 # Number of loads committed -system.cpu1.commit.membars 36648 # Number of memory barriers committed -system.cpu1.commit.branches 1542101 # Number of branches committed -system.cpu1.commit.fp_insts 60269 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9518406 # Number of committed integer instructions. -system.cpu1.commit.function_calls 159983 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 312255 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2811640 # Number of memory references committed +system.cpu1.commit.loads 1676136 # Number of loads committed +system.cpu1.commit.membars 41495 # Number of memory barriers committed +system.cpu1.commit.branches 1262292 # Number of branches committed +system.cpu1.commit.fp_insts 92546 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8189363 # Number of committed integer instructions. +system.cpu1.commit.function_calls 139415 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 427272 4.84% 4.84% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5265448 59.60% 64.44% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 15610 0.18% 64.62% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.62% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10725 0.12% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1763 0.02% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1717631 19.44% 84.20% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1136016 12.86% 97.06% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 259653 2.94% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 8834118 # Class of committed instruction +system.cpu1.commit.bw_lim_events 279048 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 27899142 # The number of ROB reads -system.cpu1.rob.rob_writes 24169847 # The number of ROB writes -system.cpu1.timesIdled 181051 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2174922 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3790987217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9739356 # Number of Instructions Simulated -system.cpu1.committedOps 9739356 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 9739356 # Number of Instructions Simulated -system.cpu1.cpi 1.930209 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.930209 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.518079 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.518079 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13792462 # number of integer regfile reads -system.cpu1.int_regfile_writes 7586165 # number of integer regfile writes -system.cpu1.fp_regfile_reads 35303 # number of floating regfile reads -system.cpu1.fp_regfile_writes 34737 # number of floating regfile writes -system.cpu1.misc_regfile_reads 829246 # number of misc regfile reads -system.cpu1.misc_regfile_writes 174995 # number of misc regfile writes -system.cpu1.icache.tags.replacements 184023 # number of replacements -system.cpu1.icache.tags.tagsinuse 502.144736 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1436916 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 184535 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.786685 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1712232500000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 502.144736 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980751 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980751 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 23736453 # The number of ROB reads +system.cpu1.rob.rob_writes 20710450 # The number of ROB writes +system.cpu1.timesIdled 126022 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 861019 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3795679739 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8410372 # Number of Instructions Simulated +system.cpu1.committedOps 8410372 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8410372 # Number of Instructions Simulated +system.cpu1.cpi 1.779309 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.779309 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.562016 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.562016 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11653751 # number of integer regfile reads +system.cpu1.int_regfile_writes 6367365 # number of integer regfile writes +system.cpu1.fp_regfile_reads 51509 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51143 # number of floating regfile writes +system.cpu1.misc_regfile_reads 926936 # number of misc regfile reads +system.cpu1.misc_regfile_writes 206554 # number of misc regfile writes +system.cpu1.icache.tags.replacements 210820 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.468430 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1201520 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 211332 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.685462 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1879665276250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.468430 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918884 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.918884 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1815116 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1815116 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1436916 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1436916 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1436916 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1436916 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1436916 # number of overall hits -system.cpu1.icache.overall_hits::total 1436916 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 193606 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 193606 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 193606 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 193606 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 193606 # number of overall misses -system.cpu1.icache.overall_misses::total 193606 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2794361223 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2794361223 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2794361223 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2794361223 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2794361223 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2794361223 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1630522 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1630522 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1630522 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1630522 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1630522 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1630522 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.118739 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.118739 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.118739 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.118739 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.118739 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.118739 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14433.236692 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14433.236692 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14433.236692 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14433.236692 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14433.236692 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14433.236692 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1663 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 1632124 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1632124 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1201520 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1201520 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1201520 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1201520 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1201520 # number of overall hits +system.cpu1.icache.overall_hits::total 1201520 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 219211 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 219211 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 219211 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 219211 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 219211 # number of overall misses +system.cpu1.icache.overall_misses::total 219211 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2949137410 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2949137410 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2949137410 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2949137410 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2949137410 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2949137410 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1420731 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1420731 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1420731 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1420731 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1420731 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1420731 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154295 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.154295 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154295 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.154295 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154295 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.154295 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.418898 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.418898 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13453.418898 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13453.418898 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 63 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.396825 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.380952 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9012 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 9012 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 9012 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 9012 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 9012 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 9012 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 184594 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 184594 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 184594 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 184594 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 184594 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 184594 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2304763360 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2304763360 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2304763360 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2304763360 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2304763360 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2304763360 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.113212 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.113212 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.113212 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12485.581113 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12485.581113 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12485.581113 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7818 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7818 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7818 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7818 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7818 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7818 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211393 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 211393 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 211393 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 211393 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 211393 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 211393 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2447786762 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2447786762 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2447786762 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2447786762 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2447786762 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2447786762 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148792 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.148792 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.148792 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 203792 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.930753 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2483389 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 204116 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 12.166557 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 43808643250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.930753 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960802 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.960802 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12059624 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12059624 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1586410 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1586410 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 857564 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 857564 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 22125 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 22125 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 21120 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 21120 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2443974 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2443974 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2443974 # number of overall hits -system.cpu1.dcache.overall_hits::total 2443974 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 285731 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 285731 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 181299 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 181299 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4484 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4484 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2742 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2742 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 467030 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 467030 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 467030 # number of overall misses -system.cpu1.dcache.overall_misses::total 467030 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4578373047 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1872141 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1872141 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1038863 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1038863 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 26609 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 26609 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 23862 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 23862 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2911004 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2911004 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2911004 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160436 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.160436 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16023.368297 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16023.368297 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 57562.775575 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 57562.775575 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12575.489964 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12575.489964 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7495.961707 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7495.961707 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32148.784224 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32148.784224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32148.784224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32148.784224 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 370227 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 102235 # number of replacements +system.cpu1.dcache.tags.tagsinuse 491.253867 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2477501 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 102637 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.138478 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 45814117000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.253867 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959480 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.959480 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11642464 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11642464 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1521331 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1521331 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 890954 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 890954 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30283 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 30283 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29173 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 29173 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2412285 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2412285 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2412285 # number of overall hits +system.cpu1.dcache.overall_hits::total 2412285 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 196472 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 196472 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 206616 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 206616 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5011 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5011 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2898 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2898 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 403088 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 403088 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 403088 # number of overall misses +system.cpu1.dcache.overall_misses::total 403088 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2745758970 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2745758970 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6806020354 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6806020354 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50048997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 50048997 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21170434 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 21170434 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9551779324 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9551779324 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9551779324 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9551779324 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1717803 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1717803 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1097570 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1097570 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 35294 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 35294 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32071 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 32071 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2815373 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2815373 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2815373 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2815373 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114374 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114374 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188249 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.188249 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.141979 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.141979 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090362 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090362 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143174 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.143174 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143174 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.143174 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13975.319486 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13975.319486 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32940.432270 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32940.432270 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9987.826182 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9987.826182 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7305.187716 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7305.187716 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23696.511243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23696.511243 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 206242 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6127 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3728 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 60.425494 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 55.322425 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 162776 # number of writebacks -system.cpu1.dcache.writebacks::total 162776 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 104604 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 104604 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 148843 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 148843 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 899 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 899 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 253447 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 253447 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 253447 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 253447 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181127 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 181127 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32456 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 32456 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3585 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3585 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2742 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2742 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 213583 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 213583 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 213583 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 213583 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2418933900 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2418933900 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1545787184 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1545787184 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26756251 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 26756251 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15069073 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15069073 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3964721084 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3964721084 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3964721084 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3964721084 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485705000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485705000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 998872003 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 998872003 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1484577003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1484577003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096749 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096749 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031242 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031242 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.134729 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.134729 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.114911 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.114911 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.073371 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.073371 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.073371 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.073371 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13354.905122 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13354.905122 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47627.162435 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47627.162435 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7463.389400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7463.389400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5495.650255 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5495.650255 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18562.905681 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18562.905681 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18562.905681 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18562.905681 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 67781 # number of writebacks +system.cpu1.dcache.writebacks::total 67781 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 121809 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 121809 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 169922 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 169922 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 539 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 539 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 291731 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 291731 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 291731 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 291731 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 74663 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 74663 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36694 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 36694 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4472 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4472 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2897 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2897 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 111357 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 111357 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 111357 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 111357 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 836811454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 836811454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 998585721 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 998585721 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34130252 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34130252 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15375566 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15375566 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1835397175 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1835397175 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1835397175 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1835397175 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23621500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23621500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 617644004 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 617644004 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641265504 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641265504 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043464 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043464 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033432 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033432 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.126707 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.126707 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090331 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090331 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039553 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039553 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7631.988372 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7631.988372 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5307.409734 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5307.409734 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2019,161 +2087,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5026 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 189626 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 66604 40.25% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.08% 40.33% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.16% 41.49% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 191 0.12% 41.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 96634 58.39% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 165488 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 65244 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.45% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 191 0.14% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 65055 49.08% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 132549 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865394285500 97.91% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63356500 0.00% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 573165000 0.03% 97.94% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 85999500 0.00% 97.95% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39121861000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1905238667500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.979581 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6589 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 184914 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65370 40.53% 40.53% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.19% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 186 0.12% 41.92% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 93691 58.08% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 161304 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64362 49.21% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.47% 50.79% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64176 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 130781 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863832959500 97.81% 97.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63684000 0.00% 97.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 569763500 0.03% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 89287000 0.00% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 41094897500 2.16% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1905650591500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984580 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.673210 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.800958 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 232 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.684975 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810773 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 211 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 273 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wripir 277 0.16% 0.16% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3846 2.21% 2.37% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.39% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.40% # number of callpals executed -system.cpu0.kern.callpal::swpipl 158278 90.80% 93.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6346 3.64% 96.84% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.84% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.84% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.85% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.85% # number of callpals executed -system.cpu0.kern.callpal::rti 4961 2.85% 99.70% # number of callpals executed -system.cpu0.kern.callpal::callsys 391 0.22% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 174309 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7462 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1354 # number of protection mode switches +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3529 2.08% 2.24% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 154533 90.92% 93.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6537 3.85% 97.04% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.05% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed +system.cpu0.kern.callpal::rti 4527 2.66% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 169959 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7072 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1353 -system.cpu0.kern.mode_good::user 1354 +system.cpu0.kern.mode_good::kernel 1286 +system.cpu0.kern.mode_good::user 1287 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181319 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181844 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.307055 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1903211741000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2026918500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.307812 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1903707301000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1943282500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3847 # number of times the context was actually changed +system.cpu0.kern.swap_context 3530 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3999 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 49848 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 15658 37.06% 37.06% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 4.55% 41.62% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 273 0.65% 42.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 24392 57.74% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 42247 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 15641 47.10% 47.10% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 5.79% 52.90% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 273 0.82% 53.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15369 46.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 33207 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871713408000 98.26% 98.26% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533048500 0.03% 98.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 128777500 0.01% 98.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 32519855000 1.71% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1904895089000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998914 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2439 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 54740 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16948 36.40% 36.40% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 4.13% 40.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 277 0.59% 41.13% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 27412 58.87% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 46562 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16579 47.26% 47.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.49% 52.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 277 0.79% 53.53% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16302 46.47% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 35083 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874130150000 98.36% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532183000 0.03% 98.39% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 125676500 0.01% 98.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 30535391000 1.60% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1905323400500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978228 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630084 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.786020 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed -system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed -system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 94 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.594703 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.753468 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed +system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed +system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 115 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 191 0.44% 0.44% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.44% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed -system.cpu1.kern.callpal::swpctx 742 1.70% 2.15% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.15% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 2.17% # number of callpals executed -system.cpu1.kern.callpal::swpipl 37463 85.96% 88.13% # number of callpals executed -system.cpu1.kern.callpal::rdps 2409 5.53% 93.66% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.66% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.67% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.68% # number of callpals executed -system.cpu1.kern.callpal::rti 2587 5.94% 99.62% # number of callpals executed -system.cpu1.kern.callpal::callsys 124 0.28% 99.90% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.10% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 186 0.39% 0.39% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.39% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1067 2.22% 2.61% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.63% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.64% # number of callpals executed +system.cpu1.kern.callpal::swpipl 41329 85.97% 88.61% # number of callpals executed +system.cpu1.kern.callpal::rdps 2224 4.63% 93.23% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.23% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.24% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.24% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.25% # number of callpals executed +system.cpu1.kern.callpal::rti 3030 6.30% 99.55% # number of callpals executed +system.cpu1.kern.callpal::callsys 172 0.36% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 43580 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 937 # number of protection mode switches -system.cpu1.kern.mode_switch::user 383 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2395 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 617 -system.cpu1.kern.mode_good::user 383 -system.cpu1.kern.mode_good::idle 234 -system.cpu1.kern.mode_switch_good::kernel 0.658485 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 48076 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1341 # number of protection mode switches +system.cpu1.kern.mode_switch::user 460 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2398 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 662 +system.cpu1.kern.mode_good::user 460 +system.cpu1.kern.mode_good::idle 202 +system.cpu1.kern.mode_switch_good::kernel 0.493661 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.097704 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.332167 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 34875641000 1.83% 1.83% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 708299500 0.04% 1.87% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868990228500 98.13% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 743 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.084237 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.315313 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4271038500 0.22% 0.22% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 809340000 0.04% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1900232555000 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1068 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 0b1609ec3..272c07d73 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,128 +1,128 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860192 # Number of seconds simulated -sim_ticks 1860191785500 # Number of ticks simulated -final_tick 1860191785500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860188 # Number of seconds simulated +sim_ticks 1860187818000 # Number of ticks simulated +final_tick 1860187818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128947 # Simulator instruction rate (inst/s) -host_op_rate 128947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4527634915 # Simulator tick rate (ticks/s) -host_mem_usage 347764 # Number of bytes of host memory used -host_seconds 410.85 # Real time elapsed on the host -sim_insts 52978349 # Number of instructions simulated -sim_ops 52978349 # Number of ops (including micro ops) simulated +host_inst_rate 129673 # Simulator instruction rate (inst/s) +host_op_rate 129673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4553007725 # Simulator tick rate (ticks/s) +host_mem_usage 348812 # Number of bytes of host memory used +host_seconds 408.56 # Real time elapsed on the host +sim_insts 52979638 # Number of instructions simulated +sim_ops 52979638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 963264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 963200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881344 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28492800 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15051 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516608 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388771 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445200 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13373486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15317130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13373486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19357247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445200 # Number of read requests accepted -system.physmem.writeReqs 117428 # Number of write requests accepted -system.physmem.readBursts 445200 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117428 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28485504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.physmem.bytesWritten 7513728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28492800 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7515392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 445263 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117447 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117447 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13375716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15319331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517797 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517797 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040779 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040779 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517797 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13375716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19360110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445263 # Number of read requests accepted +system.physmem.writeReqs 117447 # Number of write requests accepted +system.physmem.readBursts 445263 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117447 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28490624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue +system.physmem.bytesWritten 7515520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28496832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7516608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 178 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28210 # Per bank write bursts -system.physmem.perBankRdBursts::1 27995 # Per bank write bursts -system.physmem.perBankRdBursts::2 28357 # Per bank write bursts -system.physmem.perBankRdBursts::3 27829 # Per bank write bursts -system.physmem.perBankRdBursts::4 27761 # Per bank write bursts -system.physmem.perBankRdBursts::5 27267 # Per bank write bursts -system.physmem.perBankRdBursts::6 27371 # Per bank write bursts -system.physmem.perBankRdBursts::7 27375 # Per bank write bursts -system.physmem.perBankRdBursts::8 27696 # Per bank write bursts -system.physmem.perBankRdBursts::9 27269 # Per bank write bursts -system.physmem.perBankRdBursts::10 28017 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 171 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28211 # Per bank write bursts +system.physmem.perBankRdBursts::1 27992 # Per bank write bursts +system.physmem.perBankRdBursts::2 28433 # Per bank write bursts +system.physmem.perBankRdBursts::3 27987 # Per bank write bursts +system.physmem.perBankRdBursts::4 27796 # Per bank write bursts +system.physmem.perBankRdBursts::5 27217 # Per bank write bursts +system.physmem.perBankRdBursts::6 27269 # Per bank write bursts +system.physmem.perBankRdBursts::7 27319 # Per bank write bursts +system.physmem.perBankRdBursts::8 27690 # Per bank write bursts +system.physmem.perBankRdBursts::9 27272 # Per bank write bursts +system.physmem.perBankRdBursts::10 28021 # Per bank write bursts system.physmem.perBankRdBursts::11 27509 # Per bank write bursts -system.physmem.perBankRdBursts::12 27546 # Per bank write bursts -system.physmem.perBankRdBursts::13 28232 # Per bank write bursts -system.physmem.perBankRdBursts::14 28342 # Per bank write bursts -system.physmem.perBankRdBursts::15 28310 # Per bank write bursts -system.physmem.perBankWrBursts::0 7920 # Per bank write bursts -system.physmem.perBankWrBursts::1 7516 # Per bank write bursts -system.physmem.perBankWrBursts::2 7873 # Per bank write bursts -system.physmem.perBankWrBursts::3 7373 # Per bank write bursts -system.physmem.perBankWrBursts::4 7309 # Per bank write bursts -system.physmem.perBankWrBursts::5 6720 # Per bank write bursts -system.physmem.perBankWrBursts::6 6881 # Per bank write bursts -system.physmem.perBankWrBursts::7 6774 # Per bank write bursts -system.physmem.perBankWrBursts::8 7136 # Per bank write bursts -system.physmem.perBankWrBursts::9 6679 # Per bank write bursts -system.physmem.perBankWrBursts::10 7411 # Per bank write bursts -system.physmem.perBankWrBursts::11 6967 # Per bank write bursts -system.physmem.perBankWrBursts::12 7107 # Per bank write bursts -system.physmem.perBankWrBursts::13 7877 # Per bank write bursts -system.physmem.perBankWrBursts::14 8064 # Per bank write bursts -system.physmem.perBankWrBursts::15 7795 # Per bank write bursts +system.physmem.perBankRdBursts::12 27548 # Per bank write bursts +system.physmem.perBankRdBursts::13 28237 # Per bank write bursts +system.physmem.perBankRdBursts::14 28335 # Per bank write bursts +system.physmem.perBankRdBursts::15 28330 # Per bank write bursts +system.physmem.perBankWrBursts::0 7921 # Per bank write bursts +system.physmem.perBankWrBursts::1 7511 # Per bank write bursts +system.physmem.perBankWrBursts::2 7946 # Per bank write bursts +system.physmem.perBankWrBursts::3 7492 # Per bank write bursts +system.physmem.perBankWrBursts::4 7346 # Per bank write bursts +system.physmem.perBankWrBursts::5 6678 # Per bank write bursts +system.physmem.perBankWrBursts::6 6778 # Per bank write bursts +system.physmem.perBankWrBursts::7 6711 # Per bank write bursts +system.physmem.perBankWrBursts::8 7130 # Per bank write bursts +system.physmem.perBankWrBursts::9 6681 # Per bank write bursts +system.physmem.perBankWrBursts::10 7414 # Per bank write bursts +system.physmem.perBankWrBursts::11 6966 # Per bank write bursts +system.physmem.perBankWrBursts::12 7109 # Per bank write bursts +system.physmem.perBankWrBursts::13 7879 # Per bank write bursts +system.physmem.perBankWrBursts::14 8056 # Per bank write bursts +system.physmem.perBankWrBursts::15 7812 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 1860186344000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1860182401000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445200 # Read request sizes (log2) +system.physmem.readPktSize::6 445263 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117428 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 322906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56729 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1891 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117447 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 316668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3992 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2540 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1617 # 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What read queue length does an incoming req see @@ -148,132 +148,129 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 651.388927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 428.580055 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.495686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8350 17.18% 17.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6347 13.06% 30.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2940 6.05% 36.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1813 3.73% 40.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1501 3.09% 43.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 899 1.85% 44.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 723 1.49% 46.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 886 1.82% 48.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25144 51.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48603 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6893 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 64.568403 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2543.170744 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6890 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1100 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63749 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 564.805095 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 351.189585 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.649920 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13350 20.94% 20.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10335 16.21% 37.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4789 7.51% 44.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2797 4.39% 49.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2437 3.82% 52.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.47% 55.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1469 2.30% 57.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1613 2.53% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25383 39.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63749 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6887 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 64.637723 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 16.523346 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2544.314640 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6884 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6893 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6893 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.032062 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.789521 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.768510 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5850 84.87% 84.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 28 0.41% 85.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 70 1.02% 86.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 418 6.06% 92.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 134 1.94% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 49 0.71% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 24 0.35% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.32% 95.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 53 0.77% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 38 0.55% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.29% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 34 0.49% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 19 0.28% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 34 0.49% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 7 0.10% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.15% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.03% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.03% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 3 0.04% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 6 0.09% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 5 0.07% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 5 0.07% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 8 0.12% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.06% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 2 0.03% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 5 0.07% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 6 0.09% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 6 0.09% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 4 0.06% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 3 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 6 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6893 # Writes before turning the bus around for reads -system.physmem.totQLat 10196532000 # Total ticks spent queuing -system.physmem.totMemAccLat 17805650750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225430000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5383688750 # Total ticks spent accessing banks -system.physmem.avgQLat 22909.13 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 12095.84 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6887 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6887 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.050966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.814496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.834643 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5493 79.76% 79.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 28 0.41% 80.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 690 10.02% 90.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 216 3.14% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 116 1.68% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 20 0.29% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 25 0.36% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 93 1.35% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 19 0.28% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 44 0.64% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 11 0.16% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 7 0.10% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 8 0.12% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 16 0.23% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.03% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 14 0.20% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 9 0.13% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.01% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.01% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 3 0.04% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.03% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.01% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.01% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 2 0.03% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 7 0.10% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 4 0.06% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 3 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 1 0.01% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 3 0.04% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 3 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 7 0.10% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 4 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.01% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 7 0.10% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 17 0.25% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6887 # Writes before turning the bus around for reads +system.physmem.totQLat 8647566500 # Total ticks spent queuing +system.physmem.totMemAccLat 16994429000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225830000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19425.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40004.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 38175.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s @@ -281,60 +278,64 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.57 # Average write queue length when enqueuing -system.physmem.readRowHits 402462 # Number of row buffer hits during reads -system.physmem.writeRowHits 96189 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.91 # Row buffer hit rate for writes -system.physmem.avgGap 3306245.59 # Average gap between requests -system.physmem.pageHitRate 88.65 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19400105 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295926 # Transaction distribution -system.membus.trans_dist::ReadResp 295846 # Transaction distribution +system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.02 # Average write queue length when enqueuing +system.physmem.readRowHits 403062 # Number of row buffer hits during reads +system.physmem.writeRowHits 95784 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.56 # Row buffer hit rate for writes +system.physmem.avgGap 3305756.79 # Average gap between requests +system.physmem.pageHitRate 88.67 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1761433244000 # Time in different power states +system.physmem.memoryStateTime::REF 62115560000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 36633312250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 19402968 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295944 # Transaction distribution +system.membus.trans_dist::ReadResp 295866 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117428 # Transaction distribution -system.membus.trans_dist::UpgradeReq 181 # Transaction distribution -system.membus.trans_dist::UpgradeResp 181 # Transaction distribution -system.membus.trans_dist::ReadExReq 156840 # Transaction distribution -system.membus.trans_dist::ReadExResp 156840 # Transaction distribution -system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.trans_dist::Writeback 117447 # Transaction distribution +system.membus.trans_dist::UpgradeReq 174 # Transaction distribution +system.membus.trans_dist::UpgradeResp 174 # Transaction distribution +system.membus.trans_dist::ReadExReq 156883 # Transaction distribution +system.membus.trans_dist::ReadExResp 156883 # Transaction distribution +system.membus.trans_dist::BadAddressError 78 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884195 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699136 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30743276 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704384 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748524 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36052332 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36052332 # Total data (bytes) +system.membus.tot_pkt_size::total 36057580 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36057580 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29929000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29864500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1552530249 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1548275500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 100500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 98000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3767548549 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3770327047 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376726994 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376611244 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261130 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261115 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710337661000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261130 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078821 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078821 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710335896000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261115 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -348,14 +349,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 13194182648 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 13194182648 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13215316531 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13215316531 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13215316531 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13215316531 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21272883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21272883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12456693929 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12456693929 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12477966812 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12477966812 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12477966812 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12477966812 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -372,19 +373,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 317534.237774 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 316724.182888 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 316724.182888 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 393531 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122964.641618 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 299785.664445 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 299052.529946 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 299052.529946 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 365915 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28535 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28370 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.791169 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.897956 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -398,14 +399,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11031075660 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 11031075660 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 11043212543 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 11043212543 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 11043212543 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 11043212543 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12274883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12274883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10293819441 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10293819441 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10306094324 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10306094324 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10306094324 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10306094324 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -414,14 +415,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -435,36 +436,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13847711 # Number of BP lookups -system.cpu.branchPred.condPredicted 11622265 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 397151 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9355929 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5809145 # Number of BTB hits +system.cpu.branchPred.lookups 13846630 # Number of BP lookups +system.cpu.branchPred.condPredicted 11622667 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 398238 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9513264 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5817388 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.090520 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 903416 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38861 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.150284 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 900921 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39034 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9926060 # DTB read hits -system.cpu.dtb.read_misses 41229 # DTB read misses -system.cpu.dtb.read_acv 545 # DTB read access violations -system.cpu.dtb.read_accesses 943227 # DTB read accesses -system.cpu.dtb.write_hits 6592681 # DTB write hits -system.cpu.dtb.write_misses 10567 # DTB write misses -system.cpu.dtb.write_acv 408 # DTB write access violations -system.cpu.dtb.write_accesses 338977 # DTB write accesses -system.cpu.dtb.data_hits 16518741 # DTB hits -system.cpu.dtb.data_misses 51796 # DTB misses -system.cpu.dtb.data_acv 953 # DTB access violations -system.cpu.dtb.data_accesses 1282204 # DTB accesses -system.cpu.itb.fetch_hits 1307907 # ITB hits -system.cpu.itb.fetch_misses 36763 # ITB misses -system.cpu.itb.fetch_acv 1058 # ITB acv -system.cpu.itb.fetch_accesses 1344670 # ITB accesses +system.cpu.dtb.read_hits 9912884 # DTB read hits +system.cpu.dtb.read_misses 41215 # DTB read misses +system.cpu.dtb.read_acv 553 # DTB read access violations +system.cpu.dtb.read_accesses 941108 # DTB read accesses +system.cpu.dtb.write_hits 6599017 # DTB write hits +system.cpu.dtb.write_misses 10339 # DTB write misses +system.cpu.dtb.write_acv 401 # DTB write access violations +system.cpu.dtb.write_accesses 338138 # DTB write accesses +system.cpu.dtb.data_hits 16511901 # DTB hits +system.cpu.dtb.data_misses 51554 # DTB misses +system.cpu.dtb.data_acv 954 # DTB access violations +system.cpu.dtb.data_accesses 1279246 # DTB accesses +system.cpu.itb.fetch_hits 1308304 # ITB hits +system.cpu.itb.fetch_misses 36786 # ITB misses +system.cpu.itb.fetch_acv 1079 # ITB acv +system.cpu.itb.fetch_accesses 1345090 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -477,269 +478,304 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122133073 # number of cpu cycles simulated +system.cpu.numCycles 121969353 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28029052 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70711644 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13847711 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6712561 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13244944 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1986135 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38034896 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253831 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 364385 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8541461 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 263003 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81242947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.213979 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28022459 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70674133 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13846630 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6718309 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13243332 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1983249 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37995640 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254581 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 364654 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8542175 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264688 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81194854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.870426 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.213908 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67998003 83.70% 83.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 851901 1.05% 84.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1695578 2.09% 86.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 822984 1.01% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2755109 3.39% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 560259 0.69% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 643349 0.79% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1008302 1.24% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4907462 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67951522 83.69% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 854853 1.05% 84.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1698258 2.09% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 823227 1.01% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2753963 3.39% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 558188 0.69% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 642929 0.79% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1006595 1.24% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4905319 6.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81242947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.113382 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.578972 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29204589 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37726390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12112827 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 958015 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1241125 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 582779 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42656 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69393384 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129440 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1241125 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30348079 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14012797 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20034433 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11321379 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4285132 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65602946 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7156 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505213 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1511728 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43797820 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79654521 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79475437 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166633 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179156 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5618656 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682920 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240154 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12205182 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10434201 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6904424 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1321264 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 860087 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58162225 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2049609 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56784496 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 110090 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6876207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3554384 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1388666 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81242947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.698947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361354 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81194854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.113525 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.579442 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29206421 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37679452 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12104138 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 965352 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1239490 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585042 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69357398 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129450 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1239490 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30354385 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13996332 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19984766 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11324382 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4295497 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65588313 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7118 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505148 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1530678 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43795306 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79617271 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79438234 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180209 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5615089 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682372 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239607 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12205686 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10422971 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6895231 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1319326 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 854507 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58152614 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2049745 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56795087 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 97937 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6861282 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3503589 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1388801 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81194854 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.699491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361721 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56591956 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10816248 13.31% 82.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5164366 6.36% 89.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3390360 4.17% 93.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2636798 3.25% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1463129 1.80% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 751413 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332295 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96382 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56519522 69.61% 69.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10856431 13.37% 82.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5145956 6.34% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3402319 4.19% 93.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2626681 3.24% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1459376 1.80% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 753323 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 333723 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 97523 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81242947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81194854 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91428 11.57% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372699 47.16% 58.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326088 41.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 92642 11.69% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372744 47.05% 58.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326922 41.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38710597 68.17% 68.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61705 0.11% 68.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10355398 18.24% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6671255 11.75% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38726894 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61723 0.11% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10344006 18.21% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6676923 11.76% 98.33% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56784496 # Type of FU issued -system.cpu.iq.rate 0.464940 # Inst issue rate -system.cpu.iq.fu_busy_cnt 790215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013916 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195020122 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66766340 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55549754 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692121 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 335594 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327937 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57205980 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 599867 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56795087 # Type of FU issued +system.cpu.iq.rate 0.465650 # Inst issue rate +system.cpu.iq.fu_busy_cnt 792308 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013950 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194982001 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66741051 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55566428 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693271 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336387 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327889 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57217918 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362191 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598643 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1342082 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3325 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14250 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 526611 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1330641 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3245 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 517313 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17915 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 172386 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17932 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 166827 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1241125 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10205447 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 698563 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63733516 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 684669 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10434201 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6904424 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805473 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512478 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17546 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14250 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 200257 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411476 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 611733 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56321962 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9995488 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 462533 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1239490 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10213175 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 697716 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63724678 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 681593 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10422971 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6895231 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805950 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512370 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16905 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 202448 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409860 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 612308 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56329043 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9982328 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 466043 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3521682 # number of nop insts executed -system.cpu.iew.exec_refs 16613940 # number of memory reference insts executed -system.cpu.iew.exec_branches 8922207 # Number of branches executed -system.cpu.iew.exec_stores 6618452 # Number of stores executed -system.cpu.iew.exec_rate 0.461152 # Inst execution rate -system.cpu.iew.wb_sent 55993079 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55877691 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27722224 # num instructions producing a value -system.cpu.iew.wb_consumers 37565081 # num instructions consuming a value +system.cpu.iew.exec_nop 3522319 # number of nop insts executed +system.cpu.iew.exec_refs 16606918 # number of memory reference insts executed +system.cpu.iew.exec_branches 8922931 # Number of branches executed +system.cpu.iew.exec_stores 6624590 # Number of stores executed +system.cpu.iew.exec_rate 0.461829 # Inst execution rate +system.cpu.iew.wb_sent 56008659 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55894317 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27713107 # num instructions producing a value +system.cpu.iew.wb_consumers 37520284 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.457515 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737979 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458265 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738617 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7447390 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660943 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 565908 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80001822 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.702098 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.631989 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7436889 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660944 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 566942 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79955364 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.702522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.631936 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59240837 74.05% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8588333 10.74% 84.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4609463 5.76% 90.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2533581 3.17% 93.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1517845 1.90% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611107 0.76% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522353 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 526375 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1851928 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59166975 74.00% 74.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8627079 10.79% 84.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4603678 5.76% 90.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2536989 3.17% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1507337 1.89% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 611638 0.76% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 523619 0.65% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 528614 0.66% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1849435 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80001822 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56169084 # Number of instructions committed -system.cpu.commit.committedOps 56169084 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79955364 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56170432 # Number of instructions committed +system.cpu.commit.committedOps 56170432 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15469932 # Number of memory references committed -system.cpu.commit.loads 9092119 # Number of loads committed -system.cpu.commit.membars 226344 # Number of memory barriers committed -system.cpu.commit.branches 8439731 # Number of branches committed +system.cpu.commit.refs 15470248 # Number of memory references committed +system.cpu.commit.loads 9092330 # Number of loads committed +system.cpu.commit.membars 226348 # Number of memory barriers committed +system.cpu.commit.branches 8439871 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52018783 # Number of committed integer instructions. -system.cpu.commit.function_calls 740550 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1851928 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52020070 # Number of committed integer instructions. +system.cpu.commit.function_calls 740568 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198067 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36230888 64.50% 70.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9318678 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383871 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949012 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 56170432 # Class of committed instruction +system.cpu.commit.bw_lim_events 1849435 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141516799 # The number of ROB reads -system.cpu.rob.rob_writes 128475885 # The number of ROB writes -system.cpu.timesIdled 1198400 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40890126 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598244060 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52978349 # Number of Instructions Simulated -system.cpu.committedOps 52978349 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52978349 # Number of Instructions Simulated -system.cpu.cpi 2.305339 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.305339 # CPI: Total CPI of All Threads -system.cpu.ipc 0.433776 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433776 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73853807 # number of integer regfile reads -system.cpu.int_regfile_writes 40298046 # number of integer regfile writes -system.cpu.fp_regfile_reads 166062 # number of floating regfile reads -system.cpu.fp_regfile_writes 167446 # number of floating regfile writes -system.cpu.misc_regfile_reads 2027357 # number of misc regfile reads -system.cpu.misc_regfile_writes 938942 # number of misc regfile writes +system.cpu.rob.rob_reads 141463709 # The number of ROB reads +system.cpu.rob.rob_writes 128455843 # The number of ROB writes +system.cpu.timesIdled 1197783 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40774499 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598399845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979638 # Number of Instructions Simulated +system.cpu.committedOps 52979638 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52979638 # Number of Instructions Simulated +system.cpu.cpi 2.302193 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.302193 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434368 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434368 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73867254 # number of integer regfile reads +system.cpu.int_regfile_writes 40307997 # number of integer regfile writes +system.cpu.fp_regfile_reads 166020 # number of floating regfile reads +system.cpu.fp_regfile_writes 167441 # number of floating regfile writes +system.cpu.misc_regfile_reads 2027897 # number of misc regfile reads +system.cpu.misc_regfile_writes 938938 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -771,7 +807,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454553 # Throughput (bytes/s) +system.iobus.throughput 1454556 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51149 # Transaction distribution @@ -831,241 +867,241 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380111537 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380172568 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43192006 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43172756 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111856774 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2116112 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2116015 # Transaction distribution +system.cpu.toL2Bus.throughput 111944057 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2118154 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2118059 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840946 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342408 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2017437 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3676056 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5693493 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64554304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143513388 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208067692 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208057644 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17408 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2478840496 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 64 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020220 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677927 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5698147 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64643392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586284 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208229676 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208219628 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17344 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2480508998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1516414125 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1518532368 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186111163 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2189805164 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1008048 # number of replacements -system.cpu.icache.tags.tagsinuse 509.665585 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7476650 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1008556 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.413222 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26682759250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.665585 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995441 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1009436 # number of replacements +system.cpu.icache.tags.tagsinuse 509.668112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7476172 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1009944 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.402561 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26651967250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.668112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995446 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995446 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9550236 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9550236 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7476651 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7476651 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7476651 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7476651 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7476651 # number of overall hits -system.cpu.icache.overall_hits::total 7476651 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064809 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064809 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064809 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064809 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064809 # number of overall misses -system.cpu.icache.overall_misses::total 1064809 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14791038698 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14791038698 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14791038698 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14791038698 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14791038698 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14791038698 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8541460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8541460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8541460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8541460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8541460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8541460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124664 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124664 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124664 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124664 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124664 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124664 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13890.790459 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13890.790459 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13890.790459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13890.790459 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5929 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 286 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9552342 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9552342 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7476173 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7476173 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7476173 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7476173 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7476173 # number of overall hits +system.cpu.icache.overall_hits::total 7476173 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1066002 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066002 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1066002 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1066002 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1066002 # number of overall misses +system.cpu.icache.overall_misses::total 1066002 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14786308436 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14786308436 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14786308436 # 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Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1401230 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994514 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11803041 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401742 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.420266 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25812000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994514 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 417 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63734677 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63734677 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7206132 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7206132 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203012 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186466 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186466 # 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miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247643 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247643 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247643 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247643 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31490.266682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31490.266682 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3050951 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 663 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 86776 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31136.036672 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31136.036672 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3013190 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 80012 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.158926 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 94.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.659226 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 118.428571 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421687998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421687998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120220 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120220 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5146 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5146 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2368528 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2368528 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2368528 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2368528 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083943 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083943 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300342 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300342 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17597 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17597 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384285 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384285 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384285 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384285 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275514507 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275514507 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11674414609 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11674414609 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201282500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201282500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38949929116 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38949929116 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38949929116 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38949929116 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424067500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424067500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997567998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997567998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421635498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421635498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120352 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120352 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084296 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084296 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091347 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091347 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1329,11 +1365,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.41% # nu system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817851866500 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64172000 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 559556500 0.03% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41715361500 2.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860190956500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1817873983000 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64184500 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 553817500 0.03% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41694992500 2.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860186977500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1387,19 +1423,19 @@ system.cpu.kern.callpal::rti 5104 2.66% 99.64% # nu system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.callpal::total 191963 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29573655500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2713841000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827903452000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29561208000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2704677000 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827921084500 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index d0170b803..14b9e6b0f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,146 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842694 # Number of seconds simulated -sim_ticks 1842693728000 # Number of ticks simulated -final_tick 1842693728000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.843672 # Number of seconds simulated +sim_ticks 1843672389000 # Number of ticks simulated +final_tick 1843672389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239111 # Simulator instruction rate (inst/s) -host_op_rate 239111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5964368765 # Simulator tick rate (ticks/s) -host_mem_usage 346744 # Number of bytes of host memory used -host_seconds 308.95 # Real time elapsed on the host -sim_insts 73873335 # Number of instructions simulated -sim_ops 73873335 # Number of ops (including micro ops) simulated +host_inst_rate 195444 # Simulator instruction rate (inst/s) +host_op_rate 195444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4916161077 # Simulator tick rate (ticks/s) +host_mem_usage 347768 # Number of bytes of host memory used +host_seconds 375.02 # Real time elapsed on the host +sim_insts 73296119 # Number of instructions simulated +sim_ops 73296119 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 489024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20126208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 488384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20120896 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 143680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2232768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 285376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2509376 # Number of bytes read from this memory -system.physmem.bytes_read::total 28438784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 489024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 143680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 285376 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2228608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 281856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2520448 # Number of bytes read from this memory +system.physmem.bytes_read::total 28440384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 488384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 281856 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 918080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7463104 # Number of bytes written to this memory -system.physmem.bytes_written::total 7463104 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7641 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314472 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 7465920 # Number of bytes written to this memory +system.physmem.bytes_written::total 7465920 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314389 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2245 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34887 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39209 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444356 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116611 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116611 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 265385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10922167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1211687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 154869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1361798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15433267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 154869 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4050105 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4050105 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4050105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10922167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1211687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 154869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1361798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19483372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 97691 # Number of read requests accepted -system.physmem.writeReqs 44282 # Number of write requests accepted -system.physmem.readBursts 97691 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44282 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6250944 # Total number of bytes read from DRAM +system.physmem.num_reads::cpu1.inst 2310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34822 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4404 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39382 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444381 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116655 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116655 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 264897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10913488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1438624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1208787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 152877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1367080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15425942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 264897 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80188 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 152877 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 497963 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4049483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4049483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4049483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 264897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10913488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1438624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1208787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 152877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1367080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19475425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98065 # Number of read requests accepted +system.physmem.writeReqs 44647 # Number of write requests accepted +system.physmem.readBursts 98065 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44647 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6274880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1280 # Total number of bytes read from write queue -system.physmem.bytesWritten 2832576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6252224 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2834048 # Total written bytes from the system interface side +system.physmem.bytesWritten 2856000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6276160 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2857408 # Total written bytes from the system interface side system.physmem.servicedByWrQ 20 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6114 # Per bank write bursts -system.physmem.perBankRdBursts::1 5899 # Per bank write bursts -system.physmem.perBankRdBursts::2 6060 # Per bank write bursts -system.physmem.perBankRdBursts::3 6276 # Per bank write bursts -system.physmem.perBankRdBursts::4 5549 # Per bank write bursts -system.physmem.perBankRdBursts::5 6233 # Per bank write bursts -system.physmem.perBankRdBursts::6 6082 # Per bank write bursts -system.physmem.perBankRdBursts::7 6075 # Per bank write bursts -system.physmem.perBankRdBursts::8 6372 # Per bank write bursts -system.physmem.perBankRdBursts::9 6119 # Per bank write bursts -system.physmem.perBankRdBursts::10 6443 # Per bank write bursts -system.physmem.perBankRdBursts::11 5953 # Per bank write bursts -system.physmem.perBankRdBursts::12 5846 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 43 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6107 # Per bank write bursts +system.physmem.perBankRdBursts::1 5922 # Per bank write bursts +system.physmem.perBankRdBursts::2 6220 # Per bank write bursts +system.physmem.perBankRdBursts::3 6321 # Per bank write bursts +system.physmem.perBankRdBursts::4 5635 # Per bank write bursts +system.physmem.perBankRdBursts::5 6235 # Per bank write bursts +system.physmem.perBankRdBursts::6 5931 # Per bank write bursts +system.physmem.perBankRdBursts::7 6044 # Per bank write bursts +system.physmem.perBankRdBursts::8 6533 # Per bank write bursts +system.physmem.perBankRdBursts::9 6108 # Per bank write bursts +system.physmem.perBankRdBursts::10 6507 # Per bank write bursts +system.physmem.perBankRdBursts::11 5966 # Per bank write bursts +system.physmem.perBankRdBursts::12 5866 # Per bank write bursts system.physmem.perBankRdBursts::13 6273 # Per bank write bursts -system.physmem.perBankRdBursts::14 6335 # Per bank write bursts -system.physmem.perBankRdBursts::15 6042 # Per bank write bursts -system.physmem.perBankWrBursts::0 2746 # Per bank write bursts -system.physmem.perBankWrBursts::1 2526 # Per bank write bursts -system.physmem.perBankWrBursts::2 2727 # Per bank write bursts -system.physmem.perBankWrBursts::3 3010 # Per bank write bursts -system.physmem.perBankWrBursts::4 2533 # Per bank write bursts -system.physmem.perBankWrBursts::5 2968 # Per bank write bursts -system.physmem.perBankWrBursts::6 2994 # Per bank write bursts -system.physmem.perBankWrBursts::7 2697 # Per bank write bursts -system.physmem.perBankWrBursts::8 3092 # Per bank write bursts -system.physmem.perBankWrBursts::9 2617 # Per bank write bursts -system.physmem.perBankWrBursts::10 2969 # Per bank write bursts -system.physmem.perBankWrBursts::11 2522 # Per bank write bursts -system.physmem.perBankWrBursts::12 2428 # Per bank write bursts -system.physmem.perBankWrBursts::13 2745 # Per bank write bursts +system.physmem.perBankRdBursts::14 6336 # Per bank write bursts +system.physmem.perBankRdBursts::15 6041 # Per bank write bursts +system.physmem.perBankWrBursts::0 2748 # Per bank write bursts +system.physmem.perBankWrBursts::1 2555 # Per bank write bursts +system.physmem.perBankWrBursts::2 2839 # Per bank write bursts +system.physmem.perBankWrBursts::3 3065 # Per bank write bursts +system.physmem.perBankWrBursts::4 2620 # Per bank write bursts +system.physmem.perBankWrBursts::5 2963 # Per bank write bursts +system.physmem.perBankWrBursts::6 2854 # Per bank write bursts +system.physmem.perBankWrBursts::7 2670 # Per bank write bursts +system.physmem.perBankWrBursts::8 3259 # Per bank write bursts +system.physmem.perBankWrBursts::9 2627 # Per bank write bursts +system.physmem.perBankWrBursts::10 3029 # Per bank write bursts +system.physmem.perBankWrBursts::11 2539 # Per bank write bursts +system.physmem.perBankWrBursts::12 2431 # Per bank write bursts +system.physmem.perBankWrBursts::13 2744 # Per bank write bursts system.physmem.perBankWrBursts::14 2948 # Per bank write bursts -system.physmem.perBankWrBursts::15 2737 # Per bank write bursts +system.physmem.perBankWrBursts::15 2734 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 1841681402500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 1842660063500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 97691 # Read request sizes (log2) +system.physmem.readPktSize::6 98065 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44282 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 495 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44647 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8078 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 373 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -153,13 +153,13 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see @@ -168,376 +168,368 @@ system.physmem.wrQLenPdf::11 35 # Wh system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 15110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 511.250298 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 300.938727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 421.415256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3831 25.35% 25.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2740 18.13% 43.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1074 7.11% 50.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 703 4.65% 55.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 520 3.44% 58.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 360 2.38% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 225 1.49% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 226 1.50% 64.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5431 35.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 15110 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2571 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.985220 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 914.533013 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2569 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 417.545272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 236.447646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 397.078129 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6878 31.45% 31.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4663 21.32% 52.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1715 7.84% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 976 4.46% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 897 4.10% 69.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 495 2.26% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 365 1.67% 73.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 382 1.75% 74.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5497 25.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21868 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.446906 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 907.093650 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2616 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2571 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.214702 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.506808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.396297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 28 1.09% 1.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 8 0.31% 1.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 1 0.04% 1.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 1.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 1.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.04% 1.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.08% 1.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 2 0.08% 1.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 1 0.04% 1.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 1 0.04% 1.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1798 69.93% 71.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 69 2.68% 74.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 74 2.88% 77.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 370 14.39% 91.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 34 1.32% 93.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.74% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 12 0.47% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 7 0.27% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 34 1.32% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 15 0.58% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.19% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.58% 97.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 11 0.43% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 14 0.54% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.16% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 5 0.19% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 6 0.23% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.12% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.04% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.04% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.08% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 2 0.08% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 3 0.12% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.16% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 3 0.12% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 5 0.19% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 2 0.08% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 2 0.08% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 2 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 2 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2571 # Writes before turning the bus around for reads -system.physmem.totQLat 3372876000 # Total ticks spent queuing -system.physmem.totMemAccLat 5050468500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 488355000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1189237500 # Total ticks spent accessing banks -system.physmem.avgQLat 34533.03 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 12175.95 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 2618 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.045455 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.392541 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.534822 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1 25 0.95% 0.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2-3 9 0.34% 1.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-5 2 0.08% 1.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6-7 3 0.11% 1.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-9 2 0.08% 1.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10-11 1 0.04% 1.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14-15 1 0.04% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 1908 72.88% 74.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 472 18.03% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 41 1.57% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 56 2.14% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 26 0.99% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 16 0.61% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 10 0.38% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 14 0.53% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 7 0.27% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.04% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 1 0.04% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 3 0.11% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 4 0.15% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.04% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 11 0.42% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 1 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2618 # Writes before turning the bus around for reads +system.physmem.totQLat 2942753000 # Total ticks spent queuing +system.physmem.totMemAccLat 4781096750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 490225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30014.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51708.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48764.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.13 # Average write queue length when enqueuing -system.physmem.readRowHits 85060 # Number of row buffer hits during reads -system.physmem.writeRowHits 35225 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.22 # Average write queue length when enqueuing +system.physmem.readRowHits 85384 # Number of row buffer hits during reads +system.physmem.writeRowHits 35418 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.55 # Row buffer hit rate for writes -system.physmem.avgGap 12972053.86 # Average gap between requests -system.physmem.pageHitRate 84.74 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19527312 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44337 # Transaction distribution -system.membus.trans_dist::ReadResp 44306 # Transaction distribution -system.membus.trans_dist::WriteReq 3779 # Transaction distribution -system.membus.trans_dist::WriteResp 3779 # Transaction distribution -system.membus.trans_dist::Writeback 44282 # Transaction distribution -system.membus.trans_dist::UpgradeReq 42 # Transaction distribution -system.membus.trans_dist::UpgradeResp 42 # Transaction distribution -system.membus.trans_dist::ReadExReq 56476 # Transaction distribution -system.membus.trans_dist::ReadExResp 56476 # Transaction distribution -system.membus.trans_dist::BadAddressError 31 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13428 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 62 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 202679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 253391 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15748 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6926464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6942212 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9102020 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35972872 # Total data (bytes) -system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12574500 # Layer occupancy (ticks) +system.physmem.writeRowHitRate 79.33 # Row buffer hit rate for writes +system.physmem.avgGap 12911738.77 # Average gap between requests +system.physmem.pageHitRate 84.66 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1768578867000 # Time in different power states +system.physmem.memoryStateTime::REF 61564100000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 13524513000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 19519346 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44419 # Transaction distribution +system.membus.trans_dist::ReadResp 44389 # Transaction distribution +system.membus.trans_dist::WriteReq 3765 # Transaction distribution +system.membus.trans_dist::WriteResp 3765 # Transaction distribution +system.membus.trans_dist::Writeback 44647 # Transaction distribution +system.membus.trans_dist::UpgradeReq 46 # Transaction distribution +system.membus.trans_dist::UpgradeResp 46 # Transaction distribution +system.membus.trans_dist::ReadExReq 56746 # Transaction distribution +system.membus.trans_dist::ReadExResp 56746 # Transaction distribution +system.membus.trans_dist::BadAddressError 30 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13356 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 202958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51481 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 51481 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 254439 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15715 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6940992 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6956707 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2192576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2192576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9149283 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35977232 # Total data (bytes) +system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12506000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 513408250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 516947250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 40000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 37500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 761373958 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 762242703 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 153163000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 155440000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 337430 # number of replacements -system.l2c.tags.tagsinuse 65422.148259 # Cycle average of tags in use -system.l2c.tags.total_refs 2473441 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402593 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.143775 # Average number of references to valid blocks. +system.l2c.tags.replacements 337456 # number of replacements +system.l2c.tags.tagsinuse 65422.465864 # Cycle average of tags in use +system.l2c.tags.total_refs 2473240 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402619 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.142879 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54880.563920 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2458.853214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2711.613848 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 517.416897 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 618.305247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2161.633442 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2073.761691 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.837411 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.037519 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007895 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009435 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032984 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.031643 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998263 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54816.531838 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2443.286445 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2722.487240 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 580.950396 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 624.587700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2109.099829 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2125.522416 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.836434 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.037282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041542 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008865 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009530 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.032433 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998268 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1047 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5588 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2973 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55387 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1026 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5608 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55383 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26153114 # Number of tag accesses -system.l2c.tags.data_accesses 26153114 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 521024 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493028 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 125251 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 84722 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 291154 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239311 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1754490 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 836107 # number of Writeback hits -system.l2c.Writeback_hits::total 836107 # number of Writeback hits +system.l2c.tags.tag_accesses 26151122 # Number of tag accesses +system.l2c.tags.data_accesses 26151122 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 519486 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 493287 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 124779 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 84464 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 292648 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239510 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1754174 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 836240 # number of Writeback hits +system.l2c.Writeback_hits::total 836240 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62277.572254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59199.154841 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -648,14 +640,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254944 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.262765 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694864715000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254944 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078434 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078434 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694865594000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.262765 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078923 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078923 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -669,14 +661,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5375933278 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5375933278 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5385236741 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5385236741 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5385236741 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5385236741 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9418062 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9418062 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5145673458 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5145673458 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5155091520 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5155091520 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5155091520 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5155091520 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -693,56 +685,56 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 129378.448161 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 129378.448161 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 129064.990797 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129064.990797 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 129064.990797 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129064.990797 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 158120 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54439.664740 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54439.664740 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 123836.962312 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123836.962312 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 123549.227561 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123549.227561 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 123549.227561 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123549.227561 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 151978 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11558 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11614 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.680568 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.085759 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4496386278 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4496386278 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 4502100741 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4502100741 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 4502100741 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4502100741 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 266121.346946 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 266121.346946 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 265375.817330 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 265375.817330 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 265375.817330 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 265375.817330 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 17152 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 17152 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 17222 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17222 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17222 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17222 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5777062 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5777062 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4252886458 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4252886458 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4258663520 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4258663520 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4258663520 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4258663520 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.412784 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.412784 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.412750 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.412750 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82529.457143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82529.457143 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247952.801889 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247952.801889 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -760,22 +752,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4928404 # DTB read hits +system.cpu0.dtb.read_hits 4916751 # DTB read hits system.cpu0.dtb.read_misses 6099 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 428233 # DTB read accesses -system.cpu0.dtb.write_hits 3518338 # DTB write hits +system.cpu0.dtb.write_hits 3511411 # DTB write hits system.cpu0.dtb.write_misses 670 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations system.cpu0.dtb.write_accesses 163777 # DTB write accesses -system.cpu0.dtb.data_hits 8446742 # DTB hits +system.cpu0.dtb.data_hits 8428162 # DTB hits system.cpu0.dtb.data_misses 6769 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations system.cpu0.dtb.data_accesses 592010 # DTB accesses -system.cpu0.itb.fetch_hits 2763962 # ITB hits +system.cpu0.itb.fetch_hits 2761691 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2766996 # ITB accesses +system.cpu0.itb.fetch_accesses 2764725 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -788,52 +780,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928692350 # number of cpu cycles simulated +system.cpu0.numCycles 928579533 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 34273964 # Number of instructions committed -system.cpu0.committedOps 34273964 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 32130742 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169948 # Number of float alu accesses -system.cpu0.num_func_calls 813899 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4819398 # number of instructions that are conditional controls -system.cpu0.num_int_insts 32130742 # number of integer instructions -system.cpu0.num_fp_insts 169948 # number of float instructions -system.cpu0.num_int_register_reads 45237353 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23423813 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87792 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89256 # number of times the floating registers were written -system.cpu0.num_mem_refs 8476912 # number of memory refs -system.cpu0.num_load_insts 4949798 # Number of load instructions -system.cpu0.num_store_insts 3527114 # Number of store instructions -system.cpu0.num_idle_cycles 904863863.789935 # Number of idle cycles -system.cpu0.num_busy_cycles 23828486.210065 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025658 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974342 # Percentage of idle cycles -system.cpu0.Branches 5897308 # Number of branches fetched +system.cpu0.committedInsts 33817210 # Number of instructions committed +system.cpu0.committedOps 33817210 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31677975 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169596 # Number of float alu accesses +system.cpu0.num_func_calls 812570 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4683135 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31677975 # number of integer instructions +system.cpu0.num_fp_insts 169596 # number of float instructions +system.cpu0.num_int_register_reads 44495639 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23114141 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87595 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89102 # number of times the floating registers were written +system.cpu0.num_mem_refs 8458293 # number of memory refs +system.cpu0.num_load_insts 4938120 # Number of load instructions +system.cpu0.num_store_insts 3520173 # Number of store instructions +system.cpu0.num_idle_cycles 904460149.841647 # Number of idle cycles +system.cpu0.num_busy_cycles 24119383.158353 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025974 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974026 # Percentage of idle cycles +system.cpu0.Branches 5759211 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1618304 4.78% 4.78% # Class of executed instruction +system.cpu0.op_class::IntAlu 23033604 68.10% 72.88% # Class of executed instruction +system.cpu0.op_class::IntMult 32432 0.10% 72.98% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.98% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12174 0.04% 73.01% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 73.01% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 73.01% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 73.01% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1606 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 73.02% # Class of executed instruction +system.cpu0.op_class::MemRead 5072252 15.00% 88.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 3523323 10.42% 98.43% # Class of executed instruction +system.cpu0.op_class::IprAccess 530494 1.57% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 33824189 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6415 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211374 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74800 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6417 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211389 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182573 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73433 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73433 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148948 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819462416000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38889500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365010500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22826642500 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842692958500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1820445327500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38826000 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365496000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22821970000 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1843671619500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -869,33 +896,33 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175314 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192229 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1907 -system.cpu0.kern.mode_good::user 1737 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches +system.cpu0.kern.callpal::total 192243 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 +system.cpu0.kern.mode_good::user 1739 +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29759204500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2578304000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810355445500 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29786667000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2578002500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1811306945500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -927,458 +954,460 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110509038 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 784786 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 784740 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3779 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3779 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 372271 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution +system.toL2Bus.throughput 110441912 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 785832 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 785787 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3765 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3765 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 372222 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150355 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133459 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 31 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370023 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2216252 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27078976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55338308 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82417284 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203623496 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10816 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2138093500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150766 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133614 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 848294 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370287 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2218581 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27145024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55347363 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82492387 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203607824 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10880 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2138460500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1905810483 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1910550337 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2232783145 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2233740752 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469145 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 3004 # Transaction distribution -system.iobus.trans_dist::ReadResp 3004 # Transaction distribution -system.iobus.trans_dist::WriteReq 20675 # Transaction distribution -system.iobus.trans_dist::WriteResp 20675 # Transaction distribution +system.iobus.throughput 1468369 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2983 # Transaction distribution +system.iobus.trans_dist::ReadResp 2983 # Transaction distribution +system.iobus.trans_dist::WriteReq 20917 # Transaction distribution +system.iobus.trans_dist::WriteResp 20917 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8488 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8382 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2408 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13428 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34444 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 34444 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47800 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4191 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1098540 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2707184 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15715 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1099184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1099184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1114899 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2707192 # Total data (bytes) system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6326000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6246000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1819000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 154493741 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 156921520 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9649000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9591000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17628000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17887000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 951123 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.189701 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 44044625 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 951634 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 46.283156 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10406456250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 252.370031 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 94.623296 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.196374 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.492910 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.184811 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.320696 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998417 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 950608 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.189792 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43374256 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 951119 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.603396 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10403794250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.164377 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 98.345392 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 161.680023 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490555 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.192081 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.315781 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998418 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45964526 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45964526 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 33752258 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8060384 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2231983 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44044625 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33752258 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8060384 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2231983 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44044625 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 33752258 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8060384 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2231983 # number of overall hits -system.cpu0.icache.overall_hits::total 44044625 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 528685 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 127496 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 311915 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 968096 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 528685 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 127496 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 311915 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 968096 # 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Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 130.350177 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.486656 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.258749 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.254590 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 251.446594 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 129.524111 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.027107 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.491107 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.252977 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255912 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63289936 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63289936 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4090319 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1090270 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2387407 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7567996 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3221527 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 836656 # 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number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3672969 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12911741 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7311846 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1926926 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3672969 # number of overall hits -system.cpu0.dcache.overall_hits::total 12911741 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 721875 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 99348 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 531757 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1352980 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 169301 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 44567 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 593518 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 807386 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9749 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2170 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6797 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18716 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63293161 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63293161 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4078776 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1086651 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2400445 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7565872 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3215108 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 831895 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1295006 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5342009 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117088 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19357 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47741 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184186 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126296 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21393 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51592 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7293884 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1918546 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3695451 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12907881 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7293884 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1918546 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3695451 # number of overall hits +system.cpu0.dcache.overall_hits::total 12907881 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 722029 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 99123 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 533441 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1354593 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 169072 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 44217 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 597048 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 810337 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9771 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2167 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6787 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18725 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 891176 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 143915 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1125275 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2160366 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 891176 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 143915 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1125275 # number of overall misses -system.cpu0.dcache.overall_misses::total 2160366 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2256659500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9313664253 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11570323753 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1642839260 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18220741943 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19863581203 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28601250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 101979747 # 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miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.143631 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108870 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069519 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234253 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.143631 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22724.347528 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17489.395946 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8550.218673 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37102.681322 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30140.231626 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 24231.565721 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13181.933549 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15201.230146 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7035.300347 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27095.846576 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24469.046407 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14550.268314 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27095.846576 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24469.046407 # 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average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 573016 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 707 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 17657 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 32.523224 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 218.285714 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 32.452625 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 101 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 836107 # number of writebacks -system.cpu0.dcache.writebacks::total 836107 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6866806739 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10462811979 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 298253500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 315317000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 613570500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 366377000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 431165001 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 797542001 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 664630500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 746482001 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411112501 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083513 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086327 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3590648240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6837055396 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10427703636 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3590648240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6837055396 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10427703636 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296463000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 608356000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 365040500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 428466000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 793506500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 661503500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 740359000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1401862500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083594 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085963 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039385 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050574 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047182 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021659 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100575 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099593 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037257 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000020 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050470 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047127 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021680 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100678 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099820 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037504 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069496 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070997 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032150 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069496 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070997 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032150 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20639.031485 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16811.977655 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17894.118381 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34679.443086 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29666.299104 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31343.317591 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11179.608295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12106.553369 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11840.380177 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032158 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032158 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20648.179535 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16797.792678 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17884.127168 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34917.310989 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29164.763848 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31071.742023 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11181.241347 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12266.948374 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.785808 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24987.007887 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20157.361413 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21591.728791 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24987.007887 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20157.361413 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21591.728791 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1393,22 +1422,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1209129 # DTB read hits +system.cpu1.dtb.read_hits 1205243 # DTB read hits system.cpu1.dtb.read_misses 1367 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations system.cpu1.dtb.read_accesses 142945 # DTB read accesses -system.cpu1.dtb.write_hits 903134 # DTB write hits +system.cpu1.dtb.write_hits 897974 # DTB write hits system.cpu1.dtb.write_misses 185 # DTB write misses system.cpu1.dtb.write_acv 23 # DTB write access violations system.cpu1.dtb.write_accesses 58533 # DTB write accesses -system.cpu1.dtb.data_hits 2112263 # DTB hits +system.cpu1.dtb.data_hits 2103217 # DTB hits system.cpu1.dtb.data_misses 1552 # DTB misses system.cpu1.dtb.data_acv 57 # DTB access violations system.cpu1.dtb.data_accesses 201478 # DTB accesses -system.cpu1.itb.fetch_hits 860790 # ITB hits +system.cpu1.itb.fetch_hits 859888 # ITB hits system.cpu1.itb.fetch_misses 693 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 861483 # ITB accesses +system.cpu1.itb.fetch_accesses 860581 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1421,29 +1450,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953612854 # number of cpu cycles simulated +system.cpu1.numCycles 953622390 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8186270 # Number of instructions committed -system.cpu1.committedOps 8186270 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7639715 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45422 # Number of float alu accesses -system.cpu1.num_func_calls 213980 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1089106 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7639715 # number of integer instructions -system.cpu1.num_fp_insts 45422 # number of float instructions -system.cpu1.num_int_register_reads 10757840 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5542682 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24502 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24833 # number of times the floating registers were written -system.cpu1.num_mem_refs 2119540 # number of memory refs -system.cpu1.num_load_insts 1214044 # Number of load instructions -system.cpu1.num_store_insts 905496 # Number of store instructions -system.cpu1.num_idle_cycles 923510145.865154 # Number of idle cycles -system.cpu1.num_busy_cycles 30102708.134846 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031567 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968433 # Percentage of idle cycles -system.cpu1.Branches 1370105 # Number of branches fetched +system.cpu1.committedInsts 7961300 # Number of instructions committed +system.cpu1.committedOps 7961300 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7416956 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45099 # Number of float alu accesses +system.cpu1.num_func_calls 213358 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1019863 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7416956 # number of integer instructions +system.cpu1.num_fp_insts 45099 # number of float instructions +system.cpu1.num_int_register_reads 10395465 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5394572 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24307 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24707 # number of times the floating registers were written +system.cpu1.num_mem_refs 2110464 # number of memory refs +system.cpu1.num_load_insts 1210140 # Number of load instructions +system.cpu1.num_store_insts 900324 # Number of store instructions +system.cpu1.num_idle_cycles 923192460.103175 # Number of idle cycles +system.cpu1.num_busy_cycles 30429929.896825 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031910 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968090 # Percentage of idle cycles +system.cpu1.Branches 1300058 # Number of branches fetched +system.cpu1.op_class::No_OpClass 413905 5.20% 5.20% # Class of executed instruction +system.cpu1.op_class::IntAlu 5261386 66.07% 71.27% # Class of executed instruction +system.cpu1.op_class::IntMult 8416 0.11% 71.38% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.38% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5003 0.06% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::MemRead 1239389 15.56% 87.01% # Class of executed instruction +system.cpu1.op_class::MemWrite 901545 11.32% 98.34% # Class of executed instruction +system.cpu1.op_class::IprAccess 132455 1.66% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 7962909 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1461,35 +1525,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9158053 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8481927 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 123683 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7604727 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6560922 # Number of BTB hits +system.cpu2.branchPred.lookups 9178120 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8499449 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 123200 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7695654 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6571533 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 86.274261 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 280761 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13305 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.392781 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 282084 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 12342 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3175061 # DTB read hits -system.cpu2.dtb.read_misses 11717 # DTB read misses +system.cpu2.dtb.read_hits 3191151 # DTB read hits +system.cpu2.dtb.read_misses 11650 # DTB read misses system.cpu2.dtb.read_acv 122 # DTB read access violations -system.cpu2.dtb.read_accesses 217137 # DTB read accesses -system.cpu2.dtb.write_hits 2001578 # DTB write hits -system.cpu2.dtb.write_misses 2618 # DTB write misses -system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 82142 # DTB write accesses -system.cpu2.dtb.data_hits 5176639 # DTB hits -system.cpu2.dtb.data_misses 14335 # DTB misses -system.cpu2.dtb.data_acv 228 # DTB access violations -system.cpu2.dtb.data_accesses 299279 # DTB accesses -system.cpu2.itb.fetch_hits 368924 # ITB hits -system.cpu2.itb.fetch_misses 5740 # ITB misses -system.cpu2.itb.fetch_acv 243 # ITB acv -system.cpu2.itb.fetch_accesses 374664 # ITB accesses +system.cpu2.dtb.read_accesses 216295 # DTB read accesses +system.cpu2.dtb.write_hits 2013879 # DTB write hits +system.cpu2.dtb.write_misses 2626 # DTB write misses +system.cpu2.dtb.write_acv 104 # DTB write access violations +system.cpu2.dtb.write_accesses 81955 # DTB write accesses +system.cpu2.dtb.data_hits 5205030 # DTB hits +system.cpu2.dtb.data_misses 14276 # DTB misses +system.cpu2.dtb.data_acv 226 # DTB access violations +system.cpu2.dtb.data_accesses 298250 # DTB accesses +system.cpu2.itb.fetch_hits 370022 # ITB hits +system.cpu2.itb.fetch_misses 5569 # ITB misses +system.cpu2.itb.fetch_acv 246 # ITB acv +system.cpu2.itb.fetch_accesses 375591 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1502,270 +1566,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31279022 # number of cpu cycles simulated +system.cpu2.numCycles 31335688 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8287542 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37055340 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9158053 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6841683 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8878582 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 603474 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9658598 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 9919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63764 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 87901 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 585 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2543899 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 85179 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27382085 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.353269 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.291783 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8331242 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 37157937 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9178120 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6853617 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8899845 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 601293 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9656250 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 62491 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 87858 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 258 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2554389 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 85437 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27441825 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.354062 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.292990 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18503503 67.58% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 267960 0.98% 68.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 427466 1.56% 70.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5038940 18.40% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 758703 2.77% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 165190 0.60% 91.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 190909 0.70% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 425900 1.56% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1603514 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18541980 67.57% 67.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 269924 0.98% 68.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 430608 1.57% 70.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5041958 18.37% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 762355 2.78% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 165901 0.60% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 191104 0.70% 92.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 428586 1.56% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1609409 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27382085 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.292786 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.184671 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8439244 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9737555 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8269995 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 308345 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 381075 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165536 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12831 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36664015 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39751 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 381075 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8796739 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2804819 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5741072 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8142606 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1269911 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35531036 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2469 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 231647 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 446543 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23808302 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44475961 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44419812 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52401 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22020270 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1788032 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 498319 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 58753 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3705896 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3335757 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2091143 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 366529 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 285241 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 33051386 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 616780 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32598005 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 35098 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2143170 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1082478 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 435207 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27382085 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.190487 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.575531 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27441825 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.292897 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.185802 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8480872 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9736053 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8290323 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 308881 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 379812 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165178 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12521 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36770346 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39237 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 379812 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8839767 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2783657 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5759458 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8162466 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1270789 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35635356 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2433 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 230404 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 445807 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23881418 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44614948 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44558512 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52675 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22098169 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1783249 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 500707 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 58904 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3714662 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3352351 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2102718 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 368829 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 261079 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33144056 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 620028 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32694445 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 35243 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2135274 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1079120 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 437376 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27441825 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.191409 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.576872 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15085778 55.09% 55.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3054879 11.16% 66.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1548873 5.66% 71.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5868849 21.43% 93.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 901287 3.29% 96.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 476925 1.74% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 288026 1.05% 99.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 138840 0.51% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18628 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15111094 55.07% 55.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3067205 11.18% 66.24% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1556680 5.67% 71.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5872597 21.40% 93.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 904620 3.30% 96.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 481374 1.75% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 286422 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 142457 0.52% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 19376 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27382085 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27441825 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33655 13.83% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 111431 45.78% 59.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 98340 40.40% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33866 13.68% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112679 45.53% 59.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100956 40.79% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26953534 82.68% 82.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 19910 0.06% 82.75% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8410 0.03% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3301438 10.13% 92.91% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2024047 6.21% 99.12% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 287006 0.88% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 27019317 82.64% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20282 0.06% 82.71% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.71% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8426 0.03% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3318398 10.15% 92.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2035966 6.23% 99.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288396 0.88% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32598005 # Type of FU issued -system.cpu2.iq.rate 1.042168 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 243426 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007468 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92623863 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35700994 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32205742 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 232756 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114085 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110215 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32717888 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 121103 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 185687 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32694445 # Type of FU issued +system.cpu2.iq.rate 1.043361 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 247501 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007570 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92879210 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35788610 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32300559 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234249 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114557 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110717 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32817438 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 122068 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 187489 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 410803 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1083 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3827 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 157383 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 409544 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 984 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3929 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 155635 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4176 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 27619 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4136 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 26287 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 381075 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2023183 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 204607 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34934170 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 220301 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3335757 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2091143 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 547666 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 141469 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2123 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3827 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63090 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.iewSquashCycles 379812 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2011431 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 204809 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35034427 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 220433 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3352351 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2102718 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 550753 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 142349 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2108 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3929 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63003 # Number of branches that were predicted taken incorrectly system.cpu2.iew.predictedNotTakenIncorrect 127121 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 190211 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32442083 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3195032 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 155922 # Number of squashed instructions skipped in execute +system.cpu2.iew.branchMispredicts 190124 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32537756 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3211080 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 156689 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1266004 # number of nop insts executed -system.cpu2.iew.exec_refs 5203645 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7597485 # Number of branches executed -system.cpu2.iew.exec_stores 2008613 # Number of stores executed -system.cpu2.iew.exec_rate 1.037183 # Inst execution rate -system.cpu2.iew.wb_sent 32348485 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32315957 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18839799 # num instructions producing a value -system.cpu2.iew.wb_consumers 22025525 # num instructions consuming a value +system.cpu2.iew.exec_nop 1270343 # number of nop insts executed +system.cpu2.iew.exec_refs 5232018 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7610407 # Number of branches executed +system.cpu2.iew.exec_stores 2020938 # Number of stores executed +system.cpu2.iew.exec_rate 1.038361 # Inst execution rate +system.cpu2.iew.wb_sent 32444193 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32411276 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18891849 # num instructions producing a value +system.cpu2.iew.wb_consumers 22089477 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.033151 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.855362 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.034325 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.855242 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2315429 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 181573 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 175784 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27001010 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.206363 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.845727 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2305077 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182652 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 175963 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 27062013 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.207707 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.849174 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16087817 59.58% 59.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2320535 8.59% 68.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1221811 4.53% 72.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5612171 20.79% 93.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 500601 1.85% 95.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 184383 0.68% 96.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 174610 0.65% 96.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 192284 0.71% 97.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 706798 2.62% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16121128 59.57% 59.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2330838 8.61% 68.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1224813 4.53% 72.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5615394 20.75% 93.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 503174 1.86% 95.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185895 0.69% 96.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 176248 0.65% 96.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179513 0.66% 97.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 725010 2.68% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27001010 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32573021 # Number of instructions committed -system.cpu2.commit.committedOps 32573021 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 27062013 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32682976 # Number of instructions committed +system.cpu2.commit.committedOps 32682976 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4858714 # Number of memory references committed -system.cpu2.commit.loads 2924954 # Number of loads committed -system.cpu2.commit.membars 63567 # Number of memory barriers committed -system.cpu2.commit.branches 7451291 # Number of branches committed -system.cpu2.commit.fp_insts 109021 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31134232 # Number of committed integer instructions. -system.cpu2.commit.function_calls 227850 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 706798 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4889890 # Number of memory references committed +system.cpu2.commit.loads 2942807 # Number of loads committed +system.cpu2.commit.membars 63964 # Number of memory barriers committed +system.cpu2.commit.branches 7465437 # Number of branches committed +system.cpu2.commit.fp_insts 109562 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31237309 # Number of committed integer instructions. +system.cpu2.commit.function_calls 229028 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1167807 3.57% 3.57% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 26241804 80.29% 83.87% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 19886 0.06% 83.93% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 8426 0.03% 83.95% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.95% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.95% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.95% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.96% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3006771 9.20% 93.16% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 1948666 5.96% 99.12% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 288396 0.88% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 32682976 # Class of committed instruction +system.cpu2.commit.bw_lim_events 725010 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 61108801 # The number of ROB reads -system.cpu2.rob.rob_writes 70157468 # The number of ROB writes -system.cpu2.timesIdled 244589 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3896937 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746488839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31413101 # Number of Instructions Simulated -system.cpu2.committedOps 31413101 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 31413101 # Number of Instructions Simulated -system.cpu2.cpi 0.995732 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.995732 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.004287 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.004287 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42678646 # number of integer regfile reads -system.cpu2.int_regfile_writes 22701958 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67399 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67744 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5400058 # number of misc regfile reads -system.cpu2.misc_regfile_writes 256035 # number of misc regfile writes +system.cpu2.rob.rob_reads 61251181 # The number of ROB reads +system.cpu2.rob.rob_writes 70355425 # The number of ROB writes +system.cpu2.timesIdled 245354 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3893863 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1748379581 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31517609 # Number of Instructions Simulated +system.cpu2.committedOps 31517609 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31517609 # Number of Instructions Simulated +system.cpu2.cpi 0.994228 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.994228 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.005806 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.005806 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42812311 # number of integer regfile reads +system.cpu2.int_regfile_writes 22772429 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67678 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67966 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5406368 # number of misc regfile reads +system.cpu2.misc_regfile_writes 257490 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 5f9799ffe..2c9e78fdf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526170 # Number of seconds simulated -sim_ticks 2526169857500 # Number of ticks simulated -final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526192 # Number of seconds simulated +sim_ticks 2526192217500 # Number of ticks simulated +final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46796 # Simulator instruction rate (inst/s) -host_op_rate 60213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1960134913 # Simulator tick rate (ticks/s) -host_mem_usage 468616 # Number of bytes of host memory used -host_seconds 1288.77 # Real time elapsed on the host -sim_insts 60309637 # Number of instructions simulated -sim_ops 77601213 # Number of ops (including micro ops) simulated +host_inst_rate 45758 # Simulator instruction rate (inst/s) +host_op_rate 58877 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1916680323 # Simulator tick rate (ticks/s) +host_mem_usage 469072 # Number of bytes of host memory used +host_seconds 1318.00 # Real time elapsed on the host +sim_insts 60309034 # Number of instructions simulated +sim_ops 77600502 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096868 # Number of read requests accepted -system.physmem.writeReqs 813159 # Number of write requests accepted -system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue -system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943297 # Per bank write bursts -system.physmem.perBankRdBursts::1 937033 # Per bank write bursts -system.physmem.perBankRdBursts::2 936962 # Per bank write bursts -system.physmem.perBankRdBursts::3 936535 # Per bank write bursts -system.physmem.perBankRdBursts::4 942693 # Per bank write bursts -system.physmem.perBankRdBursts::5 936569 # Per bank write bursts -system.physmem.perBankRdBursts::6 936319 # Per bank write bursts -system.physmem.perBankRdBursts::7 936043 # Per bank write bursts -system.physmem.perBankRdBursts::8 943596 # Per bank write bursts -system.physmem.perBankRdBursts::9 936992 # Per bank write bursts -system.physmem.perBankRdBursts::10 936414 # Per bank write bursts -system.physmem.perBankRdBursts::11 935912 # Per bank write bursts -system.physmem.perBankRdBursts::12 943556 # Per bank write bursts -system.physmem.perBankRdBursts::13 937007 # Per bank write bursts -system.physmem.perBankRdBursts::14 937039 # Per bank write bursts -system.physmem.perBankRdBursts::15 936676 # Per bank write bursts -system.physmem.perBankWrBursts::0 6606 # Per bank write bursts -system.physmem.perBankWrBursts::1 6375 # Per bank write bursts -system.physmem.perBankWrBursts::2 6521 # Per bank write bursts -system.physmem.perBankWrBursts::3 6552 # Per bank write bursts -system.physmem.perBankWrBursts::4 6461 # Per bank write bursts -system.physmem.perBankWrBursts::5 6711 # Per bank write bursts -system.physmem.perBankWrBursts::6 6720 # Per bank write bursts -system.physmem.perBankWrBursts::7 6668 # Per bank write bursts -system.physmem.perBankWrBursts::8 7045 # Per bank write bursts -system.physmem.perBankWrBursts::9 6826 # Per bank write bursts -system.physmem.perBankWrBursts::10 6497 # Per bank write bursts -system.physmem.perBankWrBursts::11 6136 # Per bank write bursts -system.physmem.perBankWrBursts::12 7072 # Per bank write bursts -system.physmem.perBankWrBursts::13 6672 # Per bank write bursts -system.physmem.perBankWrBursts::14 6956 # Per bank write bursts -system.physmem.perBankWrBursts::15 6819 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096864 # Number of read requests accepted +system.physmem.writeReqs 813148 # Number of write requests accepted +system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue +system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943480 # Per bank write bursts +system.physmem.perBankRdBursts::1 937980 # Per bank write bursts +system.physmem.perBankRdBursts::2 937559 # Per bank write bursts +system.physmem.perBankRdBursts::3 937528 # Per bank write bursts +system.physmem.perBankRdBursts::4 943087 # Per bank write bursts +system.physmem.perBankRdBursts::5 937982 # Per bank write bursts +system.physmem.perBankRdBursts::6 937070 # Per bank write bursts +system.physmem.perBankRdBursts::7 936990 # Per bank write bursts +system.physmem.perBankRdBursts::8 943982 # Per bank write bursts +system.physmem.perBankRdBursts::9 938303 # Per bank write bursts +system.physmem.perBankRdBursts::10 937119 # Per bank write bursts +system.physmem.perBankRdBursts::11 936407 # Per bank write bursts +system.physmem.perBankRdBursts::12 943924 # Per bank write bursts +system.physmem.perBankRdBursts::13 938214 # Per bank write bursts +system.physmem.perBankRdBursts::14 937241 # Per bank write bursts +system.physmem.perBankRdBursts::15 937211 # Per bank write bursts +system.physmem.perBankWrBursts::0 6601 # Per bank write bursts +system.physmem.perBankWrBursts::1 6388 # Per bank write bursts +system.physmem.perBankWrBursts::2 6528 # Per bank write bursts +system.physmem.perBankWrBursts::3 6554 # Per bank write bursts +system.physmem.perBankWrBursts::4 6464 # Per bank write bursts +system.physmem.perBankWrBursts::5 6726 # Per bank write bursts +system.physmem.perBankWrBursts::6 6713 # Per bank write bursts +system.physmem.perBankWrBursts::7 6652 # Per bank write bursts +system.physmem.perBankWrBursts::8 7031 # Per bank write bursts +system.physmem.perBankWrBursts::9 6803 # Per bank write bursts +system.physmem.perBankWrBursts::10 6461 # Per bank write bursts +system.physmem.perBankWrBursts::11 6104 # Per bank write bursts +system.physmem.perBankWrBursts::12 7064 # Per bank write bursts +system.physmem.perBankWrBursts::13 6684 # Per bank write bursts +system.physmem.perBankWrBursts::14 6965 # Per bank write bursts +system.physmem.perBankWrBursts::15 6836 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526168741500 # Total gap between requests +system.physmem.totGap 2526191083500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154622 # Read request sizes (log2) +system.physmem.readPktSize::6 154618 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1044851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 985737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 947948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 933228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 933834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2717841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2709185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3589675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 37568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 34960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 32201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 30053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59130 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,47 +159,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -208,67 +208,50 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads -system.physmem.totQLat 571195583500 # Total ticks spent queuing -system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers -system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks -system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads +system.physmem.totQLat 389908010000 # Total ticks spent queuing +system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -276,15 +259,19 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.99 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing -system.physmem.readRowHits 14041195 # Number of row buffer hits during reads -system.physmem.writeRowHits 91389 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes -system.physmem.avgGap 158778.41 # Average gap between requests -system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing +system.physmem.readRowHits 14044000 # Number of row buffer hits during reads +system.physmem.writeRowHits 91096 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes +system.physmem.avgGap 158779.96 # Average gap between requests +system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states +system.physmem.memoryStateTime::REF 84354920000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -297,50 +284,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54878638 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149508 # Transaction distribution -system.membus.trans_dist::ReadResp 16149508 # Transaction distribution +system.membus.throughput 54877773 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149486 # Transaction distribution +system.membus.trans_dist::ReadResp 16149486 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59141 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59130 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution +system.membus.trans_dist::ReadExReq 131451 # Transaction distribution +system.membus.trans_dist::ReadExResp 131451 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138632762 # Total data (bytes) +system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138631802 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -348,7 +335,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48266001 # Throughput (bytes/s) +system.iobus.throughput 48265574 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution @@ -458,18 +445,18 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14755327 # Number of BP lookups -system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits +system.cpu.branchPred.lookups 14753661 # Number of BP lookups +system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -493,9 +480,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987589 # DTB read hits -system.cpu.checker.dtb.read_misses 7306 # DTB read misses -system.cpu.checker.dtb.write_hits 11227681 # DTB write hits +system.cpu.checker.dtb.read_hits 14987453 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11227597 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -506,12 +493,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994895 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229872 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994761 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229788 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215270 # DTB hits -system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26224767 # DTB accesses +system.cpu.checker.dtb.hits 26215050 # DTB hits +system.cpu.checker.dtb.misses 9499 # DTB misses +system.cpu.checker.dtb.accesses 26224549 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -533,7 +520,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61483612 # ITB inst hits +system.cpu.checker.itb.inst_hits 61483008 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -550,11 +537,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61488085 # ITB inst accesses -system.cpu.checker.itb.hits 61483612 # DTB hits +system.cpu.checker.itb.inst_accesses 61487481 # ITB inst accesses +system.cpu.checker.itb.hits 61483008 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61488085 # DTB accesses -system.cpu.checker.numCycles 77887007 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61487481 # DTB accesses +system.cpu.checker.numCycles 77886295 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -580,25 +567,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51187284 # DTB read hits -system.cpu.dtb.read_misses 65383 # DTB read misses -system.cpu.dtb.write_hits 11703682 # DTB write hits -system.cpu.dtb.write_misses 15916 # DTB write misses +system.cpu.dtb.read_hits 51183231 # DTB read hits +system.cpu.dtb.read_misses 65223 # DTB read misses +system.cpu.dtb.write_hits 11700953 # DTB write hits +system.cpu.dtb.write_misses 15725 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252667 # DTB read accesses -system.cpu.dtb.write_accesses 11719598 # DTB write accesses +system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51248454 # DTB read accesses +system.cpu.dtb.write_accesses 11716678 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62890966 # DTB hits -system.cpu.dtb.misses 81299 # DTB misses -system.cpu.dtb.accesses 62972265 # DTB accesses +system.cpu.dtb.hits 62884184 # DTB hits +system.cpu.dtb.misses 80948 # DTB misses +system.cpu.dtb.accesses 62965132 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -620,8 +607,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11527099 # ITB inst hits -system.cpu.itb.inst_misses 11249 # ITB inst misses +system.cpu.itb.inst_hits 11525561 # ITB inst hits +system.cpu.itb.inst_misses 11159 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -630,113 +617,113 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11538348 # ITB inst accesses -system.cpu.itb.hits 11527099 # DTB hits -system.cpu.itb.misses 11249 # DTB misses -system.cpu.itb.accesses 11538348 # DTB accesses -system.cpu.numCycles 477119451 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11536720 # ITB inst accesses +system.cpu.itb.hits 11525561 # DTB hits +system.cpu.itb.misses 11159 # DTB misses +system.cpu.itb.accesses 11536720 # DTB accesses +system.cpu.numCycles 477128882 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available @@ -765,13 +752,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued @@ -784,11 +771,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued @@ -797,404 +784,440 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued -system.cpu.iq.rate 0.257655 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued +system.cpu.iq.rate 0.257622 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221278 # number of nop insts executed -system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed -system.cpu.iew.exec_branches 11821235 # Number of branches executed -system.cpu.iew.exec_stores 12215513 # Number of stores executed -system.cpu.iew.exec_rate 0.253301 # Inst execution rate -system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47029089 # num instructions producing a value -system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value +system.cpu.iew.exec_nop 222849 # number of nop insts executed +system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed +system.cpu.iew.exec_branches 11822089 # Number of branches executed +system.cpu.iew.exec_stores 12212847 # Number of stores executed +system.cpu.iew.exec_rate 0.253272 # Inst execution rate +system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47017508 # num instructions producing a value +system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60460018 # Number of instructions committed -system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459415 # Number of instructions committed +system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386851 # Number of memory references committed -system.cpu.commit.loads 15654790 # Number of loads committed -system.cpu.commit.membars 403577 # Number of memory barriers committed -system.cpu.commit.branches 10306380 # Number of branches committed +system.cpu.commit.refs 27386618 # Number of memory references committed +system.cpu.commit.loads 15654647 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 10306311 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191623 # Number of committed integer instructions. -system.cpu.commit.function_calls 991253 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. +system.cpu.commit.function_calls 991245 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction +system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242979782 # The number of ROB reads -system.cpu.rob.rob_writes 196005989 # The number of ROB writes -system.cpu.timesIdled 1777234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575137230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309637 # Number of Instructions Simulated -system.cpu.committedOps 77601213 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60309637 # Number of Instructions Simulated -system.cpu.cpi 7.911164 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911164 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126404 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126404 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548698002 # number of integer regfile reads -system.cpu.int_regfile_writes 87552826 # number of integer regfile writes -system.cpu.fp_regfile_reads 8408 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 268236665 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173235 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58867266 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2659080 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2659079 # Transaction distribution +system.cpu.rob.rob_reads 243007370 # The number of ROB reads +system.cpu.rob.rob_writes 195993770 # The number of ROB writes +system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309034 # Number of Instructions Simulated +system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60309034 # Number of Instructions Simulated +system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548643018 # number of integer regfile reads +system.cpu.int_regfile_writes 87545925 # number of integer regfile writes +system.cpu.fp_regfile_reads 8332 # number of floating regfile reads +system.cpu.fp_regfile_writes 2902 # number of floating regfile writes +system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2959 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2975 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246069 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796085 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129069 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62744960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85505466 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148505990 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148505990 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202724 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129185667 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474638965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2549207556 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20255489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75530794 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980897 # number of replacements -system.cpu.icache.tags.tagsinuse 511.570903 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10462766 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981409 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.660964 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6958078250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.570903 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999162 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999162 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 981488 # number of replacements +system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12504958 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12504958 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10462766 # 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miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13451.548479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13451.548479 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7798 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits +system.cpu.icache.overall_hits::total 10460581 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses +system.cpu.icache.overall_misses::total 1061360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 344 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.668605 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981450 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981450 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587546773 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11587546773 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587546773 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11587546773 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587546773 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11587546773 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9345000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9345000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9345000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9345000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085169 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085169 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085169 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79319 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79319 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79319 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79319 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79319 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79319 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982041 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8965500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8965500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8965500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8965500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085232 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085232 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085232 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64391 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51374.630920 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1887139 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129786 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.540390 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490832751500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 31.305745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000374 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8179.061871 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6245.594773 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563334 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000478 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64387 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51384.068329 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1888247 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129781 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.549487 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2490875317000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 37.347999 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.789418 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6233.237161 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563624 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000570 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095300 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783915 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65372 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3052 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6933 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54996 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997498 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18788998 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18788998 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53598 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10246 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967912 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 386978 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1418734 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607635 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607635 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 46 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112878 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112878 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53598 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10246 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026850 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015999 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984454 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984454 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541275 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6434999 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17456853479 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17456853479 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6434999 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1315,168 +1338,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # 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Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101537487 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9982812336 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 139744433579 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185287000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185287000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 245503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149727245915 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149727245915 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 149727245915 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 149727245915 # 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number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24719289 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050794 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050794 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289800 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289800 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052732 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000065 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000065 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149631 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149631 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149631 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149631 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40480.214513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40480.214513 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31777 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 23524 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.050436 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 85.854015 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits +system.cpu.dcache.overall_hits::total 21015072 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses +system.cpu.dcache.overall_misses::total 3699212 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607635 # number of writebacks -system.cpu.dcache.writebacks::total 607635 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350728 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350728 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713476 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713476 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1349 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064204 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064204 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064204 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064204 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385631 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385631 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248941 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248941 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12178 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12178 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634572 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634572 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634572 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967633608 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967633608 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11307381788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11307381788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145644250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145644250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 213497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 213497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16275015396 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16275015396 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16275015396 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16275015396 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26867769000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26867769000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025671 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks +system.cpu.dcache.writebacks::total 607456 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1500,16 +1523,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 7d13ac1ec..97a804211 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.605649 # Number of seconds simulated -sim_ticks 2605649343000 # Number of ticks simulated -final_tick 2605649343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.605644 # Number of seconds simulated +sim_ticks 2605643988500 # Number of ticks simulated +final_tick 2605643988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57764 # Simulator instruction rate (inst/s) -host_op_rate 74374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2397402056 # Simulator tick rate (ticks/s) -host_mem_usage 474764 # Number of bytes of host memory used -host_seconds 1086.86 # Real time elapsed on the host -sim_insts 62781325 # Number of instructions simulated -sim_ops 80834116 # Number of ops (including micro ops) simulated +host_inst_rate 56388 # Simulator instruction rate (inst/s) +host_op_rate 72604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2339801960 # Simulator tick rate (ticks/s) +host_mem_usage 475216 # Number of bytes of host memory used +host_seconds 1113.62 # Real time elapsed on the host +sim_insts 62794806 # Number of instructions simulated +sim_ops 80853196 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 383680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5448188 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 438080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4125688 # Number of bytes read from this memory -system.physmem.bytes_read::total 131508276 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 383680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 438080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4229952 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 394240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4377212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 429184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5246712 # Number of bytes read from this memory +system.physmem.bytes_read::total 131559796 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 429184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 823424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4275584 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7259088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7304720 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 5995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 85202 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6845 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 64492 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301383 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66093 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82008 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302188 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66806 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823377 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46479979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 824090 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46480075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 147249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2090914 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 168127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1583363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50470443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 147249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 168127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1623377 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1679896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2013595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50490319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151302 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316016 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1640893 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156002 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2785904 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1623377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46479979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2803422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1640893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46480075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 147249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2097438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 168127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2739365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53256346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15301383 # Number of read requests accepted -system.physmem.writeReqs 823377 # Number of write requests accepted -system.physmem.readBursts 15301383 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823377 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 973889408 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5399104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7284800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131508276 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7259088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 84361 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709522 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14082 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956098 # Per bank write bursts -system.physmem.perBankRdBursts::1 950020 # Per bank write bursts -system.physmem.perBankRdBursts::2 950090 # Per bank write bursts -system.physmem.perBankRdBursts::3 949980 # Per bank write bursts -system.physmem.perBankRdBursts::4 956223 # Per bank write bursts -system.physmem.perBankRdBursts::5 949119 # Per bank write bursts -system.physmem.perBankRdBursts::6 948884 # Per bank write bursts -system.physmem.perBankRdBursts::7 948711 # Per bank write bursts -system.physmem.perBankRdBursts::8 956337 # Per bank write bursts -system.physmem.perBankRdBursts::9 950158 # Per bank write bursts -system.physmem.perBankRdBursts::10 948908 # Per bank write bursts -system.physmem.perBankRdBursts::11 948900 # Per bank write bursts -system.physmem.perBankRdBursts::12 955944 # Per bank write bursts -system.physmem.perBankRdBursts::13 949314 # Per bank write bursts -system.physmem.perBankRdBursts::14 949393 # Per bank write bursts -system.physmem.perBankRdBursts::15 948943 # Per bank write bursts -system.physmem.perBankWrBursts::0 7119 # Per bank write bursts -system.physmem.perBankWrBursts::1 7037 # Per bank write bursts -system.physmem.perBankWrBursts::2 7071 # Per bank write bursts -system.physmem.perBankWrBursts::3 7168 # Per bank write bursts -system.physmem.perBankWrBursts::4 7696 # Per bank write bursts -system.physmem.perBankWrBursts::5 7220 # Per bank write bursts -system.physmem.perBankWrBursts::6 7070 # Per bank write bursts -system.physmem.perBankWrBursts::7 6913 # Per bank write bursts -system.physmem.perBankWrBursts::8 7415 # Per bank write bursts -system.physmem.perBankWrBursts::9 7415 # Per bank write bursts -system.physmem.perBankWrBursts::10 6887 # Per bank write bursts -system.physmem.perBankWrBursts::11 6788 # Per bank write bursts -system.physmem.perBankWrBursts::12 7071 # Per bank write bursts -system.physmem.perBankWrBursts::13 6872 # Per bank write bursts -system.physmem.perBankWrBursts::14 7197 # Per bank write bursts -system.physmem.perBankWrBursts::15 6886 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 151302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1686421 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3169600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53293741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302188 # Number of read requests accepted +system.physmem.writeReqs 824090 # Number of write requests accepted +system.physmem.readBursts 15302188 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 824090 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 974626176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4713856 # Total number of bytes read from write queue +system.physmem.bytesWritten 7328128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131559796 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7304720 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 73654 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709569 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14159 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956238 # Per bank write bursts +system.physmem.perBankRdBursts::1 951013 # Per bank write bursts +system.physmem.perBankRdBursts::2 950196 # Per bank write bursts +system.physmem.perBankRdBursts::3 950464 # Per bank write bursts +system.physmem.perBankRdBursts::4 956634 # Per bank write bursts +system.physmem.perBankRdBursts::5 950822 # Per bank write bursts +system.physmem.perBankRdBursts::6 949869 # Per bank write bursts +system.physmem.perBankRdBursts::7 949811 # Per bank write bursts +system.physmem.perBankRdBursts::8 956681 # Per bank write bursts +system.physmem.perBankRdBursts::9 951277 # Per bank write bursts +system.physmem.perBankRdBursts::10 949961 # Per bank write bursts +system.physmem.perBankRdBursts::11 949024 # Per bank write bursts +system.physmem.perBankRdBursts::12 956331 # Per bank write bursts +system.physmem.perBankRdBursts::13 950586 # Per bank write bursts +system.physmem.perBankRdBursts::14 950041 # Per bank write bursts +system.physmem.perBankRdBursts::15 949586 # Per bank write bursts +system.physmem.perBankWrBursts::0 7062 # Per bank write bursts +system.physmem.perBankWrBursts::1 6963 # Per bank write bursts +system.physmem.perBankWrBursts::2 7126 # Per bank write bursts +system.physmem.perBankWrBursts::3 7116 # Per bank write bursts +system.physmem.perBankWrBursts::4 7811 # Per bank write bursts +system.physmem.perBankWrBursts::5 7409 # Per bank write bursts +system.physmem.perBankWrBursts::6 7013 # Per bank write bursts +system.physmem.perBankWrBursts::7 7004 # Per bank write bursts +system.physmem.perBankWrBursts::8 7458 # Per bank write bursts +system.physmem.perBankWrBursts::9 7561 # Per bank write bursts +system.physmem.perBankWrBursts::10 6914 # Per bank write bursts +system.physmem.perBankWrBursts::11 6583 # Per bank write bursts +system.physmem.perBankWrBursts::12 7179 # Per bank write bursts +system.physmem.perBankWrBursts::13 7101 # Per bank write bursts +system.physmem.perBankWrBursts::14 7219 # Per bank write bursts +system.physmem.perBankWrBursts::15 6983 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2605648115500 # Total gap between requests +system.physmem.totGap 2605642823000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 109 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 162458 # Read request sizes (log2) +system.physmem.readPktSize::6 163263 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66093 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1062706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 998935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 959607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 945820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 946342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2754714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2746120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3637640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 38272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 34182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 34523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 32360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 30630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 22253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66806 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1074226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1009957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 967065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1078396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 970167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1034458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2664402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2566961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3342237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 136100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 116220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 107345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -176,47 +176,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -225,85 +225,74 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 965097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1010.691593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 992.992769 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 104.599429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5712 0.59% 0.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4413 0.46% 1.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2116 0.22% 1.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1499 0.16% 1.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1121 0.12% 1.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 815 0.08% 1.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 661 0.07% 1.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 851 0.09% 1.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 947909 98.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 965097 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5955 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2555.332662 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 92927.024688 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 5949 99.90% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 2 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5955 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.114190 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.218740 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.431880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3971 66.68% 66.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 19 0.32% 67.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 175 2.94% 69.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1141 19.16% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 44 0.74% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.32% 90.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.35% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.17% 90.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.10% 90.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 90.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.07% 90.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 90.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.02% 90.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.02% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 90.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 146 2.45% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 311 5.22% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 13 0.22% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 13 0.22% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 16 0.27% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 22 0.37% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 9 0.15% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 4 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5955 # Writes before turning the bus around for reads -system.physmem.totQLat 579051796250 # Total ticks spent queuing -system.physmem.totMemAccLat 683715373750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76085110000 # Total ticks spent in databus transfers -system.physmem.totBankLat 28578467500 # Total ticks spent accessing banks -system.physmem.avgQLat 38052.90 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1878.06 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 1012463 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 969.866853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 900.909804 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 207.662919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24967 2.47% 2.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21104 2.08% 4.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8681 0.86% 5.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2506 0.25% 5.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2720 0.27% 5.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2029 0.20% 6.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8638 0.85% 6.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1014 0.10% 7.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 940804 92.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1012463 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6706 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2270.880853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 84552.226363 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6700 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.88358e+06-3.14573e+06 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5.24288e+06-5.50502e+06 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6706 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6706 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.074560 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.020748 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.396636 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3829 57.10% 57.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 48 0.72% 57.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1779 26.53% 84.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 878 13.09% 97.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 53 0.79% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 31 0.46% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 34 0.51% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 40 0.60% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 12 0.18% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6706 # Writes before turning the bus around for reads +system.physmem.totQLat 395588666000 # Total ticks spent queuing +system.physmem.totMemAccLat 681123678500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76142670000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25976.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44930.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 373.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.47 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44726.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.04 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.94 # Data bus utilization in percentage system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.53 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14231578 # Number of row buffer hits during reads -system.physmem.writeRowHits 96073 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.38 # Row buffer hit rate for writes -system.physmem.avgGap 161592.99 # Average gap between requests -system.physmem.pageHitRate 93.46 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.22 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing +system.physmem.readRowHits 14234195 # Number of row buffer hits during reads +system.physmem.writeRowHits 96378 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.16 # Row buffer hit rate for writes +system.physmem.avgGap 161577.45 # Average gap between requests +system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2260536385250 # Time in different power states +system.physmem.memoryStateTime::REF 87007960000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 258093332250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -322,300 +311,299 @@ system.realview.nvmem.bw_inst_read::total 172 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54186995 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352581 # Transaction distribution -system.membus.trans_dist::ReadResp 16352581 # Transaction distribution -system.membus.trans_dist::WriteReq 769189 # Transaction distribution -system.membus.trans_dist::WriteResp 769189 # Transaction distribution -system.membus.trans_dist::Writeback 66093 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35785 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18271 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14082 # Transaction distribution -system.membus.trans_dist::ReadExReq 137406 # Transaction distribution -system.membus.trans_dist::ReadExResp 137045 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384396 # Packet count per connected master and slave (bytes) +system.membus.throughput 54224369 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352672 # Transaction distribution +system.membus.trans_dist::ReadResp 16352672 # Transaction distribution +system.membus.trans_dist::WriteReq 769183 # Transaction distribution +system.membus.trans_dist::WriteResp 769183 # Transaction distribution +system.membus.trans_dist::Writeback 66806 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35949 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18292 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14159 # Transaction distribution +system.membus.trans_dist::ReadExReq 138125 # Transaction distribution +system.membus.trans_dist::ReadExResp 137746 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13840 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1974294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4374590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4377155 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34652222 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392725 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34654787 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17656836 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20081781 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17753988 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20178873 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141192309 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141192309 # Total data (bytes) +system.membus.tot_pkt_size::total 141289401 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141289401 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1488242000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487962500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11807000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11808000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1796000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17652470999 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17659548997 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4843604815 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4847870095 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37703679634 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37379122644 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 72164 # number of replacements -system.l2c.tags.tagsinuse 53016.131060 # Cycle average of tags in use -system.l2c.tags.total_refs 1876966 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137304 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.670148 # Average number of references to valid blocks. +system.l2c.tags.replacements 72974 # number of replacements +system.l2c.tags.tagsinuse 53023.948009 # Cycle average of tags in use +system.l2c.tags.total_refs 1873330 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 138152 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.559920 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37702.356015 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 7.377107 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000365 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4186.473555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2957.675740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.683393 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4035.806716 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4115.758170 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.575292 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000113 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37706.296895 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.412172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000364 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4169.126027 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2962.597547 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.621110 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4061.748879 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4107.145016 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.575352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063881 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045131 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.062801 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808962 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063616 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045206 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000177 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061977 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.062670 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.809081 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65136 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8263 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53454 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65174 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3154 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9081 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52631 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.993896 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18860644 # Number of tag accesses -system.l2c.tags.data_accesses 18860644 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 23595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5577 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 409210 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169724 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 33221 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5824 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 593571 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 196649 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1437371 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 582434 # number of Writeback hits -system.l2c.Writeback_hits::total 582434 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 737 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1202 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1939 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 203 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 149 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 352 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 52746 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54725 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107471 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 23595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5577 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 409210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 222470 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 33221 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5824 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 593571 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 251374 # number of demand (read+write) hits -system.l2c.demand_hits::total 1544842 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 23595 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5577 # number of overall hits -system.l2c.overall_hits::cpu0.inst 409210 # number of overall hits -system.l2c.overall_hits::cpu0.data 222470 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 33221 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5824 # number of overall hits -system.l2c.overall_hits::cpu1.inst 593571 # number of overall hits -system.l2c.overall_hits::cpu1.data 251374 # number of overall hits -system.l2c.overall_hits::total 1544842 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 16 # number of ReadReq misses +system.l2c.tags.occ_task_id_percent::1024 0.994476 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18850449 # Number of tag accesses +system.l2c.tags.data_accesses 18850449 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 22712 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 393676 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165723 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 33196 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5802 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 607870 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201576 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1434996 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 583128 # number of Writeback hits +system.l2c.Writeback_hits::total 583128 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1123 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1850 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 207 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 158 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47567 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59393 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22712 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4441 # 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average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.796889 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.668510 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10014.033898 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.541596 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10009.476401 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57729.104367 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65666.928730 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62074.834549 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -806,62 +794,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58721934 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2742702 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2742701 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769189 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769189 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 582434 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35028 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18623 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53651 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259025 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259025 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831060 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2542800 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15169 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56113 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1201524 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 3348368 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 16175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 77084 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8088293 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26573504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 39205457 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 22316 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94444 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38427456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 43600612 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148080029 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148080029 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4928740 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4918843977 # Layer occupancy (ticks) +system.toL2Bus.throughput 58718575 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2740966 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2740965 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 583128 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35123 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53780 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259272 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259272 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800244 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13760 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56807 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1229764 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15635 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8085518 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25589824 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34686241 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17772 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39333696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48239320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148113805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148113805 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4885896 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4921313376 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872939397 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1803473389 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2324821689 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1514355955 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9616940 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9338456 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 32646700 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34226949 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2706859206 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2770248418 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2444231662 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 3257977460 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 10370957 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 9851958 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 44131664 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 42643941 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47398263 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322928 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322928 # Transaction distribution -system.iobus.trans_dist::WriteReq 8086 # Transaction distribution -system.iobus.trans_dist::WriteResp 8086 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8852 # Packet count per connected master and slave (bytes) +system.iobus.throughput 47398342 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution +system.iobus.trans_dist::WriteReq 8083 # Transaction distribution +system.iobus.trans_dist::WriteResp 8083 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8836 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -883,12 +871,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384396 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32662028 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40729 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17704 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 32661996 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17672 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -910,14 +898,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392725 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503253 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21724000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503205 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4432000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4424000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -963,19 +951,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376310000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37739478366 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu0.branchPred.lookups 6715650 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5214611 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 297509 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4164563 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3259277 # Number of BTB hits +system.iobus.respLayer1.occupancy 38174483356 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.branchPred.lookups 6117114 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4670626 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296157 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3842728 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2949969 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 78.262161 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 722080 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28659 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.767572 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 683314 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28361 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -999,25 +987,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 30314049 # DTB read hits -system.cpu0.dtb.read_misses 28675 # DTB read misses -system.cpu0.dtb.write_hits 5612279 # DTB write hits -system.cpu0.dtb.write_misses 4120 # DTB write misses +system.cpu0.dtb.read_hits 8969403 # DTB read hits +system.cpu0.dtb.read_misses 29343 # DTB read misses +system.cpu0.dtb.write_hits 5210557 # DTB write hits +system.cpu0.dtb.write_misses 5731 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1934 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1024 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1050 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 30342724 # DTB read accesses -system.cpu0.dtb.write_accesses 5616399 # DTB write accesses +system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8998746 # DTB read accesses +system.cpu0.dtb.write_accesses 5216288 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 35926328 # DTB hits -system.cpu0.dtb.misses 32795 # DTB misses -system.cpu0.dtb.accesses 35959123 # DTB accesses +system.cpu0.dtb.hits 14179960 # DTB hits +system.cpu0.dtb.misses 35074 # DTB misses +system.cpu0.dtb.accesses 14215034 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1039,8 +1027,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 4601822 # ITB inst hits -system.cpu0.itb.inst_misses 5333 # ITB inst misses +system.cpu0.itb.inst_hits 4277605 # ITB inst hits +system.cpu0.itb.inst_misses 5145 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1049,544 +1037,584 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1359 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1531 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1426 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4607155 # ITB inst accesses -system.cpu0.itb.hits 4601822 # DTB hits -system.cpu0.itb.misses 5333 # DTB misses -system.cpu0.itb.accesses 4607155 # DTB accesses -system.cpu0.numCycles 298758505 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4282750 # ITB inst accesses +system.cpu0.itb.hits 4277605 # DTB hits +system.cpu0.itb.misses 5145 # DTB misses +system.cpu0.itb.accesses 4282750 # DTB accesses +system.cpu0.numCycles 70248238 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 12556555 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 35349888 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6715650 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3981357 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 8343175 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1485021 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 73668 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 62934939 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 43768 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1358657 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 326 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4600051 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 159705 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 86381436 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.526874 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.794731 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11931842 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32451975 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6117114 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3633283 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7612739 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1460869 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60951 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20309232 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 6063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46682 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1377400 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 299 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4276074 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 156796 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2089 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42393450 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988978 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.370199 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 78045507 90.35% 90.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 675063 0.78% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 847046 0.98% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 783211 0.91% 93.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1013921 1.17% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 572462 0.66% 94.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 659407 0.76% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 359642 0.42% 96.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3425177 3.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34788183 82.06% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 572054 1.35% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 825907 1.95% 85.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686377 1.62% 86.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 779180 1.84% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 565083 1.33% 90.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 677221 1.60% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 357838 0.84% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3141607 7.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 86381436 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.022479 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.118323 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13622847 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 63604727 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7412124 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 742617 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 999121 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 974392 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66422 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 44125799 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 218867 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 999121 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14363042 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 26099881 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 33731509 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 7356267 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3831616 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 43013829 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 321 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 629927 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2476084 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 94 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 43352703 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 198103413 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 178854732 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5396 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34867311 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8485392 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 643580 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 598183 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 7434614 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8769305 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6206849 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1218439 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1296110 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 40716219 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1133567 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61584494 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 78672 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6465857 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13399979 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 300001 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 86381436 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.712937 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.420531 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42393450 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.087079 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461961 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12487890 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21493629 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6874468 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 552722 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 984741 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 950951 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64626 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40558878 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212020 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 984741 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13064503 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5883311 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13498743 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6804692 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2157460 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39446559 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 311 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 442642 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1180293 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 145 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39856275 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 180582545 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 163877057 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4135 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31488132 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8368142 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 460013 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 416638 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5509006 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7758217 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5771757 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1123661 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1193308 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37348678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 906063 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37718806 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82800 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6312476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13233696 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257258 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42393450 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.889732 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.506737 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 63313818 73.30% 73.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8088215 9.36% 82.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3310781 3.83% 86.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2721682 3.15% 89.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7122842 8.25% 97.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1038791 1.20% 99.09% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 532976 0.62% 99.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 192156 0.22% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 60175 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27027469 63.75% 63.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5904750 13.93% 77.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3167008 7.47% 85.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2470651 5.83% 90.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2117188 4.99% 95.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 941206 2.22% 98.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 520081 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 187957 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 57140 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 86381436 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42393450 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26298 0.46% 0.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.01% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5416194 95.59% 96.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 223026 3.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26875 2.51% 2.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 458 0.04% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 836202 77.98% 80.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 208765 19.47% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15923 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 24790294 40.25% 40.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50109 0.08% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 806 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 30788025 49.99% 90.36% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5939307 9.64% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22694630 60.17% 60.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47979 0.13% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9430195 25.00% 85.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5530734 14.66% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61584494 # Type of FU issued -system.cpu0.iq.rate 0.206135 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 5665970 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.092003 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 215315704 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 48322789 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 38367249 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11842 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6226 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5089 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67228191 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6350 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 325894 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37718806 # Type of FU issued +system.cpu0.iq.rate 0.536936 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1072300 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028429 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119012569 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44575137 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34852276 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8350 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38772197 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4358 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316382 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1367932 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2587 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13911 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 563678 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1375838 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2694 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13105 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 538991 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 22510150 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5899 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149907 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5937 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 999121 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 20412775 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 272757 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 41952562 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83343 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8769305 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6206849 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 796686 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 50755 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3694 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13911 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 151015 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 116203 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267218 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61206576 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 30649831 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 377918 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 984741 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4273547 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 99764 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38372810 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83727 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7758217 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5771757 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 578717 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40350 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3282 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13105 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151036 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117828 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 268864 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37337135 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9286340 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 381671 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 102776 # number of nop insts executed -system.cpu0.iew.exec_refs 36543183 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5550332 # Number of branches executed -system.cpu0.iew.exec_stores 5893352 # Number of stores executed -system.cpu0.iew.exec_rate 0.204870 # Inst execution rate -system.cpu0.iew.wb_sent 61019070 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 38372338 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 20674113 # num instructions producing a value -system.cpu0.iew.wb_consumers 38142518 # num instructions consuming a value +system.cpu0.iew.exec_nop 118069 # number of nop insts executed +system.cpu0.iew.exec_refs 14769450 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4962843 # Number of branches executed +system.cpu0.iew.exec_stores 5483110 # Number of stores executed +system.cpu0.iew.exec_rate 0.531503 # Inst execution rate +system.cpu0.iew.wb_sent 37142523 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34856145 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18592748 # num instructions producing a value +system.cpu0.iew.wb_consumers 35683758 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.128439 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.542023 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496185 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.521042 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6195680 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 833566 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232261 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 85382315 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.412432 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.299663 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6125993 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 648805 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232656 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41408709 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.767702 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.726975 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 71262923 83.46% 83.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7740236 9.07% 92.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2004904 2.35% 94.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1114217 1.30% 96.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 806577 0.94% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 503262 0.59% 97.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 497454 0.58% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 227564 0.27% 98.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1225178 1.43% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29445863 71.11% 71.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5939620 14.34% 85.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1940870 4.69% 90.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1013361 2.45% 92.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 759448 1.83% 94.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 515426 1.24% 95.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 408347 0.99% 96.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 223076 0.54% 97.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1162698 2.81% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 85382315 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 26835114 # Number of instructions committed -system.cpu0.commit.committedOps 35214409 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41408709 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24071577 # Number of instructions committed +system.cpu0.commit.committedOps 31789563 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13044544 # Number of memory references committed -system.cpu0.commit.loads 7401373 # Number of loads committed -system.cpu0.commit.membars 236456 # Number of memory barriers committed -system.cpu0.commit.branches 4918099 # Number of branches committed -system.cpu0.commit.fp_insts 5062 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 31243705 # Number of committed integer instructions. -system.cpu0.commit.function_calls 531450 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1225178 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11615145 # Number of memory references committed +system.cpu0.commit.loads 6382379 # Number of loads committed +system.cpu0.commit.membars 231812 # Number of memory barriers committed +system.cpu0.commit.branches 4351457 # Number of branches committed +system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 28135168 # Number of committed integer instructions. +system.cpu0.commit.function_calls 498959 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 20133954 63.34% 63.34% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39784 0.13% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6382379 20.08% 83.54% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5232766 16.46% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 31789563 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1162698 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124649951 # The number of ROB reads -system.cpu0.rob.rob_writes 83821170 # The number of ROB writes -system.cpu0.timesIdled 1018994 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 212377069 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 4911896145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 26765511 # Number of Instructions Simulated -system.cpu0.committedOps 35144806 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 26765511 # Number of Instructions Simulated -system.cpu0.cpi 11.162070 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 11.162070 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.089589 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.089589 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 273626518 # number of integer regfile reads -system.cpu0.int_regfile_writes 37917674 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4695 # number of floating regfile reads -system.cpu0.fp_regfile_writes 986 # number of floating regfile writes -system.cpu0.misc_regfile_reads 148789996 # number of misc regfile reads -system.cpu0.misc_regfile_writes 678362 # number of misc regfile writes -system.cpu0.icache.tags.replacements 415188 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.568306 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 4152259 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 415700 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.988595 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7103550250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.568306 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999157 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999157 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 77292791 # The number of ROB reads +system.cpu0.rob.rob_writes 76817595 # The number of ROB writes +system.cpu0.timesIdled 365665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27854788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5140997105 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23990835 # Number of Instructions Simulated +system.cpu0.committedOps 31708821 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23990835 # Number of Instructions Simulated +system.cpu0.cpi 2.928128 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.928128 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341515 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341515 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174285855 # number of integer regfile reads +system.cpu0.int_regfile_writes 34604955 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3294 # number of floating regfile reads +system.cpu0.fp_regfile_writes 912 # number of floating regfile writes +system.cpu0.misc_regfile_reads 79299010 # number of misc regfile reads +system.cpu0.misc_regfile_writes 500883 # number of misc regfile writes +system.cpu0.icache.tags.replacements 399739 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.543627 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3844274 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 400251 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.604658 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7097393250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.543627 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999109 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999109 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 5015647 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 5015647 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 4152259 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 4152259 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 4152259 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 4152259 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 4152259 # number of overall hits -system.cpu0.icache.overall_hits::total 4152259 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 447663 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 447663 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 447663 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 447663 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 447663 # number of overall misses -system.cpu0.icache.overall_misses::total 447663 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6158685000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6158685000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6158685000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6158685000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6158685000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6158685000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4599922 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4599922 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4599922 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4599922 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4599922 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4599922 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097320 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.097320 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097320 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.097320 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097320 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.097320 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13757.413501 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13757.413501 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13757.413501 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13757.413501 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4464 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 4676219 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 4676219 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 3844274 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3844274 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3844274 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3844274 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3844274 # number of overall hits +system.cpu0.icache.overall_hits::total 3844274 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 431668 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 431668 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 431668 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 431668 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 431668 # number of overall misses +system.cpu0.icache.overall_misses::total 431668 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5966691765 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5966691765 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5966691765 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5966691765 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5966691765 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5966691765 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4275942 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4275942 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4275942 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4275942 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4275942 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4275942 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100953 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100953 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100953 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100953 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100953 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100953 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13822.409271 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13822.409271 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13822.409271 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13822.409271 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4149 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.730539 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.122093 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31938 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31938 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31938 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31938 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31938 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31938 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 415725 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 415725 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 415725 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 415725 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 415725 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 415725 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5022987594 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5022987594 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5022987594 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5022987594 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5022987594 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5022987594 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9487250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9487250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9487250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9487250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090377 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090377 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090377 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12082.476623 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31390 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31390 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31390 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31390 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31390 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31390 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400278 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 400278 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 400278 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 400278 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 400278 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 400278 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4859637603 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4859637603 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4859637603 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4859637603 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4859637603 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4859637603 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9490000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9490000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9490000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 9490000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093612 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093612 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093612 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12140.656251 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 298882 # number of replacements -system.cpu0.dcache.tags.tagsinuse 483.456705 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10027143 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 299266 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.505787 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 44230250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.456705 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944251 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.944251 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 48541082 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 48541082 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6144970 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6144970 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3563655 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3563655 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 144672 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 144672 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142233 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 142233 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9708625 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9708625 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9708625 # number of overall hits -system.cpu0.dcache.overall_hits::total 9708625 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 393929 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 393929 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1644577 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1644577 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9244 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9244 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7866 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7866 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2038506 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2038506 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2038506 # number of overall misses -system.cpu0.dcache.overall_misses::total 2038506 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5542234631 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5542234631 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82471404032 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 82471404032 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94602484 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 94602484 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50293768 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50293768 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 88013638663 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 88013638663 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 88013638663 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 88013638663 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6538899 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6538899 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5208232 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5208232 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153916 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 153916 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150099 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 150099 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11747131 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11747131 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11747131 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11747131 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.060244 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.060244 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.315765 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.315765 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060059 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060059 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052405 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052405 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173532 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.173532 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.173532 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.173532 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.120656 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.120656 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50147.487185 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50147.487185 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10233.933795 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10233.933795 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6393.817442 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6393.817442 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43175.560270 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43175.560270 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10878 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5936 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 678 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.044248 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 51.172414 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 275002 # number of replacements +system.cpu0.dcache.tags.tagsinuse 479.873805 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9429051 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 275514 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.223491 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43985250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.873805 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937254 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.937254 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 45805638 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 45805638 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5875796 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5875796 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3229179 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3229179 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139566 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139566 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137212 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137212 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9104975 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9104975 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9104975 # number of overall hits +system.cpu0.dcache.overall_hits::total 9104975 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392540 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392540 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582550 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582550 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8878 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8878 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7747 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7747 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1975090 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1975090 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1975090 # number of overall misses +system.cpu0.dcache.overall_misses::total 1975090 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5503316358 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5503316358 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80403947306 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 80403947306 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91149731 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 91149731 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49845761 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 49845761 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85907263664 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85907263664 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85907263664 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85907263664 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6268336 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6268336 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4811729 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4811729 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148444 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148444 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144959 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144959 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11080065 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11080065 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11080065 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11080065 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062623 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062623 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328894 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.328894 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059807 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059807 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053443 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053443 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178256 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178256 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178256 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178256 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14019.759408 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14019.759408 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50806.576289 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50806.576289 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10266.921717 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10266.921717 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6434.201756 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6434.201756 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43495.366623 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43495.366623 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9513 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 7748 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 587 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.206133 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 56.970588 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 278268 # number of writebacks -system.cpu0.dcache.writebacks::total 278268 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201648 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 201648 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493557 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1493557 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 632 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 632 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1695205 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1695205 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1695205 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1695205 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 192281 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 192281 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 151020 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 151020 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8612 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8612 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70543016 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34562232 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34562232 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 255347 # number of writebacks +system.cpu0.dcache.writebacks::total 255347 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203411 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203411 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451593 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1451593 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655004 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1655004 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655004 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1655004 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189129 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189129 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130957 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130957 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8410 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8410 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7747 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7747 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320086 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320086 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320086 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320086 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2397985131 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2397985131 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338215866 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338215866 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69513767 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69513767 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34349239 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34349239 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9119572267 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9119572267 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9119572267 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9119572267 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 120538982283 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 120538982283 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1232045382 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1232045382 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 121771027665 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 121771027665 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029406 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029406 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028996 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028996 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055953 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055953 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052405 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052405 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029224 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029224 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12681.087923 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12681.087923 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44240.762813 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44240.762813 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8191.246633 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.246633 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4393.876430 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4393.876430 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7736200997 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7736200997 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7736200997 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7736200997 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434640527 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434640527 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206086382 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206086382 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640726909 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640726909 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030172 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030172 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027216 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027216 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056654 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056654 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053443 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053443 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028888 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028888 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12679.098028 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12679.098028 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40763.119696 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40763.119696 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8265.608442 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8265.608442 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4433.876210 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4433.876210 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1594,15 +1622,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8689698 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7082612 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 415349 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5570453 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4730059 # Number of BTB hits +system.cpu1.branchPred.lookups 9293378 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7631598 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 415998 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5889507 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5046361 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.913363 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 759549 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43595 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.683929 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 797302 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43622 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1626,25 +1654,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 21626734 # DTB read hits -system.cpu1.dtb.read_misses 38691 # DTB read misses -system.cpu1.dtb.write_hits 6575784 # DTB write hits -system.cpu1.dtb.write_misses 12298 # DTB write misses +system.cpu1.dtb.read_hits 42971422 # DTB read hits +system.cpu1.dtb.read_misses 37905 # DTB read misses +system.cpu1.dtb.write_hits 6976449 # DTB write hits +system.cpu1.dtb.write_misses 10883 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1712 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3023 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2893 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 296 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 600 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 21665425 # DTB read accesses -system.cpu1.dtb.write_accesses 6588082 # DTB write accesses +system.cpu1.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43009327 # DTB read accesses +system.cpu1.dtb.write_accesses 6987332 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 28202518 # DTB hits -system.cpu1.dtb.misses 50989 # DTB misses -system.cpu1.dtb.accesses 28253507 # DTB accesses +system.cpu1.dtb.hits 49947871 # DTB hits +system.cpu1.dtb.misses 48788 # DTB misses +system.cpu1.dtb.accesses 49996659 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1666,8 +1694,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7394895 # ITB inst hits -system.cpu1.itb.inst_misses 5860 # ITB inst misses +system.cpu1.itb.inst_hits 7719787 # ITB inst hits +system.cpu1.itb.inst_misses 5634 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1676,546 +1704,575 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1207 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1503 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1538 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7400755 # ITB inst accesses -system.cpu1.itb.hits 7394895 # DTB hits -system.cpu1.itb.misses 5860 # DTB misses -system.cpu1.itb.accesses 7400755 # DTB accesses -system.cpu1.numCycles 185247782 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7725421 # ITB inst accesses +system.cpu1.itb.hits 7719787 # DTB hits +system.cpu1.itb.misses 5634 # DTB misses +system.cpu1.itb.accesses 7725421 # DTB accesses +system.cpu1.numCycles 413693823 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18767441 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 58413381 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8689698 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5489608 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 12630025 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3326163 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 70879 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 38401480 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5864 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 46813 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1518730 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7393189 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 549179 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3073 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 73717325 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.969397 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.351920 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19372544 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61318271 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9293378 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5843663 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13362487 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3346253 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69736 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 80999073 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42062 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1494344 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7717920 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 551887 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2996 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 117635394 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.638004 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.959630 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 61095045 82.88% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 712004 0.97% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939814 1.27% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1614257 2.19% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1180828 1.60% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 579149 0.79% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1971485 2.67% 92.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 418985 0.57% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5205758 7.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 104280280 88.65% 88.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 814710 0.69% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 961160 0.82% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1713171 1.46% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1415249 1.20% 92.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 586962 0.50% 93.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1954597 1.66% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 422243 0.36% 95.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5487022 4.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 73717325 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.046909 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.315326 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 19856835 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 39689565 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11370888 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 621997 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2178040 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1113164 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 99384 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 67504859 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 329486 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2178040 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 20884497 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 13732674 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 23091492 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 10921071 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2909551 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 63553177 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 150 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 495727 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 1775459 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 454 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 67243012 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 295535307 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 271726361 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4962 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 47019288 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20223723 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 581683 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 523637 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6484055 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11835207 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7683859 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 982260 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1485488 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 58475771 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 951228 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 65019700 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 99369 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13400197 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36106127 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236520 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 73717325 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.882014 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.585621 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 117635394 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022464 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.148221 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20963679 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 81759193 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11913295 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 809519 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2189708 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1137363 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100954 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71089276 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 336011 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2189708 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22156707 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33902507 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 43325786 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11473545 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4587141 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67137864 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 137 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 682095 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3075433 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1010 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70763032 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 313108743 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 286757803 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6623 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50416422 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20346610 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 765987 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 705836 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8420477 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12843204 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8115826 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1055497 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1512633 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 61850161 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1179252 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88896986 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93979 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13548762 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36246660 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 279849 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 117635394 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.755699 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.498688 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 50542925 68.56% 68.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7121407 9.66% 78.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4031042 5.47% 83.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3362905 4.56% 88.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 5367239 7.28% 95.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1894348 2.57% 98.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1048738 1.42% 99.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 275398 0.37% 99.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73323 0.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86772303 73.76% 73.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9298113 7.90% 81.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4175598 3.55% 85.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3594840 3.06% 88.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10374006 8.82% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1994938 1.70% 98.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1065613 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 281099 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 78884 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 73717325 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 117635394 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 33869 1.02% 1.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.03% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 2994112 90.44% 91.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 281623 8.51% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32152 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 986 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7573471 95.70% 96.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 306947 3.88% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12895 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 35505233 54.61% 54.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59031 0.09% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1556 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 22501549 34.61% 89.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6939400 10.67% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14268 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37614404 42.31% 42.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43858329 49.34% 91.74% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7347048 8.26% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 65019700 # Type of FU issued -system.cpu1.iq.rate 0.350988 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 3310600 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.050917 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 207206368 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 72837982 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 50730101 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11167 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5978 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5058 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 68311542 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5863 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 343642 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88896986 # Type of FU issued +system.cpu1.iq.rate 0.214886 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7913556 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089019 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 303469985 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 76586992 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54255274 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15534 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8108 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6874 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96788024 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8250 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 355713 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2877094 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3994 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17361 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1094953 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2862172 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4122 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17485 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1111950 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 11606945 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675630 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965671 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675853 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2178040 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 10295917 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 191116 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 59545170 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 114100 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11835207 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7683859 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 664311 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 56460 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4454 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17361 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 204103 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 160517 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 364620 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 63283569 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 21990431 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1736131 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2189708 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26386476 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 363440 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63133555 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 115239 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12843204 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8115826 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 883054 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 66097 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4286 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17485 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 204520 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 158639 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 363159 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87164207 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43354058 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1732779 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 118171 # number of nop insts executed -system.cpu1.iew.exec_refs 28863200 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6787528 # Number of branches executed -system.cpu1.iew.exec_stores 6872769 # Number of stores executed -system.cpu1.iew.exec_rate 0.341616 # Inst execution rate -system.cpu1.iew.wb_sent 62514610 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 50735159 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 28199774 # num instructions producing a value -system.cpu1.iew.wb_consumers 51433237 # num instructions consuming a value +system.cpu1.iew.exec_nop 104142 # number of nop insts executed +system.cpu1.iew.exec_refs 50636612 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7376811 # Number of branches executed +system.cpu1.iew.exec_stores 7282554 # Number of stores executed +system.cpu1.iew.exec_rate 0.210697 # Inst execution rate +system.cpu1.iew.wb_sent 86400335 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54262148 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30287291 # num instructions producing a value +system.cpu1.iew.wb_consumers 53873069 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.273877 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.548279 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131165 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.562197 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13377367 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 714708 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 317605 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 71539285 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.639790 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.672504 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13443206 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899403 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 316783 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 115445686 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.426296 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.378874 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 55665383 77.81% 77.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7811223 10.92% 88.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2101815 2.94% 91.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1189986 1.66% 93.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 946066 1.32% 94.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 613597 0.86% 95.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 912617 1.28% 96.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531458 0.74% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1767140 2.47% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97421932 84.39% 84.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9594899 8.31% 92.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2172227 1.88% 94.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1301741 1.13% 95.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 988993 0.86% 96.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 587152 0.51% 97.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1008803 0.87% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 534624 0.46% 98.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1835315 1.59% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 71539285 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 36096592 # Number of instructions committed -system.cpu1.commit.committedOps 45770088 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 115445686 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38873610 # Number of instructions committed +system.cpu1.commit.committedOps 49214014 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 15547019 # Number of memory references committed -system.cpu1.commit.loads 8958113 # Number of loads committed -system.cpu1.commit.membars 191016 # Number of memory barriers committed -system.cpu1.commit.branches 5856523 # Number of branches committed -system.cpu1.commit.fp_insts 5022 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 40800338 # Number of committed integer instructions. -system.cpu1.commit.function_calls 520894 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1767140 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16984908 # Number of memory references committed +system.cpu1.commit.loads 9981032 # Number of loads committed +system.cpu1.commit.membars 195536 # Number of memory barriers committed +system.cpu1.commit.branches 6424997 # Number of branches committed +system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43926362 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553376 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 32169137 65.37% 65.37% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 58263 0.12% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9981032 20.28% 85.77% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 7003876 14.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 49214014 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1835315 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 127901171 # The number of ROB reads -system.cpu1.rob.rob_writes 120555711 # The number of ROB writes -system.cpu1.timesIdled 777241 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 111530457 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5026003021 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 36015814 # Number of Instructions Simulated -system.cpu1.committedOps 45689310 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 36015814 # Number of Instructions Simulated -system.cpu1.cpi 5.143512 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 5.143512 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.194420 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.194420 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 292255401 # number of integer regfile reads -system.cpu1.int_regfile_writes 53047565 # number of integer regfile writes -system.cpu1.fp_regfile_reads 3797 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1766 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133121160 # number of misc regfile reads -system.cpu1.misc_regfile_writes 545345 # number of misc regfile writes -system.cpu1.icache.tags.replacements 600500 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.750005 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6745926 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 601012 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.224278 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74974413000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.750005 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974121 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974121 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 175201017 # The number of ROB reads +system.cpu1.rob.rob_writes 127586843 # The number of ROB writes +system.cpu1.timesIdled 1428644 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 296058429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4796946974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38803971 # Number of Instructions Simulated +system.cpu1.committedOps 49144375 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38803971 # Number of Instructions Simulated +system.cpu1.cpi 10.661121 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.661121 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093799 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093799 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391634066 # number of integer regfile reads +system.cpu1.int_regfile_writes 56368159 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5144 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes +system.cpu1.misc_regfile_reads 202762353 # number of misc regfile reads +system.cpu1.misc_regfile_writes 723009 # number of misc regfile writes +system.cpu1.icache.tags.replacements 614589 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.738252 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7056364 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 615101 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.471879 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74953244500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.738252 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974098 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974098 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 7994182 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 7994182 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6745926 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6745926 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6745926 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6745926 # 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number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8801556837 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8801556837 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7393137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7393137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7393137 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7393137 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7393137 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7393137 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.087542 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.087542 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.087542 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.087542 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.087542 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.087542 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13599.207734 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13599.207734 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13599.207734 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13599.207734 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3107 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 341 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 199 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.613065 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 341 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 8332995 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 8332995 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7056364 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7056364 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7056364 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7056364 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7056364 # number of overall hits +system.cpu1.icache.overall_hits::total 7056364 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661505 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661505 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661505 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661505 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661505 # number of overall misses +system.cpu1.icache.overall_misses::total 661505 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8964922762 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8964922762 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8964922762 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8964922762 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8964922762 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8964922762 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7717869 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7717869 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7717869 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7717869 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7717869 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7717869 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085711 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.085711 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085711 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.085711 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085711 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.085711 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13552.312926 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13552.312926 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13552.312926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13552.312926 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3582 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 212 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.896226 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46165 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46165 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46165 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46165 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46165 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46165 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 601046 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 601046 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 601046 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 601046 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 601046 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 601046 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7178040035 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7178040035 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7178040035 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7178040035 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7178040035 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7178040035 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3605250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3605250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3605250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3605250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.081298 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.081298 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.081298 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11942.580160 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46379 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46379 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46379 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46379 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46379 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46379 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615126 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 615126 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 615126 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 615126 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 615126 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 615126 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7320744820 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7320744820 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7320744820 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7320744820 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7320744820 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7320744820 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3847250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3847250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3847250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3847250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079702 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.079702 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.079702 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11901.211817 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 339082 # number of replacements -system.cpu1.dcache.tags.tagsinuse 482.965075 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12423447 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 339594 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.583235 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 71024759250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.965075 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943291 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.943291 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 57544569 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 57544569 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 8247311 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8247311 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3935666 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3935666 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94453 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 94453 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 92037 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 92037 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12182977 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12182977 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12182977 # number of overall hits -system.cpu1.dcache.overall_hits::total 12182977 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 400036 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 400036 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1501327 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1501327 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13642 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13642 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10758 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10758 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1901363 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1901363 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1901363 # number of overall misses -system.cpu1.dcache.overall_misses::total 1901363 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6052529769 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6052529769 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75305143416 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 75305143416 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124772740 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 124772740 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57202570 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 57202570 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 81357673185 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 81357673185 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 81357673185 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 81357673185 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8647347 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8647347 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5436993 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5436993 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 108095 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 108095 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102795 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102795 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14084340 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14084340 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14084340 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14084340 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046261 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046261 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.276132 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.276132 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126204 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126204 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104655 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104655 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134998 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134998 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134998 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134998 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15129.962726 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15129.962726 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50159.054900 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 50159.054900 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9146.220496 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9146.220496 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5317.212307 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5317.212307 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 42789.132420 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 42789.132420 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 27478 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17677 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 363297 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.117445 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 13019165 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 363645 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.801853 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 71011321250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.117445 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949448 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949448 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 60291027 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 60291027 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 8513196 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8513196 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4271027 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4271027 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99804 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 99804 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97081 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 97081 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12784223 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12784223 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12784223 # number of overall hits +system.cpu1.dcache.overall_hits::total 12784223 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 403038 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 403038 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1566274 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1566274 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14187 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14187 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10911 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10911 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1969312 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1969312 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1969312 # number of overall misses +system.cpu1.dcache.overall_misses::total 1969312 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6108097691 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6108097691 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 77891341203 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 77891341203 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131130743 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131130743 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58206088 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 58206088 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 83999438894 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 83999438894 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 83999438894 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 83999438894 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8916234 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8916234 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837301 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5837301 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113991 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 113991 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107992 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 107992 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14753535 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14753535 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14753535 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14753535 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045203 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045203 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268322 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.268322 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124457 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124457 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101035 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101035 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133481 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.133481 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133481 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.133481 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15155.140932 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15155.140932 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 49730.341692 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 49730.341692 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9243.021287 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9243.021287 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.624507 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.624507 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 42654.205577 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 42654.205577 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29593 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18156 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 175 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.517669 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 101.011429 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.003042 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 103.748571 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 304166 # number of writebacks -system.cpu1.dcache.writebacks::total 304166 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172051 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 172051 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1358464 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1358464 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1244 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1244 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1530515 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1530515 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1530515 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1530515 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227985 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 227985 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 142863 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 142863 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12398 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12398 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10758 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10758 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 370848 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 370848 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 370848 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 370848 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2835218608 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2835218608 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5632564954 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5632564954 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86730259 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86730259 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35684430 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35684430 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8467783562 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8467783562 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8467783562 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8467783562 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 62130810008 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 62130810008 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25850406364 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25850406364 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 87981216372 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 87981216372 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026365 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026365 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026276 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026276 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.114695 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.114695 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104655 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104655 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026331 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026331 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12435.987490 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12435.987490 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39426.338198 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39426.338198 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6995.504033 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6995.504033 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3317.013385 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3317.013385 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327781 # number of writebacks +system.cpu1.dcache.writebacks::total 327781 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171674 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171674 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1403027 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1403027 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1467 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1467 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574701 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1574701 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574701 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1574701 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231364 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231364 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163247 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163247 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10911 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10911 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394611 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394611 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394611 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394611 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2878773157 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2878773157 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7001686259 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7001686259 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89753005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89753005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36382912 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36382912 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9880459416 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9880459416 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9880459416 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9880459416 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231749012 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231749012 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25869959988 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25869959988 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195101709000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195101709000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025949 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025949 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027966 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027966 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111588 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111588 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101035 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101035 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026747 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026747 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12442.614914 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12442.614914 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42890.137393 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42890.137393 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7056.053852 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7056.053852 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3334.516726 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3334.516726 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2239,18 +2296,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1737834287366 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1737834287366 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1735350782356 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1735350782356 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 45161 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42636 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 47884 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50408 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 0d3018ad7..d345e80f2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526170 # Number of seconds simulated -sim_ticks 2526169857500 # Number of ticks simulated -final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526192 # Number of seconds simulated +sim_ticks 2526192217500 # Number of ticks simulated +final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58326 # Simulator instruction rate (inst/s) -host_op_rate 75048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2443063970 # Simulator tick rate (ticks/s) -host_mem_usage 467448 # Number of bytes of host memory used -host_seconds 1034.02 # Real time elapsed on the host -sim_insts 60309637 # Number of instructions simulated -sim_ops 77601213 # Number of ops (including micro ops) simulated +host_inst_rate 56578 # Simulator instruction rate (inst/s) +host_op_rate 72800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2369913329 # Simulator tick rate (ticks/s) +host_mem_usage 467016 # Number of bytes of host memory used +host_seconds 1065.94 # Real time elapsed on the host +sim_insts 60309034 # Number of instructions simulated +sim_ops 77600502 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096868 # Number of read requests accepted -system.physmem.writeReqs 813159 # Number of write requests accepted -system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue -system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943297 # Per bank write bursts -system.physmem.perBankRdBursts::1 937033 # Per bank write bursts -system.physmem.perBankRdBursts::2 936962 # Per bank write bursts -system.physmem.perBankRdBursts::3 936535 # Per bank write bursts -system.physmem.perBankRdBursts::4 942693 # Per bank write bursts -system.physmem.perBankRdBursts::5 936569 # Per bank write bursts -system.physmem.perBankRdBursts::6 936319 # Per bank write bursts -system.physmem.perBankRdBursts::7 936043 # Per bank write bursts -system.physmem.perBankRdBursts::8 943596 # Per bank write bursts -system.physmem.perBankRdBursts::9 936992 # Per bank write bursts -system.physmem.perBankRdBursts::10 936414 # Per bank write bursts -system.physmem.perBankRdBursts::11 935912 # Per bank write bursts -system.physmem.perBankRdBursts::12 943556 # Per bank write bursts -system.physmem.perBankRdBursts::13 937007 # Per bank write bursts -system.physmem.perBankRdBursts::14 937039 # Per bank write bursts -system.physmem.perBankRdBursts::15 936676 # Per bank write bursts -system.physmem.perBankWrBursts::0 6606 # Per bank write bursts -system.physmem.perBankWrBursts::1 6375 # Per bank write bursts -system.physmem.perBankWrBursts::2 6521 # Per bank write bursts -system.physmem.perBankWrBursts::3 6552 # Per bank write bursts -system.physmem.perBankWrBursts::4 6461 # Per bank write bursts -system.physmem.perBankWrBursts::5 6711 # Per bank write bursts -system.physmem.perBankWrBursts::6 6720 # Per bank write bursts -system.physmem.perBankWrBursts::7 6668 # Per bank write bursts -system.physmem.perBankWrBursts::8 7045 # Per bank write bursts -system.physmem.perBankWrBursts::9 6826 # Per bank write bursts -system.physmem.perBankWrBursts::10 6497 # Per bank write bursts -system.physmem.perBankWrBursts::11 6136 # Per bank write bursts -system.physmem.perBankWrBursts::12 7072 # Per bank write bursts -system.physmem.perBankWrBursts::13 6672 # Per bank write bursts -system.physmem.perBankWrBursts::14 6956 # Per bank write bursts -system.physmem.perBankWrBursts::15 6819 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096864 # Number of read requests accepted +system.physmem.writeReqs 813148 # Number of write requests accepted +system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue +system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943480 # Per bank write bursts +system.physmem.perBankRdBursts::1 937980 # Per bank write bursts +system.physmem.perBankRdBursts::2 937559 # Per bank write bursts +system.physmem.perBankRdBursts::3 937528 # Per bank write bursts +system.physmem.perBankRdBursts::4 943087 # Per bank write bursts +system.physmem.perBankRdBursts::5 937982 # Per bank write bursts +system.physmem.perBankRdBursts::6 937070 # Per bank write bursts +system.physmem.perBankRdBursts::7 936990 # Per bank write bursts +system.physmem.perBankRdBursts::8 943982 # Per bank write bursts +system.physmem.perBankRdBursts::9 938303 # Per bank write bursts +system.physmem.perBankRdBursts::10 937119 # Per bank write bursts +system.physmem.perBankRdBursts::11 936407 # Per bank write bursts +system.physmem.perBankRdBursts::12 943924 # Per bank write bursts +system.physmem.perBankRdBursts::13 938214 # Per bank write bursts +system.physmem.perBankRdBursts::14 937241 # Per bank write bursts +system.physmem.perBankRdBursts::15 937211 # Per bank write bursts +system.physmem.perBankWrBursts::0 6601 # Per bank write bursts +system.physmem.perBankWrBursts::1 6388 # Per bank write bursts +system.physmem.perBankWrBursts::2 6528 # Per bank write bursts +system.physmem.perBankWrBursts::3 6554 # Per bank write bursts +system.physmem.perBankWrBursts::4 6464 # Per bank write bursts +system.physmem.perBankWrBursts::5 6726 # Per bank write bursts +system.physmem.perBankWrBursts::6 6713 # Per bank write bursts +system.physmem.perBankWrBursts::7 6652 # Per bank write bursts +system.physmem.perBankWrBursts::8 7031 # Per bank write bursts +system.physmem.perBankWrBursts::9 6803 # Per bank write bursts +system.physmem.perBankWrBursts::10 6461 # Per bank write bursts +system.physmem.perBankWrBursts::11 6104 # Per bank write bursts +system.physmem.perBankWrBursts::12 7064 # Per bank write bursts +system.physmem.perBankWrBursts::13 6684 # Per bank write bursts +system.physmem.perBankWrBursts::14 6965 # Per bank write bursts +system.physmem.perBankWrBursts::15 6836 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526168741500 # Total gap between requests +system.physmem.totGap 2526191083500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154622 # Read request sizes (log2) +system.physmem.readPktSize::6 154618 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1044851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 985737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 947948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 933228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 933834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2717841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2709185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3589675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 37568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 34960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 32201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 30053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59130 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,47 +159,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -208,67 +208,50 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads -system.physmem.totQLat 571195583500 # Total ticks spent queuing -system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers -system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks -system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads +system.physmem.totQLat 389908010000 # Total ticks spent queuing +system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -276,15 +259,19 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.99 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing -system.physmem.readRowHits 14041195 # Number of row buffer hits during reads -system.physmem.writeRowHits 91389 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes -system.physmem.avgGap 158778.41 # Average gap between requests -system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing +system.physmem.readRowHits 14044000 # Number of row buffer hits during reads +system.physmem.writeRowHits 91096 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes +system.physmem.avgGap 158779.96 # Average gap between requests +system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states +system.physmem.memoryStateTime::REF 84354920000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -297,50 +284,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54878638 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149508 # Transaction distribution -system.membus.trans_dist::ReadResp 16149508 # Transaction distribution +system.membus.throughput 54877773 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149486 # Transaction distribution +system.membus.trans_dist::ReadResp 16149486 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59141 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59130 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution +system.membus.trans_dist::ReadExReq 131451 # Transaction distribution +system.membus.trans_dist::ReadExResp 131451 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138632762 # Total data (bytes) +system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138631802 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -348,7 +335,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48266001 # Throughput (bytes/s) +system.iobus.throughput 48265574 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution @@ -458,18 +445,18 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14755327 # Number of BP lookups -system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits +system.cpu.branchPred.lookups 14753661 # Number of BP lookups +system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -493,25 +480,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51187284 # DTB read hits -system.cpu.dtb.read_misses 65383 # DTB read misses -system.cpu.dtb.write_hits 11703682 # DTB write hits -system.cpu.dtb.write_misses 15916 # DTB write misses +system.cpu.dtb.read_hits 51183231 # DTB read hits +system.cpu.dtb.read_misses 65223 # DTB read misses +system.cpu.dtb.write_hits 11700953 # DTB write hits +system.cpu.dtb.write_misses 15725 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252667 # DTB read accesses -system.cpu.dtb.write_accesses 11719598 # DTB write accesses +system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51248454 # DTB read accesses +system.cpu.dtb.write_accesses 11716678 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62890966 # DTB hits -system.cpu.dtb.misses 81299 # DTB misses -system.cpu.dtb.accesses 62972265 # DTB accesses +system.cpu.dtb.hits 62884184 # DTB hits +system.cpu.dtb.misses 80948 # DTB misses +system.cpu.dtb.accesses 62965132 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -533,8 +520,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11527099 # ITB inst hits -system.cpu.itb.inst_misses 11249 # ITB inst misses +system.cpu.itb.inst_hits 11525561 # ITB inst hits +system.cpu.itb.inst_misses 11159 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -543,113 +530,113 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11538348 # ITB inst accesses -system.cpu.itb.hits 11527099 # DTB hits -system.cpu.itb.misses 11249 # DTB misses -system.cpu.itb.accesses 11538348 # DTB accesses -system.cpu.numCycles 477119451 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11536720 # ITB inst accesses +system.cpu.itb.hits 11525561 # DTB hits +system.cpu.itb.misses 11159 # DTB misses +system.cpu.itb.accesses 11536720 # DTB accesses +system.cpu.numCycles 477128882 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available @@ -678,13 +665,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued @@ -697,11 +684,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued @@ -710,404 +697,440 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued -system.cpu.iq.rate 0.257655 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued +system.cpu.iq.rate 0.257622 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221278 # number of nop insts executed -system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed -system.cpu.iew.exec_branches 11821235 # Number of branches executed -system.cpu.iew.exec_stores 12215513 # Number of stores executed -system.cpu.iew.exec_rate 0.253301 # Inst execution rate -system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47029089 # num instructions producing a value -system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value +system.cpu.iew.exec_nop 222849 # number of nop insts executed +system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed +system.cpu.iew.exec_branches 11822089 # Number of branches executed +system.cpu.iew.exec_stores 12212847 # Number of stores executed +system.cpu.iew.exec_rate 0.253272 # Inst execution rate +system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47017508 # num instructions producing a value +system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60460018 # Number of instructions committed -system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459415 # Number of instructions committed +system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386851 # Number of memory references committed -system.cpu.commit.loads 15654790 # Number of loads committed -system.cpu.commit.membars 403577 # Number of memory barriers committed -system.cpu.commit.branches 10306380 # Number of branches committed +system.cpu.commit.refs 27386618 # Number of memory references committed +system.cpu.commit.loads 15654647 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 10306311 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191623 # Number of committed integer instructions. -system.cpu.commit.function_calls 991253 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. +system.cpu.commit.function_calls 991245 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction +system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242979782 # The number of ROB reads -system.cpu.rob.rob_writes 196005989 # The number of ROB writes -system.cpu.timesIdled 1777234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575137230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309637 # Number of Instructions Simulated -system.cpu.committedOps 77601213 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60309637 # Number of Instructions Simulated -system.cpu.cpi 7.911164 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911164 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126404 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126404 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548697999 # number of integer regfile reads -system.cpu.int_regfile_writes 87552825 # number of integer regfile writes -system.cpu.fp_regfile_reads 8408 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 268236665 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173235 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58867266 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2659080 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2659079 # Transaction distribution +system.cpu.rob.rob_reads 243007370 # The number of ROB reads +system.cpu.rob.rob_writes 195993770 # The number of ROB writes +system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309034 # Number of Instructions Simulated +system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60309034 # Number of Instructions Simulated +system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548643015 # number of integer regfile reads +system.cpu.int_regfile_writes 87545924 # number of integer regfile writes +system.cpu.fp_regfile_reads 8332 # number of floating regfile reads +system.cpu.fp_regfile_writes 2902 # number of floating regfile writes +system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2959 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2975 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246069 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796085 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129069 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62744960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85505466 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148505990 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148505990 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202724 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129185667 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474638965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2549207556 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20255489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75530794 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980897 # number of replacements -system.cpu.icache.tags.tagsinuse 511.570903 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10462766 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981409 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.660964 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6958078250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.570903 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999162 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999162 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 981488 # number of replacements +system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12504958 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12504958 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10462766 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10462766 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10462766 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10462766 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10462766 # number of overall hits -system.cpu.icache.overall_hits::total 10462766 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060743 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060743 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060743 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060743 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060743 # number of overall misses -system.cpu.icache.overall_misses::total 1060743 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14268635888 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14268635888 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14268635888 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14268635888 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14268635888 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14268635888 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11523509 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11523509 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11523509 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11523509 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11523509 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11523509 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13451.548479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13451.548479 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7798 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits +system.cpu.icache.overall_hits::total 10460581 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses +system.cpu.icache.overall_misses::total 1061360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 344 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.668605 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79293 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79293 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79293 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79293 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79293 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79293 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981450 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981450 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981450 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981450 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981450 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981450 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587546773 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11587546773 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587546773 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11587546773 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587546773 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11587546773 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9345000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9345000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9345000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9345000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085169 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085169 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085169 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 412000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 905251250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10637329490 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11546967240 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53643 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10248 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 980269 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397722 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1441882 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607635 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607635 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8190370021 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8190370021 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3834000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 405500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 738779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8858643271 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9601662271 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3834000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 405500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 738779500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8858643271 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9601662271 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6434999 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17456853479 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17456853479 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6434999 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1228,168 +1251,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101537487 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101537487 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13760648 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13760648 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259865 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259865 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242998 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242998 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21020513 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21020513 # 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number of overall misses -system.cpu.dcache.overall_misses::total 3698776 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9982812336 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9982812336 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 139744433579 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185287000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185287000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 245503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149727245915 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149727245915 # 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number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24719289 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24719289 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24719289 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050794 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050794 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289800 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289800 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052732 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000065 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000065 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149631 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149631 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149631 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149631 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40480.214513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40480.214513 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31777 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 23524 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.050436 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 85.854015 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21015072 # 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number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607635 # number of writebacks -system.cpu.dcache.writebacks::total 607635 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350728 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350728 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713476 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713476 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1349 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064204 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064204 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064204 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064204 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385631 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385631 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248941 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248941 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12178 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12178 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634572 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634572 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634572 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967633608 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967633608 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11307381788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11307381788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145644250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145644250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 213497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 213497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16275015396 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16275015396 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16275015396 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16275015396 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26867769000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26867769000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025671 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks +system.cpu.dcache.writebacks::total 607456 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1413,16 +1436,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 8e01cba8d..8f1b31c18 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,172 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403854 # Number of seconds simulated -sim_ticks 2403853586500 # Number of ticks simulated -final_tick 2403853586500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403852 # Number of seconds simulated +sim_ticks 2403852457500 # Number of ticks simulated +final_tick 2403852457500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171159 # Simulator instruction rate (inst/s) -host_op_rate 219830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6819657603 # Simulator tick rate (ticks/s) -host_mem_usage 469520 # Number of bytes of host memory used -host_seconds 352.49 # Real time elapsed on the host -sim_insts 60331708 # Number of instructions simulated -sim_ops 77487722 # Number of ops (including micro ops) simulated +host_inst_rate 165592 # Simulator instruction rate (inst/s) +host_op_rate 212680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6597855857 # Simulator tick rate (ticks/s) +host_mem_usage 469068 # Number of bytes of host memory used +host_seconds 364.34 # Real time elapsed on the host +sim_insts 60331653 # Number of instructions simulated +sim_ops 77487544 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7053720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7048216 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 63616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 681152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1342304 # Number of bytes read from this memory -system.physmem.bytes_read::total 124659968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 762760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298364 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558196 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759176 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 63936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 680960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1348288 # Number of bytes read from this memory +system.physmem.bytes_read::total 124660704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 63936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 186944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743808 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298564 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159248 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558004 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759624 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110250 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110164 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2912 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20981 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512403 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58490 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324591 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389549 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812444 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47764586 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10640 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21067 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512407 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58497 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324641 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39812 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389501 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812451 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47764609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2934338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932050 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 283358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 558397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51858386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77529 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557233 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540118 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648208 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811809 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47764586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 283279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 560886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51858717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317547 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557420 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66247 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47764609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3474456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472251 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 349609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1206604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54670195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13446822 # Number of read requests accepted -system.physmem.writeReqs 446449 # Number of write requests accepted -system.physmem.readBursts 13446822 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446449 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860596480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 2823168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109564448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2810956 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 402307 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2362 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835680 # Per bank write bursts -system.physmem.perBankRdBursts::1 835344 # Per bank write bursts -system.physmem.perBankRdBursts::2 835508 # Per bank write bursts -system.physmem.perBankRdBursts::3 835965 # Per bank write bursts -system.physmem.perBankRdBursts::4 837088 # Per bank write bursts -system.physmem.perBankRdBursts::5 837779 # Per bank write bursts -system.physmem.perBankRdBursts::6 837907 # Per bank write bursts -system.physmem.perBankRdBursts::7 839147 # Per bank write bursts -system.physmem.perBankRdBursts::8 840641 # Per bank write bursts -system.physmem.perBankRdBursts::9 843268 # Per bank write bursts -system.physmem.perBankRdBursts::10 843373 # Per bank write bursts -system.physmem.perBankRdBursts::11 843869 # Per bank write bursts -system.physmem.perBankRdBursts::12 845852 # Per bank write bursts -system.physmem.perBankRdBursts::13 846016 # Per bank write bursts -system.physmem.perBankRdBursts::14 844806 # Per bank write bursts -system.physmem.perBankRdBursts::15 844577 # Per bank write bursts -system.physmem.perBankWrBursts::0 2668 # Per bank write bursts -system.physmem.perBankWrBursts::1 2526 # Per bank write bursts -system.physmem.perBankWrBursts::2 2530 # Per bank write bursts -system.physmem.perBankWrBursts::3 3005 # Per bank write bursts -system.physmem.perBankWrBursts::4 3419 # Per bank write bursts -system.physmem.perBankWrBursts::5 3167 # Per bank write bursts -system.physmem.perBankWrBursts::6 2515 # Per bank write bursts -system.physmem.perBankWrBursts::7 2303 # Per bank write bursts -system.physmem.perBankWrBursts::8 2186 # Per bank write bursts -system.physmem.perBankWrBursts::9 2396 # Per bank write bursts -system.physmem.perBankWrBursts::10 2346 # Per bank write bursts -system.physmem.perBankWrBursts::11 2792 # Per bank write bursts -system.physmem.perBankWrBursts::12 3710 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 26597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 349526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1209014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54670713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13446501 # Number of read requests accepted +system.physmem.writeReqs 446412 # Number of write requests accepted +system.physmem.readBursts 13446501 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446412 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860576000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue +system.physmem.bytesWritten 2816640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109567680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2811588 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 402376 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2365 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835689 # Per bank write bursts +system.physmem.perBankRdBursts::1 835334 # Per bank write bursts +system.physmem.perBankRdBursts::2 835514 # Per bank write bursts +system.physmem.perBankRdBursts::3 835992 # Per bank write bursts +system.physmem.perBankRdBursts::4 837083 # Per bank write bursts +system.physmem.perBankRdBursts::5 837766 # Per bank write bursts +system.physmem.perBankRdBursts::6 837910 # Per bank write bursts +system.physmem.perBankRdBursts::7 839140 # Per bank write bursts +system.physmem.perBankRdBursts::8 840643 # Per bank write bursts +system.physmem.perBankRdBursts::9 843328 # Per bank write bursts +system.physmem.perBankRdBursts::10 843395 # Per bank write bursts +system.physmem.perBankRdBursts::11 843892 # Per bank write bursts +system.physmem.perBankRdBursts::12 845429 # Per bank write bursts +system.physmem.perBankRdBursts::13 846004 # Per bank write bursts +system.physmem.perBankRdBursts::14 844795 # Per bank write bursts +system.physmem.perBankRdBursts::15 844586 # Per bank write bursts +system.physmem.perBankWrBursts::0 2674 # Per bank write bursts +system.physmem.perBankWrBursts::1 2534 # Per bank write bursts +system.physmem.perBankWrBursts::2 2538 # Per bank write bursts +system.physmem.perBankWrBursts::3 3024 # Per bank write bursts +system.physmem.perBankWrBursts::4 3410 # Per bank write bursts +system.physmem.perBankWrBursts::5 3131 # Per bank write bursts +system.physmem.perBankWrBursts::6 2493 # Per bank write bursts +system.physmem.perBankWrBursts::7 2267 # Per bank write bursts +system.physmem.perBankWrBursts::8 2164 # Per bank write bursts +system.physmem.perBankWrBursts::9 2378 # Per bank write bursts +system.physmem.perBankWrBursts::10 2328 # Per bank write bursts +system.physmem.perBankWrBursts::11 2803 # Per bank write bursts +system.physmem.perBankWrBursts::12 3718 # Per bank write bursts system.physmem.perBankWrBursts::13 3446 # Per bank write bursts -system.physmem.perBankWrBursts::14 2600 # Per bank write bursts -system.physmem.perBankWrBursts::15 2503 # Per bank write bursts +system.physmem.perBankWrBursts::14 2595 # Per bank write bursts +system.physmem.perBankWrBursts::15 2507 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402817511500 # Total gap between requests +system.physmem.totGap 2402816386500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13411280 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 13410864 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35534 # Read request sizes (log2) +system.physmem.readPktSize::6 35637 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429363 # Write request sizes (log2) +system.physmem.writePktSize::2 429313 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17086 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 867414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 844196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 838512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 839224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 838671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 838847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2475363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2475187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3292199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 19694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 19741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 19565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 19145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17099 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 877452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 853858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 853065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 937219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 912169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2402802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2330624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3052022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 86874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 80661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 76244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 73288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -184,8 +180,8 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see @@ -196,48 +192,48 @@ system.physmem.wrQLenPdf::10 93 # Wh system.physmem.wrQLenPdf::11 93 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -246,79 +242,63 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 844644 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1019.942660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1014.395909 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 58.300980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1516 0.18% 0.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1237 0.15% 0.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 570 0.07% 0.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 375 0.04% 0.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 256 0.03% 0.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 198 0.02% 0.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 155 0.02% 0.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 158 0.02% 0.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 840179 99.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 844644 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 8295.373226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 315033.644502 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 1620 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.06% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1621 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1621 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.212832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 24.563019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.121341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 1 0.06% 0.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.12% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 1 0.06% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.06% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.06% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.06% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.06% 0.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.12% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 6 0.37% 0.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 488 30.10% 31.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 27 1.67% 32.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 60 3.70% 36.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 333 20.54% 57.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 10 0.62% 57.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.19% 57.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.12% 57.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.19% 58.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.12% 58.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.19% 58.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.31% 58.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.25% 58.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.31% 59.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 7 0.43% 59.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.19% 59.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 2 0.12% 60.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 8 0.49% 60.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.12% 60.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.06% 60.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 50 3.08% 63.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.25% 64.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 167 10.30% 74.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 328 20.23% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 16 0.99% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 15 0.93% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 23 1.42% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 17 1.05% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 13 0.80% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.12% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 2 0.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1621 # Writes before turning the bus around for reads -system.physmem.totQLat 510864117000 # Total ticks spent queuing -system.physmem.totMemAccLat 601782495750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67234100000 # Total ticks spent in databus transfers -system.physmem.totBankLat 23684278750 # Total ticks spent accessing banks -system.physmem.avgQLat 37991.44 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1761.33 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 866032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.952353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.296727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.584191 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8288 0.96% 0.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8846 1.02% 1.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6189 0.71% 2.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 800 0.09% 2.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 916 0.11% 2.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 687 0.08% 2.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7828 0.90% 3.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 243 0.03% 3.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 832235 96.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866032 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2414 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5570.207125 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 258157.496677 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2413 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2414 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2414 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.231152 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.108696 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.979905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 1 0.04% 0.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 2 0.08% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.04% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 1 0.04% 0.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 1 0.04% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 7 0.29% 0.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 485 20.09% 20.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.62% 21.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 872 36.12% 57.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 845 35.00% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 52 2.15% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 24 0.99% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 26 1.08% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 34 1.41% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.54% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.21% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.25% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.04% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 6 0.25% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 7 0.29% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.08% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.17% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2414 # Writes before turning the bus around for reads +system.physmem.totQLat 345783645500 # Total ticks spent queuing +system.physmem.totMemAccLat 597905520500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67232500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25715.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44752.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44465.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.00 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s @@ -326,15 +306,19 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 8.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 5.41 # Average write queue length when enqueuing -system.physmem.readRowHits 12595156 # Number of row buffer hits during reads -system.physmem.writeRowHits 38053 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.21 # Row buffer hit rate for writes -system.physmem.avgGap 172948.29 # Average gap between requests -system.physmem.pageHitRate 93.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.74 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 7.51 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.43 # Average write queue length when enqueuing +system.physmem.readRowHits 12586631 # Number of row buffer hits during reads +system.physmem.writeRowHits 37847 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.95 # Row buffer hit rate for writes +system.physmem.avgGap 172952.67 # Average gap between requests +system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2167477603250 # Time in different power states +system.physmem.memoryStateTime::REF 80269800000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 156101819250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -347,341 +331,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55667457 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13781916 # Transaction distribution -system.membus.trans_dist::ReadResp 13781916 # Transaction distribution -system.membus.trans_dist::WriteReq 432200 # Transaction distribution -system.membus.trans_dist::WriteResp 432200 # Transaction distribution -system.membus.trans_dist::Writeback 17086 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2361 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2362 # Transaction distribution -system.membus.trans_dist::ReadExReq 27973 # Transaction distribution -system.membus.trans_dist::ReadExResp 27973 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1683428 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26822560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26822560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28505988 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 420 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5085164 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5821052 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107290240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107290240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113111292 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133816415 # Total data (bytes) +system.membus.throughput 55667977 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13781620 # Transaction distribution +system.membus.trans_dist::ReadResp 13781620 # Transaction distribution +system.membus.trans_dist::WriteReq 432153 # Transaction distribution +system.membus.trans_dist::WriteResp 432153 # Transaction distribution +system.membus.trans_dist::Writeback 17099 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2365 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2365 # Transaction distribution +system.membus.trans_dist::ReadExReq 28041 # Transaction distribution +system.membus.trans_dist::ReadExResp 28041 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1683729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26821728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26821728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28505457 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735662 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5092356 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5828446 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107286912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107286912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113115358 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817603 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 416850000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 416874000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 198000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 199500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14576843000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14576510500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1595419615 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1596663785 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33523642000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33229062000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63235 # number of replacements -system.l2c.tags.tagsinuse 50381.174231 # Cycle average of tags in use -system.l2c.tags.total_refs 1749008 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128627 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.597518 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375559570500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36838.397677 # Average occupied blocks per requestor +system.l2c.tags.replacements 63248 # number of replacements +system.l2c.tags.tagsinuse 50398.234461 # Cycle average of tags in use +system.l2c.tags.total_refs 1749256 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128641 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.597966 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375562300000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36845.662788 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5238.516596 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3833.196793 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 493.229672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 688.317801 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.879272 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.004789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1684.639749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1594.998425 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562109 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5231.089770 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3832.891832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 496.025776 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 690.296020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.797358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1694.464698 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1598.012760 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562220 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079933 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079820 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058485 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007526 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010503 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024338 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768756 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.007569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010533 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024384 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.769016 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65389 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6490 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55882 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17681539 # Number of tag accesses -system.l2c.tags.data_accesses 17681539 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8692 # number of ReadReq hits +system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6488 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55889 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997757 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17683113 # Number of tag accesses +system.l2c.tags.data_accesses 17683113 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8690 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 468000 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177035 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2622 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1183 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 129681 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18896 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281169 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131701 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290860 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597704 # number of Writeback hits -system.l2c.Writeback_hits::total 597704 # number of Writeback hits +system.l2c.ReadReq_hits::cpu0.inst 468117 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 177120 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2623 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 129717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64377 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18993 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4195 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281260 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 131724 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291137 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597632 # number of Writeback hits +system.l2c.Writeback_hits::total 597632 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61997 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18431 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33199 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113627 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8692 # number of demand (read+write) hits +system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 62001 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 18409 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33201 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113611 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8690 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3137 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 468000 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239032 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2622 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 129681 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 82958 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18896 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4217 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 281169 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 164900 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404487 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8692 # number of overall hits +system.l2c.demand_hits::cpu0.inst 468117 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 239121 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2623 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1184 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 129717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 82786 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18993 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4195 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 281260 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 164925 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404748 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8690 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3137 # number of overall hits -system.l2c.overall_hits::cpu0.inst 468000 # number of overall hits -system.l2c.overall_hits::cpu0.data 239032 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2622 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1183 # number of overall hits -system.l2c.overall_hits::cpu1.inst 129681 # number of overall hits -system.l2c.overall_hits::cpu1.data 82958 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18896 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4217 # number of overall hits -system.l2c.overall_hits::cpu2.inst 281169 # number of overall hits -system.l2c.overall_hits::cpu2.data 164900 # number of overall hits -system.l2c.overall_hits::total 1404487 # number of overall hits +system.l2c.overall_hits::cpu0.inst 468117 # number of overall hits +system.l2c.overall_hits::cpu0.data 239121 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2623 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1184 # number of overall hits +system.l2c.overall_hits::cpu1.inst 129717 # number of overall hits +system.l2c.overall_hits::cpu1.data 82786 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18993 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4195 # number of overall hits +system.l2c.overall_hits::cpu2.inst 281260 # number of overall hits +system.l2c.overall_hits::cpu2.data 164925 # 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mshr miss rate for ReadExReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017085 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018967 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005786 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991543 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988361 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.507157 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347268 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365485 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117086 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007607 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.116274 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000529 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000237 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010251 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.115688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.116469 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116131 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023410 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007607 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.116274 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000529 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000237 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010251 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.115688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.116469 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116131 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023410 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58128.521127 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65115.591398 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66625 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64723.585279 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63163.106732 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64058.310992 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64394.188850 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63013.296340 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61297.583631 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61580.949808 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61484.690182 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59891.492036 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61174.798891 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60740.166229 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58128.521127 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61687.954375 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61949.052146 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61833.263466 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58128.521127 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61687.954375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61949.052146 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61833.263466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -854,52 +799,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58805312 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1019677 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1019676 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432200 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432200 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265274 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1507 # Transaction distribution +system.toL2Bus.throughput 58808825 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1019736 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1019735 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432153 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432153 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265208 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1511 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80476 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80476 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830192 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419562 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15560 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52654 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3317968 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26544384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37373820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21604 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86116 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64025924 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141258487 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 100872 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176910263 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1508 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80528 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80528 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830481 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419466 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15414 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52803 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3318164 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26553408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37366366 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64027794 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141267007 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 100732 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2176624753 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870334166 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1870991697 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1845880168 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1845922726 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10179455 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10050964 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31260469 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31304739 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48758934 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13774305 # Transaction distribution -system.iobus.trans_dist::ReadResp 13774305 # Transaction distribution -system.iobus.trans_dist::WriteReq 2774 # Transaction distribution -system.iobus.trans_dist::WriteResp 2774 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3022 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48758959 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13773981 # Transaction distribution +system.iobus.trans_dist::ReadResp 13773981 # Transaction distribution +system.iobus.trans_dist::WriteReq 2776 # Transaction distribution +system.iobus.trans_dist::WriteResp 2776 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11410 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716788 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -915,18 +860,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 731598 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26822560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26822560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27554158 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 731786 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26821728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26821728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27553514 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15374 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 504 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 712940 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713112 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -942,18 +887,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 735468 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107290240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107290240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108025708 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209339 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 735662 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107286912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107286912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108022574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209343 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7968000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1511000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 126000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -961,7 +906,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 358810000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 358898000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -993,11 +938,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13411280000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13410864000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 728824000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 729010000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33525822000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33767373000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1022,25 +967,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7997782 # DTB read hits -system.cpu0.dtb.read_misses 6203 # DTB read misses -system.cpu0.dtb.write_hits 6595987 # DTB write hits -system.cpu0.dtb.write_misses 1983 # DTB write misses +system.cpu0.dtb.read_hits 7995700 # DTB read hits +system.cpu0.dtb.read_misses 6195 # DTB read misses +system.cpu0.dtb.write_hits 6594454 # DTB write hits +system.cpu0.dtb.write_misses 1984 # DTB write misses system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5673 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8003985 # DTB read accesses -system.cpu0.dtb.write_accesses 6597970 # DTB write accesses +system.cpu0.dtb.read_accesses 8001895 # DTB read accesses +system.cpu0.dtb.write_accesses 6596438 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14593769 # DTB hits -system.cpu0.dtb.misses 8186 # DTB misses -system.cpu0.dtb.accesses 14601955 # DTB accesses +system.cpu0.dtb.hits 14590154 # DTB hits +system.cpu0.dtb.misses 8179 # DTB misses +system.cpu0.dtb.accesses 14598333 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1062,433 +1007,468 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32336935 # ITB inst hits -system.cpu0.itb.inst_misses 3451 # ITB inst misses +system.cpu0.itb.inst_hits 32327896 # ITB inst hits +system.cpu0.itb.inst_misses 3449 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2626 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32340386 # ITB inst accesses -system.cpu0.itb.hits 32336935 # DTB hits -system.cpu0.itb.misses 3451 # DTB misses -system.cpu0.itb.accesses 32340386 # DTB accesses -system.cpu0.numCycles 113724377 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32331345 # ITB inst accesses +system.cpu0.itb.hits 32327896 # DTB hits +system.cpu0.itb.misses 3449 # DTB misses +system.cpu0.itb.accesses 32331345 # DTB accesses +system.cpu0.numCycles 113683212 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31861763 # Number of instructions committed -system.cpu0.committedOps 42032224 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37415212 # Number of integer alu accesses +system.cpu0.committedInsts 31852389 # Number of instructions committed +system.cpu0.committedOps 42022034 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37405417 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses -system.cpu0.num_func_calls 1199152 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4246542 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37415212 # number of integer instructions +system.cpu0.num_func_calls 1199046 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4246321 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37405417 # number of integer instructions system.cpu0.num_fp_insts 4937 # number of float instructions -system.cpu0.num_int_register_reads 193939915 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39523913 # number of times the integer registers were written +system.cpu0.num_int_register_reads 193890675 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39514617 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written -system.cpu0.num_mem_refs 15261638 # number of memory refs -system.cpu0.num_load_insts 8366552 # Number of load instructions -system.cpu0.num_store_insts 6895086 # Number of store instructions -system.cpu0.num_idle_cycles 110931893.434026 # Number of idle cycles -system.cpu0.num_busy_cycles 2792483.565974 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024555 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975445 # Percentage of idle cycles -system.cpu0.Branches 5615139 # Number of branches fetched +system.cpu0.num_mem_refs 15257672 # number of memory refs +system.cpu0.num_load_insts 8364380 # Number of load instructions +system.cpu0.num_store_insts 6893292 # Number of store instructions +system.cpu0.num_idle_cycles 110986808.765580 # Number of idle cycles +system.cpu0.num_busy_cycles 2696403.234420 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023719 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976281 # Percentage of idle cycles +system.cpu0.Branches 5614656 # Number of branches fetched +system.cpu0.op_class::No_OpClass 14792 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 26773719 63.60% 63.63% # Class of executed instruction +system.cpu0.op_class::IntMult 49650 0.12% 63.75% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1431 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::MemRead 8364380 19.87% 83.63% # Class of executed instruction +system.cpu0.op_class::MemWrite 6893292 16.37% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 42097264 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891249 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602369 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43668526 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891761 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.968867 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8187850250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.923201 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.626935 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.052233 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966647 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014896 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017680 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999223 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 891512 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.602542 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43658005 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892024 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.942635 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8184230000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.829489 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.587272 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.185782 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966464 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014819 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017941 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 166 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45475856 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45475856 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31863243 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8064619 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3740664 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43668526 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31863243 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8064619 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3740664 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43668526 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31863243 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8064619 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3740664 # number of overall hits -system.cpu0.icache.overall_hits::total 43668526 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 476340 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 130939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 308276 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915555 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 476340 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 130939 # 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average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37626.330752 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29685.996789 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.723624 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13383.243432 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6098.345729 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21812.458447 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21812.458447 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8069 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3116 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 905 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 48 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.916022 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 64.916667 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597704 # number of writebacks -system.cpu0.dcache.writebacks::total 597704 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139099 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 139099 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 554931 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 554931 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 402 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 402 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 694030 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 694030 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 694030 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 694030 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63884 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57672251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1730851510 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543754841 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5274606351 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1730851510 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543754841 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5274606351 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27378129500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579482250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55957611750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439295977 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341687506 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14780983483 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817425477 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41921169756 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70738595233 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033899 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026683 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014082 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92428 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184316 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 276744 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92428 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184316 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 276744 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779830000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1694363864 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2474193864 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 934250758 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1848694495 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2782945253 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19406250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38393502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57799752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714080758 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543058359 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5257139117 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714080758 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543058359 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5257139117 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27392049000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579464500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55971513500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1440396400 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339396963 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14779793363 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28832445400 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41918861463 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70751306863 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033859 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026666 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014074 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021352 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008021 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050558 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.042958 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020268 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019443 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008026 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050186 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043054 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020255 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011508 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011508 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12244.912654 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12929.192868 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.836166 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33049.874922 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34752.722924 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34156.328208 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11146.105742 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.904561 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.197436 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011505 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011505 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12232.243694 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12934.667725 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.722377 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32579.535430 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34670.389239 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33939.184529 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.436927 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11550.391697 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11404.844515 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1522,25 +1502,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2097642 # DTB read hits +system.cpu1.dtb.read_hits 2096038 # DTB read hits system.cpu1.dtb.read_misses 2089 # DTB read misses -system.cpu1.dtb.write_hits 1419704 # DTB write hits -system.cpu1.dtb.write_misses 373 # DTB write misses +system.cpu1.dtb.write_hits 1418402 # DTB write hits +system.cpu1.dtb.write_misses 376 # DTB write misses system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1767 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1770 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2099731 # DTB read accesses -system.cpu1.dtb.write_accesses 1420077 # DTB write accesses +system.cpu1.dtb.read_accesses 2098127 # DTB read accesses +system.cpu1.dtb.write_accesses 1418778 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3517346 # DTB hits -system.cpu1.dtb.misses 2462 # DTB misses -system.cpu1.dtb.accesses 3519808 # DTB accesses +system.cpu1.dtb.hits 3514440 # DTB hits +system.cpu1.dtb.misses 2465 # DTB misses +system.cpu1.dtb.accesses 3516905 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1562,8 +1542,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8195558 # ITB inst hits -system.cpu1.itb.inst_misses 1195 # ITB inst misses +system.cpu1.itb.inst_hits 8190394 # ITB inst hits +system.cpu1.itb.inst_misses 1200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1572,51 +1552,86 @@ system.cpu1.itb.flush_tlb 554 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8196753 # ITB inst accesses -system.cpu1.itb.hits 8195558 # DTB hits -system.cpu1.itb.misses 1195 # DTB misses -system.cpu1.itb.accesses 8196753 # DTB accesses -system.cpu1.numCycles 584703165 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8191594 # ITB inst accesses +system.cpu1.itb.hits 8190394 # DTB hits +system.cpu1.itb.misses 1200 # DTB misses +system.cpu1.itb.accesses 8191594 # DTB accesses +system.cpu1.numCycles 584767176 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7984738 # Number of instructions committed -system.cpu1.committedOps 10135701 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9107037 # Number of integer alu accesses +system.cpu1.committedInsts 7979697 # Number of instructions committed +system.cpu1.committedOps 10128513 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9101420 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304651 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1115193 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9107037 # number of integer instructions +system.cpu1.num_func_calls 304592 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114093 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9101420 # number of integer instructions system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 53092313 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9899825 # number of times the integer registers were written +system.cpu1.num_int_register_reads 53054873 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9892627 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3684662 # number of memory refs -system.cpu1.num_load_insts 2190856 # Number of load instructions -system.cpu1.num_store_insts 1493806 # Number of store instructions -system.cpu1.num_idle_cycles 548865377.428164 # Number of idle cycles -system.cpu1.num_busy_cycles 35837787.571836 # Number of busy cycles -system.cpu1.not_idle_fraction 0.061292 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.938708 # Percentage of idle cycles -system.cpu1.Branches 1448177 # Number of branches fetched +system.cpu1.num_mem_refs 3681879 # number of memory refs +system.cpu1.num_load_insts 2189240 # Number of load instructions +system.cpu1.num_store_insts 1492639 # Number of store instructions +system.cpu1.num_idle_cycles 548440957.661697 # Number of idle cycles +system.cpu1.num_busy_cycles 36326218.338303 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062121 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937879 # Percentage of idle cycles +system.cpu1.Branches 1446987 # Number of branches fetched +system.cpu1.op_class::No_OpClass 5386 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6616988 64.14% 64.19% # Class of executed instruction +system.cpu1.op_class::IntMult 11601 0.11% 64.31% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::MemRead 2189240 21.22% 85.53% # Class of executed instruction +system.cpu1.op_class::MemWrite 1492639 14.47% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 10316152 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4782343 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3901882 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223184 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3184465 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2528356 # Number of BTB hits +system.cpu2.branchPred.lookups 4788852 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3906949 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223643 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3181584 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2530711 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.396571 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 413120 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21664 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.542486 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413887 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21714 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1640,25 +1655,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10925413 # DTB read hits -system.cpu2.dtb.read_misses 23157 # DTB read misses -system.cpu2.dtb.write_hits 3347832 # DTB write hits -system.cpu2.dtb.write_misses 6500 # DTB write misses +system.cpu2.dtb.read_hits 10930564 # DTB read hits +system.cpu2.dtb.read_misses 23215 # DTB read misses +system.cpu2.dtb.write_hits 3350483 # DTB write hits +system.cpu2.dtb.write_misses 6482 # DTB write misses system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 739 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 733 # Number of TLB faults due to alignment restrictions system.cpu2.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 476 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10948570 # DTB read accesses -system.cpu2.dtb.write_accesses 3354332 # DTB write accesses +system.cpu2.dtb.perms_faults 461 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10953779 # DTB read accesses +system.cpu2.dtb.write_accesses 3356965 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14273245 # DTB hits -system.cpu2.dtb.misses 29657 # DTB misses -system.cpu2.dtb.accesses 14302902 # DTB accesses +system.cpu2.dtb.hits 14281047 # DTB hits +system.cpu2.dtb.misses 29697 # DTB misses +system.cpu2.dtb.accesses 14310744 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1680,159 +1695,159 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4050371 # ITB inst hits -system.cpu2.itb.inst_misses 4655 # ITB inst misses +system.cpu2.itb.inst_hits 4054306 # ITB inst hits +system.cpu2.itb.inst_misses 4589 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1717 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1707 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 991 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 958 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4055026 # ITB inst accesses -system.cpu2.itb.hits 4050371 # DTB hits -system.cpu2.itb.misses 4655 # DTB misses -system.cpu2.itb.accesses 4055026 # DTB accesses -system.cpu2.numCycles 88306923 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4058895 # ITB inst accesses +system.cpu2.itb.hits 4054306 # DTB hits +system.cpu2.itb.misses 4589 # DTB misses +system.cpu2.itb.accesses 4058895 # DTB accesses +system.cpu2.numCycles 88316329 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9346989 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32490356 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4782343 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2941476 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6854845 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1758076 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51100 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19188137 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 924 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33833 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 718254 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4048944 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289644 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2020 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37402774 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.043825 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.431125 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9351504 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32524106 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4788852 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2944598 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6861719 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1761177 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50498 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19190819 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 265 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 860 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33145 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 719724 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 402 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4052907 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289738 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2002 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37419321 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.044533 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.431855 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30553136 81.69% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385541 1.03% 82.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516309 1.38% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 819811 2.19% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 629209 1.68% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341976 0.91% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1043472 2.79% 91.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 229749 0.61% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2883571 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30562706 81.68% 81.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385991 1.03% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516133 1.38% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 820285 2.19% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 630351 1.68% 87.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 341631 0.91% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1045289 2.79% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 230176 0.62% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2886759 7.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37402774 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054156 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367925 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9974482 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19754417 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6192036 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 324676 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1156258 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608942 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 52938 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36945008 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178323 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1156258 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10522715 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6823267 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11427905 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5953488 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1518249 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34855169 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 324878 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 884563 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 125 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37394312 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 160859531 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148302897 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3365 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26531284 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10863027 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 285247 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 261616 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3319534 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6621271 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3899723 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 529692 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 779693 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32174765 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 504636 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34747602 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55361 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7180763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19089893 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 148627 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37402774 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.929011 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.590003 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37419321 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054224 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368268 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9979534 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19757337 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6196813 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 326068 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1158658 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 609699 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 52950 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36983425 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178083 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1158658 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10528432 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6814826 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11435729 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5959486 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1521262 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34891179 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 96 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 325442 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 887620 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 163 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37432161 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 161024301 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148452649 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3370 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26548024 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10884136 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 285664 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 261962 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3325772 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6628163 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3904378 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 525369 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 781342 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32207136 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505175 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34773283 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55288 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7195240 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19128466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148705 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37419321 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.929287 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.589860 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24715445 66.08% 66.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3980638 10.64% 76.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2310084 6.18% 82.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974798 5.28% 88.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2777209 7.43% 95.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 968528 2.59% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 496348 1.33% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144954 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34770 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24716493 66.05% 66.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3990546 10.66% 76.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2313548 6.18% 82.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1974351 5.28% 88.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2779950 7.43% 95.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 967650 2.59% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 497474 1.33% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144778 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34531 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37402774 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37419321 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19778 1.30% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1391818 91.56% 92.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 108581 7.14% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19609 1.29% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1392955 91.52% 92.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109452 7.19% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8338 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19786480 56.94% 56.97% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28071 0.08% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8340 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19803061 56.95% 56.97% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28127 0.08% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.05% # Type of FU issued @@ -1845,129 +1860,164 @@ system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.05% # Ty system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 3 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 384 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11408808 32.83% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3515506 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11414599 32.83% 89.88% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3518761 10.12% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34747602 # Type of FU issued -system.cpu2.iq.rate 0.393487 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1520177 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043749 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108495492 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39865371 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28048299 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7541 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3951 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3361 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36255412 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4029 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205816 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34773283 # Type of FU issued +system.cpu2.iq.rate 0.393736 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1522017 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043770 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108565265 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39912731 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28072202 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7477 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4009 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3345 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36282976 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3984 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206198 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1533232 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1949 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9487 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562230 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1536367 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2104 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9509 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 563915 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5287398 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344554 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5287425 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344896 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1156258 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5195373 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88422 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32761739 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61550 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6621271 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3899723 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362828 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29785 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2577 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9487 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107399 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89296 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196695 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33832847 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11137918 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 914755 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1158658 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5187034 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 87972 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32794480 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61964 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6628163 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3904378 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362952 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29501 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2651 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9509 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107755 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89629 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197384 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33857007 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11143266 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 916276 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82338 # number of nop insts executed -system.cpu2.iew.exec_refs 14620271 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3761250 # Number of branches executed -system.cpu2.iew.exec_stores 3482353 # Number of stores executed -system.cpu2.iew.exec_rate 0.383128 # Inst execution rate -system.cpu2.iew.wb_sent 33431998 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28051660 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16098716 # num instructions producing a value -system.cpu2.iew.wb_consumers 29087027 # num instructions consuming a value +system.cpu2.iew.exec_nop 82169 # number of nop insts executed +system.cpu2.iew.exec_refs 14628489 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3765120 # Number of branches executed +system.cpu2.iew.exec_stores 3485223 # Number of stores executed +system.cpu2.iew.exec_rate 0.383361 # Inst execution rate +system.cpu2.iew.wb_sent 33455826 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28075547 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16112995 # num instructions producing a value +system.cpu2.iew.wb_consumers 29113416 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317661 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.553467 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317898 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.553456 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7131660 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356009 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171002 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 36246314 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.700075 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.737192 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7147493 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356470 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171471 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 36260461 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.700277 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.736744 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27334959 75.41% 75.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4433375 12.23% 87.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1255912 3.46% 91.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 639801 1.77% 92.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 511761 1.41% 94.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 317445 0.88% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 418775 1.16% 96.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 310656 0.86% 97.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1023630 2.82% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27338017 75.39% 75.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4438533 12.24% 87.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1258858 3.47% 91.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 640995 1.77% 92.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 514559 1.42% 94.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 318215 0.88% 95.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 418287 1.15% 96.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 309870 0.85% 97.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1023127 2.82% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 36246314 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20540563 # Number of instructions committed -system.cpu2.commit.committedOps 25375153 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 36260461 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20554943 # Number of instructions committed +system.cpu2.commit.committedOps 25392373 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8425532 # Number of memory references committed -system.cpu2.commit.loads 5088039 # Number of loads committed -system.cpu2.commit.membars 94081 # Number of memory barriers committed -system.cpu2.commit.branches 3238597 # Number of branches committed +system.cpu2.commit.refs 8432259 # Number of memory references committed +system.cpu2.commit.loads 5091796 # Number of loads committed +system.cpu2.commit.membars 94283 # Number of memory barriers committed +system.cpu2.commit.branches 3240263 # Number of branches committed system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22633154 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295425 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1023630 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 22648524 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295510 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 16933133 66.69% 66.69% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 26595 0.10% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 386 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5091796 20.05% 86.84% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3340463 13.16% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 25392373 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1023127 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 67208837 # The number of ROB reads -system.cpu2.rob.rob_writes 66213984 # The number of ROB writes -system.cpu2.timesIdled 359252 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 50904149 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3546216081 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20485207 # Number of Instructions Simulated -system.cpu2.committedOps 25319797 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20485207 # Number of Instructions Simulated -system.cpu2.cpi 4.310765 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.310765 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.231977 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.231977 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 156999830 # number of integer regfile reads -system.cpu2.int_regfile_writes 29869338 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46882 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45194 # number of floating regfile writes -system.cpu2.misc_regfile_reads 67020139 # number of misc regfile reads -system.cpu2.misc_regfile_writes 296788 # number of misc regfile writes +system.cpu2.rob.rob_reads 67255841 # The number of ROB reads +system.cpu2.rob.rob_writes 66282532 # The number of ROB writes +system.cpu2.timesIdled 358696 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 50897008 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3546076715 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20499567 # Number of Instructions Simulated +system.cpu2.committedOps 25336997 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20499567 # Number of Instructions Simulated +system.cpu2.cpi 4.308205 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.308205 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232115 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232115 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157113831 # number of integer regfile reads +system.cpu2.int_regfile_writes 29893796 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46822 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes +system.cpu2.misc_regfile_reads 67223937 # number of misc regfile reads +system.cpu2.misc_regfile_writes 297064 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1984,10 +2034,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1539425711000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1539425711000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1535534030000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1535534030000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index ef9bf74a4..2ae3638d8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,166 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550648 # Number of seconds simulated -sim_ticks 2550647964000 # Number of ticks simulated -final_tick 2550647964000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550603 # Number of seconds simulated +sim_ticks 2550603285500 # Number of ticks simulated +final_tick 2550603285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57676 # Simulator instruction rate (inst/s) -host_op_rate 74213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2439007396 # Simulator tick rate (ticks/s) -host_mem_usage 470664 # Number of bytes of host memory used -host_seconds 1045.77 # Real time elapsed on the host -sim_insts 60315890 # Number of instructions simulated -sim_ops 77609880 # Number of ops (including micro ops) simulated +host_inst_rate 56179 # Simulator instruction rate (inst/s) +host_op_rate 72287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2375661490 # Simulator tick rate (ticks/s) +host_mem_usage 471120 # Number of bytes of host memory used +host_seconds 1073.64 # Real time elapsed on the host +sim_insts 60315997 # Number of instructions simulated +sim_ops 77609994 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 483008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5043284 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 315584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4051356 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 483008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 315584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785856 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494724 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801956 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 487168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5091220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 310848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4002308 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 487168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 310848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521388 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494684 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801544 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7547 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 63309 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293483 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59154 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380344 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373681 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813179 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47482259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 803 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7612 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 79585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4857 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 62537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293452 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59148 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380347 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373671 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813166 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47483091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 778 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 189367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1977256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1588363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51362077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 189367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313094 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596466 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586017 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2666756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47482259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1996085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 121872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1569161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51362340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 121872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 312873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596482 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2666641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47483091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 778 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 189367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2573722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2174381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54028833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293483 # Number of read requests accepted -system.physmem.writeReqs 813179 # Number of write requests accepted -system.physmem.readBursts 15293483 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813179 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976671488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2111424 # Total number of bytes read from write queue -system.physmem.bytesWritten 6834624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131006576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801956 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 32991 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706366 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4694 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955809 # Per bank write bursts -system.physmem.perBankRdBursts::1 953120 # Per bank write bursts -system.physmem.perBankRdBursts::2 953063 # Per bank write bursts -system.physmem.perBankRdBursts::3 953290 # Per bank write bursts -system.physmem.perBankRdBursts::4 955524 # Per bank write bursts -system.physmem.perBankRdBursts::5 952811 # Per bank write bursts -system.physmem.perBankRdBursts::6 952747 # Per bank write bursts -system.physmem.perBankRdBursts::7 952554 # Per bank write bursts -system.physmem.perBankRdBursts::8 956154 # Per bank write bursts -system.physmem.perBankRdBursts::9 953015 # Per bank write bursts -system.physmem.perBankRdBursts::10 952848 # Per bank write bursts -system.physmem.perBankRdBursts::11 952579 # Per bank write bursts -system.physmem.perBankRdBursts::12 956184 # Per bank write bursts -system.physmem.perBankRdBursts::13 953741 # Per bank write bursts -system.physmem.perBankRdBursts::14 953594 # Per bank write bursts -system.physmem.perBankRdBursts::15 953459 # Per bank write bursts -system.physmem.perBankWrBursts::0 6616 # Per bank write bursts -system.physmem.perBankWrBursts::1 6407 # Per bank write bursts -system.physmem.perBankWrBursts::2 6542 # Per bank write bursts -system.physmem.perBankWrBursts::3 6564 # Per bank write bursts -system.physmem.perBankWrBursts::4 6491 # Per bank write bursts -system.physmem.perBankWrBursts::5 6761 # Per bank write bursts -system.physmem.perBankWrBursts::6 6753 # Per bank write bursts -system.physmem.perBankWrBursts::7 6706 # Per bank write bursts -system.physmem.perBankWrBursts::8 7029 # Per bank write bursts -system.physmem.perBankWrBursts::9 6806 # Per bank write bursts -system.physmem.perBankWrBursts::10 6476 # Per bank write bursts -system.physmem.perBankWrBursts::11 6118 # Per bank write bursts -system.physmem.perBankWrBursts::12 7056 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 191001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2592566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 121872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2155173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54028981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293452 # Number of read requests accepted +system.physmem.writeReqs 813166 # Number of write requests accepted +system.physmem.readBursts 15293452 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813166 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 977025792 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1755136 # Total number of bytes read from write queue +system.physmem.bytesWritten 6829888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131004952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801544 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 27424 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706426 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955870 # Per bank write bursts +system.physmem.perBankRdBursts::1 953353 # Per bank write bursts +system.physmem.perBankRdBursts::2 953267 # Per bank write bursts +system.physmem.perBankRdBursts::3 953402 # Per bank write bursts +system.physmem.perBankRdBursts::4 955744 # Per bank write bursts +system.physmem.perBankRdBursts::5 953745 # Per bank write bursts +system.physmem.perBankRdBursts::6 953482 # Per bank write bursts +system.physmem.perBankRdBursts::7 953247 # Per bank write bursts +system.physmem.perBankRdBursts::8 956258 # Per bank write bursts +system.physmem.perBankRdBursts::9 953771 # Per bank write bursts +system.physmem.perBankRdBursts::10 953551 # Per bank write bursts +system.physmem.perBankRdBursts::11 953111 # Per bank write bursts +system.physmem.perBankRdBursts::12 956206 # Per bank write bursts +system.physmem.perBankRdBursts::13 953857 # Per bank write bursts +system.physmem.perBankRdBursts::14 953612 # Per bank write bursts +system.physmem.perBankRdBursts::15 953552 # Per bank write bursts +system.physmem.perBankWrBursts::0 6609 # Per bank write bursts +system.physmem.perBankWrBursts::1 6381 # Per bank write bursts +system.physmem.perBankWrBursts::2 6537 # Per bank write bursts +system.physmem.perBankWrBursts::3 6560 # Per bank write bursts +system.physmem.perBankWrBursts::4 6488 # Per bank write bursts +system.physmem.perBankWrBursts::5 6754 # Per bank write bursts +system.physmem.perBankWrBursts::6 6745 # Per bank write bursts +system.physmem.perBankWrBursts::7 6685 # Per bank write bursts +system.physmem.perBankWrBursts::8 7023 # Per bank write bursts +system.physmem.perBankWrBursts::9 6801 # Per bank write bursts +system.physmem.perBankWrBursts::10 6470 # Per bank write bursts +system.physmem.perBankWrBursts::11 6120 # Per bank write bursts +system.physmem.perBankWrBursts::12 7060 # Per bank write bursts system.physmem.perBankWrBursts::13 6677 # Per bank write bursts -system.physmem.perBankWrBursts::14 6959 # Per bank write bursts -system.physmem.perBankWrBursts::15 6830 # Per bank write bursts +system.physmem.perBankWrBursts::14 6963 # Per bank write bursts +system.physmem.perBankWrBursts::15 6844 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550646795500 # Total gap between requests +system.physmem.totGap 2550602119500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 44 # Read request sizes (log2) +system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154623 # Read request sizes (log2) +system.physmem.readPktSize::6 154598 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754025 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59154 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1055042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 994364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 947765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 947544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 945397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 945218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2783572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2783267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3699218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 24042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 23218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59148 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1066844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1005139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 964469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1068011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 971384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1033822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2692544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2602827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3401172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 102949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 95927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 92392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -174,61 +162,61 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5456 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -237,93 +225,76 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 965273 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1013.486813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 999.850047 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 92.541667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4202 0.44% 0.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3517 0.36% 0.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1855 0.19% 0.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1291 0.13% 1.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 949 0.10% 1.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 717 0.07% 1.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 589 0.06% 1.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 765 0.08% 1.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 951388 98.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 965273 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5001 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3051.486103 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 52637.524815 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 4974 99.46% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.16% 99.64% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 6 0.12% 99.76% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 2 0.04% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.84% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.14% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.187598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 908.669037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 201.227455 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22588 2.23% 2.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20116 1.99% 4.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8785 0.87% 5.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2331 0.23% 5.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2167 0.21% 5.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1761 0.17% 5.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9115 0.90% 6.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 858 0.08% 6.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943241 93.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2514.580135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47785.198367 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6044 99.56% 99.56% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.57% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 6 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5001 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5001 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.353929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.695200 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.701170 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 8 0.16% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.04% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 3 0.06% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.02% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 8 0.16% 0.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.02% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.02% 0.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.06% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 5 0.10% 0.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 2 0.04% 0.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 5 0.10% 0.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.04% 0.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.02% 0.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 1 0.02% 0.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 10 0.20% 1.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2816 56.31% 57.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 26 0.52% 57.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 135 2.70% 60.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 879 17.58% 78.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 49 0.98% 79.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 23 0.46% 79.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.30% 79.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 25 0.50% 80.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 14 0.28% 80.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 18 0.36% 81.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.14% 81.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.30% 81.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 16 0.32% 81.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 18 0.36% 82.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 15 0.30% 82.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 8 0.16% 82.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 16 0.32% 82.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 10 0.20% 83.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.02% 83.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.02% 83.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.06% 83.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 243 4.86% 88.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 480 9.60% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 27 0.54% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 20 0.40% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 27 0.54% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 21 0.42% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 16 0.32% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5001 # Writes before turning the bus around for reads -system.physmem.totQLat 577566851750 # Total ticks spent queuing -system.physmem.totMemAccLat 682115428000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76302460000 # Total ticks spent in databus transfers -system.physmem.totBankLat 28246116250 # Total ticks spent accessing banks -system.physmem.avgQLat 37847.20 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1850.93 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.578158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.392553 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.387042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 4 0.07% 0.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.03% 0.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 7 0.12% 0.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.05% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 4 0.07% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 6 0.10% 0.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 2 0.03% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 3 0.05% 0.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 2 0.03% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 12 0.20% 0.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2739 45.12% 46.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.58% 46.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1542 25.40% 72.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1308 21.55% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 93 1.53% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 45 0.74% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 49 0.81% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 58 0.96% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 25 0.41% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.28% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 20 0.33% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 16 0.26% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 13 0.21% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.23% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 14 0.23% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 16 0.26% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 10 0.16% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads +system.physmem.totQLat 393355196000 # Total ticks spent queuing +system.physmem.totMemAccLat 679593221000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76330140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25766.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44698.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 382.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44516.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.06 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -331,299 +302,308 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.38 # Average write queue length when enqueuing -system.physmem.readRowHits 14274135 # Number of row buffer hits during reads -system.physmem.writeRowHits 91331 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.51 # Row buffer hit rate for writes -system.physmem.avgGap 158359.74 # Average gap between requests -system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.60 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54969038 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346130 # Transaction distribution -system.membus.trans_dist::ReadResp 16346133 # Transaction distribution -system.membus.trans_dist::WriteReq 763365 # Transaction distribution -system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59154 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4694 # Transaction distribution -system.membus.trans_dist::ReadExReq 131434 # Transaction distribution -system.membus.trans_dist::ReadExResp 131434 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3 # Transaction distribution +system.physmem.avgRdQLen 6.51 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.34 # Average write queue length when enqueuing +system.physmem.readRowHits 14270645 # Number of row buffer hits during reads +system.physmem.writeRowHits 91138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.38 # Row buffer hit rate for writes +system.physmem.avgGap 158357.40 # Average gap between requests +system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2202343950500 # Time in different power states +system.physmem.memoryStateTime::REF 85170020000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 263082705750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54969203 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346092 # Transaction distribution +system.membus.trans_dist::ReadResp 16346092 # Transaction distribution +system.membus.trans_dist::WriteReq 763361 # Transaction distribution +system.membus.trans_dist::WriteResp 763361 # Transaction distribution +system.membus.trans_dist::Writeback 59148 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4680 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4680 # Transaction distribution +system.membus.trans_dist::ReadExReq 131444 # Transaction distribution +system.membus.trans_dist::ReadExResp 131444 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383060 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885926 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272780 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885816 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272670 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550412 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550302 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390486 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698004 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19096138 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16695968 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19094102 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140206666 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140206666 # Total data (bytes) +system.membus.tot_pkt_size::total 140204630 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140204630 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487459000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486938500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3616000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17565357500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17564463000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737629056 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4735162713 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37816335199 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37454635709 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64394 # number of replacements -system.l2c.tags.tagsinuse 51423.269942 # Cycle average of tags in use -system.l2c.tags.total_refs 1904392 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129782 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.673776 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2513283956500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36971.606132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 22.825180 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4577.267389 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3052.603978 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.951997 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3614.635006 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3176.379887 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564142 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000348 # Average percentage of cache occupancy +system.l2c.tags.replacements 64370 # number of replacements +system.l2c.tags.tagsinuse 51446.531370 # Cycle average of tags in use +system.l2c.tags.total_refs 1904863 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129760 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.679894 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2513258094500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36996.902854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 21.266230 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4638.850911 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3223.219228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.615555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3561.358912 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2994.317308 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564528 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000324 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.069844 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046579 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.048468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784657 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.070783 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.049182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.054342 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045690 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.785012 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65368 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3070 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6838 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55080 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000320 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18929537 # Number of tag accesses -system.l2c.tags.data_accesses 18929537 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32378 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6463 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 508619 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 187861 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31368 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7240 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 462078 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 199585 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435592 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608227 # number of Writeback hits -system.l2c.Writeback_hits::total 608227 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 19 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 39 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60126 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52843 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112969 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32378 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6463 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 508619 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 247987 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7240 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 462078 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 252428 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548561 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32378 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6463 # number of overall hits -system.l2c.overall_hits::cpu0.inst 508619 # number of overall hits -system.l2c.overall_hits::cpu0.data 247987 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31368 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7240 # number of overall hits -system.l2c.overall_hits::cpu1.inst 462078 # number of overall hits -system.l2c.overall_hits::cpu1.data 252428 # number of overall hits -system.l2c.overall_hits::total 1548561 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 32 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3064 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6835 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55083 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997437 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18932032 # Number of tag accesses +system.l2c.tags.data_accesses 18932032 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 32158 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6860 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 505744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 187679 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 31450 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7231 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 465794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 199404 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1436320 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 607907 # number of Writeback hits +system.l2c.Writeback_hits::total 607907 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58462 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54465 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112927 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32158 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6860 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 505744 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 246141 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 31450 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7231 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 465794 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 253869 # number of demand (read+write) hits +system.l2c.demand_hits::total 1549247 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32158 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6860 # number of overall hits +system.l2c.overall_hits::cpu0.inst 505744 # number of overall hits +system.l2c.overall_hits::cpu0.data 246141 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 31450 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7231 # number of overall hits +system.l2c.overall_hits::cpu1.inst 465794 # number of overall hits +system.l2c.overall_hits::cpu1.data 253869 # number of overall hits +system.l2c.overall_hits::total 1549247 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 31 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7439 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6013 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4938 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4716 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23150 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1629 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1286 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2915 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 73716 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 59496 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133212 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 32 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 7502 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6162 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4864 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4544 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23117 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1628 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1276 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 74336 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 58884 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133220 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 31 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7439 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 79729 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4938 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 64212 # number of demand (read+write) misses -system.l2c.demand_misses::total 156362 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 32 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7502 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 80498 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4864 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 63428 # number of demand (read+write) misses +system.l2c.demand_misses::total 156337 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 31 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7439 # number of overall misses -system.l2c.overall_misses::cpu0.data 79729 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4938 # number of overall misses -system.l2c.overall_misses::cpu1.data 64212 # number of overall misses -system.l2c.overall_misses::total 156362 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2459000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 535184750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 452595249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 747500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 359066750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 362580750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1712791999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 209991 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 255489 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17376757108 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6521499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92839198608 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91480887000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184326607107 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000963 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014601 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.031572 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010320 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022163 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015784 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988464 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988381 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988428 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.559767 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.519493 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541221 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000963 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014601 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010320 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.199825 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091614 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000963 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014601 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010320 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.199825 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091614 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60965.563562 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62849.336283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60431.379102 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.332037 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.028816 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61909.037929 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61530.932970 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61740.166261 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59382.099596 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61974.555949 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60166.599067 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61748.237856 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61701.909837 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59382.099596 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61974.555949 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60166.599067 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61748.237856 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61701.909837 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.566614 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.688361 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61669.274080 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61089.105156 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61412.836106 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -799,10 +767,6 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -814,43 +778,40 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58424320 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676714 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676716 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608227 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2954 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246181 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246181 # Transaction distribution -system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution -system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution -system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967568 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797861 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37552 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149979 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952960 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62924224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85579658 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 255152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148813854 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148813854 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 206020 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4963822946 # Layer occupancy (ticks) +system.toL2Bus.throughput 58427348 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677396 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677395 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 607907 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2938 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2945 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246147 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246147 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1969203 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796633 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38454 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7953885 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62977408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85532246 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56372 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148820630 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148820630 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 204356 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4962673723 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4432706696 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4436346984 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4484503287 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4483051170 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23902881 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24406904 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86618127 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86367392 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48419467 # Throughput (bytes/s) +system.iobus.throughput 48420315 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322169 # Transaction distribution system.iobus.trans_dist::ReadResp 16322169 # Transaction distribution system.iobus.trans_dist::WriteReq 8177 # Transaction distribution @@ -960,17 +921,17 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374883000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37825687801 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38146923291 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7508483 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5992866 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 375676 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4822577 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3918936 # Number of BTB hits +system.cpu0.branchPred.lookups 7527303 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6005482 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 376664 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4812068 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3910560 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.262279 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 722501 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39246 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.265685 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 724420 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38989 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -994,25 +955,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25709068 # DTB read hits -system.cpu0.dtb.read_misses 39624 # DTB read misses -system.cpu0.dtb.write_hits 6152335 # DTB write hits -system.cpu0.dtb.write_misses 10221 # DTB write misses +system.cpu0.dtb.read_hits 25762472 # DTB read hits +system.cpu0.dtb.read_misses 39475 # DTB read misses +system.cpu0.dtb.write_hits 6143291 # DTB write hits +system.cpu0.dtb.write_misses 10324 # DTB write misses system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5608 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1406 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 264 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5580 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1376 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 646 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25748692 # DTB read accesses -system.cpu0.dtb.write_accesses 6162556 # DTB write accesses +system.cpu0.dtb.perms_faults 639 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25801947 # DTB read accesses +system.cpu0.dtb.write_accesses 6153615 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31861403 # DTB hits -system.cpu0.dtb.misses 49845 # DTB misses -system.cpu0.dtb.accesses 31911248 # DTB accesses +system.cpu0.dtb.hits 31905763 # DTB hits +system.cpu0.dtb.misses 49799 # DTB misses +system.cpu0.dtb.accesses 31955562 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1034,687 +995,714 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5876098 # ITB inst hits -system.cpu0.itb.inst_misses 7014 # ITB inst misses +system.cpu0.itb.inst_hits 5893431 # ITB inst hits +system.cpu0.itb.inst_misses 7431 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2644 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2617 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1469 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1506 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5883112 # ITB inst accesses -system.cpu0.itb.hits 5876098 # DTB hits -system.cpu0.itb.misses 7014 # DTB misses -system.cpu0.itb.accesses 5883112 # DTB accesses -system.cpu0.numCycles 242192321 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5900862 # ITB inst accesses +system.cpu0.itb.hits 5893431 # DTB hits +system.cpu0.itb.misses 7431 # DTB misses +system.cpu0.itb.accesses 5900862 # DTB accesses +system.cpu0.numCycles 242264674 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15567613 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45445847 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7508483 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4641437 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10272972 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2435180 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81106 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50250706 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1544 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 48114 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1489776 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 378 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5874191 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 367063 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2900 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 79394723 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.721041 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.068559 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15531926 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45587183 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7527303 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4634980 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10285875 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2434733 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 89107 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 50171859 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2068 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 54478 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1474048 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5891523 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 366856 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3025 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 79291736 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.723314 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.072188 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 69128739 87.07% 87.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 676261 0.85% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 870795 1.10% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1169302 1.47% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1115285 1.40% 91.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 553948 0.70% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1287197 1.62% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 378519 0.48% 94.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4214677 5.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 69012854 87.04% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 680232 0.86% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 874808 1.10% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1172230 1.48% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1090891 1.38% 91.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557599 0.70% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1295199 1.63% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 379880 0.48% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4228043 5.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79394723 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031002 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.187644 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16658432 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 51288095 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9197431 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 656874 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1591763 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1006093 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91406 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54494283 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 303520 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1591763 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17551658 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20345183 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27653568 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8896202 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3354292 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 51932303 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 196 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 500448 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2179621 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 261 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 53595851 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 240832893 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 219678051 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5082 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39195467 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14400384 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 591696 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 540219 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6961736 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10014185 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6974197 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1050889 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1353332 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 48232956 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1025841 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61971057 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88766 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9957722 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24611703 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 275811 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 79394723 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.780544 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.499047 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 79291736 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031071 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.188171 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16635366 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 51194908 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9213198 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 653944 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1592125 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1010665 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90813 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54600074 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 300654 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1592125 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17527482 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20299787 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27625200 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8910460 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3334547 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52031373 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 331 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 485563 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2176301 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 182 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 53736698 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 241285167 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 220106334 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4864 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39390817 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14345881 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 590593 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 539084 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6947132 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10055649 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6962422 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1056834 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1358453 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 48348288 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1003135 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62086915 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 89013 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9905639 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24691410 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 254686 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 79291736 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.783019 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.501466 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56910995 71.68% 71.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7345017 9.25% 80.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3503110 4.41% 85.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2918035 3.68% 89.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6157997 7.76% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1482939 1.87% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 783446 0.99% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 227116 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66068 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56790483 71.62% 71.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7331291 9.25% 80.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3517102 4.44% 85.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2900884 3.66% 88.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6182474 7.80% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1488398 1.88% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 785922 0.99% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 230106 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65076 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 79394723 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 79291736 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29670 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4193006 94.32% 94.99% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 222912 5.01% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 31039 0.70% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4198728 94.33% 95.03% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 221343 4.97% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15869 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29065604 46.90% 46.93% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46869 0.08% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1239 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26385475 42.58% 89.58% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6455974 10.42% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14970 0.02% 0.02% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29137192 46.93% 46.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47374 0.08% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1226 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26440432 42.59% 89.62% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6445693 10.38% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61971057 # Type of FU issued -system.cpu0.iq.rate 0.255875 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4445589 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.071737 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207909567 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59225484 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43186225 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11292 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6130 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5133 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66394829 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5948 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 311727 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62086915 # Type of FU issued +system.cpu0.iq.rate 0.256277 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4451111 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.071692 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208044448 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59266351 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43285904 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 10871 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5830 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4924 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66517304 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5752 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316537 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2130667 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3740 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15655 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 850179 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2144033 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4052 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15721 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 849604 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17067257 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348827 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17082730 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 349385 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1591763 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15715155 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239745 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49373573 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105603 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10014185 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6974197 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 727713 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 55741 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4727 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15655 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 183161 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144870 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 328031 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 60906320 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26058550 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1064737 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1592125 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15682380 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239912 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49471978 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105539 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10055649 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6962422 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 704937 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56286 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4027 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15721 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184221 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 145235 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 329456 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61023718 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26110824 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1063197 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 114776 # number of nop insts executed -system.cpu0.iew.exec_refs 32455686 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5967734 # Number of branches executed -system.cpu0.iew.exec_stores 6397136 # Number of stores executed -system.cpu0.iew.exec_rate 0.251479 # Inst execution rate -system.cpu0.iew.wb_sent 60414213 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43191358 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23287316 # num instructions producing a value -system.cpu0.iew.wb_consumers 42834885 # num instructions consuming a value +system.cpu0.iew.exec_nop 120555 # number of nop insts executed +system.cpu0.iew.exec_refs 32498156 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5982225 # Number of branches executed +system.cpu0.iew.exec_stores 6387332 # Number of stores executed +system.cpu0.iew.exec_rate 0.251889 # Inst execution rate +system.cpu0.iew.wb_sent 60528797 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43290828 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23369621 # num instructions producing a value +system.cpu0.iew.wb_consumers 42956226 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.178335 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.543653 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.178692 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544033 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9785836 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 750030 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 285660 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77802960 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.502286 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.465598 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9786876 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 748449 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 287258 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77699611 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.504830 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.472024 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 63388396 81.47% 81.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7400911 9.51% 90.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1988257 2.56% 93.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1098992 1.41% 94.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 865715 1.11% 96.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575312 0.74% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 733525 0.94% 97.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 350428 0.45% 98.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1401424 1.80% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 63277588 81.44% 81.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7407512 9.53% 90.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1967451 2.53% 93.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1105852 1.42% 94.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 852897 1.10% 96.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 576328 0.74% 96.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 737114 0.95% 97.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 349768 0.45% 98.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1425101 1.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77802960 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29900744 # Number of instructions committed -system.cpu0.commit.committedOps 39079359 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 77699611 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30084753 # Number of instructions committed +system.cpu0.commit.committedOps 39225066 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14007536 # Number of memory references committed -system.cpu0.commit.loads 7883518 # Number of loads committed -system.cpu0.commit.membars 209346 # Number of memory barriers committed -system.cpu0.commit.branches 5162239 # Number of branches committed -system.cpu0.commit.fp_insts 5086 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34792812 # Number of committed integer instructions. -system.cpu0.commit.function_calls 507721 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1401424 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14024434 # Number of memory references committed +system.cpu0.commit.loads 7911616 # Number of loads committed +system.cpu0.commit.membars 209739 # Number of memory barriers committed +system.cpu0.commit.branches 5192960 # Number of branches committed +system.cpu0.commit.fp_insts 4874 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34907078 # Number of committed integer instructions. +system.cpu0.commit.function_calls 509367 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 25154804 64.13% 64.13% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 44602 0.11% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 1226 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7911616 20.17% 84.42% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 6112818 15.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 39225066 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1425101 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124291086 # The number of ROB reads -system.cpu0.rob.rob_writes 99365166 # The number of ROB writes -system.cpu0.timesIdled 908697 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 162797598 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2248209209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29823122 # Number of Instructions Simulated -system.cpu0.committedOps 39001737 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29823122 # Number of Instructions Simulated -system.cpu0.cpi 8.120958 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.120958 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123138 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123138 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 276680521 # number of integer regfile reads -system.cpu0.int_regfile_writes 43875243 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44965 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42348 # number of floating regfile writes -system.cpu0.misc_regfile_reads 137565982 # number of misc regfile reads -system.cpu0.misc_regfile_writes 581037 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983714 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.569506 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10510100 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984226 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.678543 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7060452000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.023627 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 194.545879 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.619187 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.379972 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999159 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 124324951 # The number of ROB reads +system.cpu0.rob.rob_writes 99658992 # The number of ROB writes +system.cpu0.timesIdled 907419 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 162972938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2247980405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30002566 # Number of Instructions Simulated +system.cpu0.committedOps 39142879 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 30002566 # Number of Instructions Simulated +system.cpu0.cpi 8.074798 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.074798 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123842 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123842 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 277224657 # number of integer regfile reads +system.cpu0.int_regfile_writes 43993248 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44815 # number of floating regfile reads +system.cpu0.fp_regfile_writes 42286 # number of floating regfile writes +system.cpu0.misc_regfile_reads 137449038 # number of misc regfile reads +system.cpu0.misc_regfile_writes 580454 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984532 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.571226 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10502635 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 985044 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.662097 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7040991250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.697202 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 193.874025 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.620502 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.378660 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999163 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 163 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12559701 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12559701 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5314791 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5195309 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10510100 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5314791 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5195309 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10510100 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5314791 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5195309 # number of overall hits -system.cpu0.icache.overall_hits::total 10510100 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 559278 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 506065 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065343 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 559278 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 506065 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065343 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 559278 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 506065 # number of overall misses -system.cpu0.icache.overall_misses::total 1065343 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7693667190 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6830219775 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14523886965 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7693667190 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6830219775 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14523886965 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7693667190 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6830219775 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14523886965 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5874069 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5701374 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11575443 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5874069 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5701374 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11575443 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5874069 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5701374 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11575443 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.095211 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.088762 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.095211 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.088762 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.095211 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.088762 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13756.427376 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13496.724284 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13633.061807 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13756.427376 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13496.724284 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13633.061807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13756.427376 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13496.724284 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13633.061807 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6850 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 406 # 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5677452 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11568850 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5891398 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5677452 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11568850 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094420 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089820 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092163 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094420 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089820 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092163 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094420 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089820 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.092163 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13768.921663 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13472.716436 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13627.252714 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13768.921663 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13472.716436 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13627.252714 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13768.921663 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13472.716436 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13627.252714 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6572 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 144 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 397 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.554156 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 144 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42606 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38478 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 81084 # 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number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 516672 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 467587 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984259 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6254333936 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5558733090 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11813067026 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6254333936 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5558733090 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11813067026 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6254333936 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5558733090 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11813067026 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9017250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9017250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9017250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9017250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087958 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082013 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085030 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087958 # 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average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12001.990356 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12105.037502 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11888.125825 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12001.990356 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42425 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38728 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 81153 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 42425 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 38728 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 81153 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 42425 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 38728 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 81153 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 513841 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 471221 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 985062 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 513841 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 471221 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 985062 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 513841 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 471221 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 985062 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6224566388 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5591223594 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11815789982 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6224566388 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5591223594 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11815789982 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6224566388 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5591223594 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11815789982 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8993000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8993000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8993000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8993000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085148 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085148 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087219 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082999 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085148 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11994.970857 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11994.970857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11994.970857 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643844 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993221 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21529454 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644356 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.412359 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43687250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 256.274589 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.718633 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.500536 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499450 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 643424 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993257 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21526419 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 643936 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.429439 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43468250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.820066 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.173192 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497695 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502291 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101648096 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101648096 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7014056 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6760706 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13774762 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3747600 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3513292 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7260892 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116614 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126440 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243054 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 119391 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 128245 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247636 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10761656 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10273998 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21035654 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10761656 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10273998 # number of overall hits -system.cpu0.dcache.overall_hits::total 21035654 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 333491 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 414863 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 748354 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1635288 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1327358 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2962646 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7514 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6065 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13579 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1968779 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1742221 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3711000 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1968779 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1742221 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711000 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5348440293 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6102853229 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11451293522 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 83999211786 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64837852526 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 148837064312 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 107360498 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 81153996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188514494 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 168501 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 89347652079 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 70940705755 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 160288357834 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 89347652079 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 70940705755 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 160288357834 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7347547 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7175569 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14523116 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5382888 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4840650 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223538 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124128 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132505 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256633 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119397 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 128251 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247648 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12730435 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12016219 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24746654 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12730435 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12016219 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24746654 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045388 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057816 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051528 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.303794 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.274211 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289787 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060534 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045772 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052912 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000047 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.154651 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.144989 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149960 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.154651 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.144989 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149960 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16037.735030 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.526677 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15301.974095 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51366.616636 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 48847.298563 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50237.883403 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14288.062018 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13380.708326 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13882.796524 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 101635836 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 101635836 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7044250 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6727132 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13771382 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3751595 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3509581 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261176 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116856 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126271 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243127 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 119516 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 128128 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247644 # 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number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6018353236 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11389312854 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84349105443 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64286693931 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 148635799374 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105098996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82392993 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 187491989 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 91000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 89720065061 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 70305047167 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 160025112228 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 89720065061 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 70305047167 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 160025112228 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7379776 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7140342 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14520118 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5372501 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4851051 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10223552 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132401 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119518 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 128133 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247651 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12752277 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11991393 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24743670 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12752277 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11991393 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24743670 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045466 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057870 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051565 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.301704 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.276532 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289760 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059532 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046299 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052705 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000039 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000028 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.153418 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.146328 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149982 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.153418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.146328 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149982 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16007.580986 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14564.877994 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15211.386729 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 52038.246168 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47922.572947 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50174.521862 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14208.327160 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13440.945024 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13860.574333 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14041.750000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45382.265901 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40718.545899 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43192.766864 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45382.265901 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40718.545899 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43192.766864 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 37128 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 22269 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3473 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 273 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.690469 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 81.571429 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45859.025543 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40067.161629 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43120.528895 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45859.025543 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40067.161629 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43120.528895 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 36695 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25289 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3463 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 288 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.596304 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 87.809028 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608227 # number of writebacks -system.cpu0.dcache.writebacks::total 608227 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 146313 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 215949 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362262 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1499850 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1213774 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2713624 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 765 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 618 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1383 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1646163 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1429723 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3075886 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1646163 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1429723 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3075886 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187178 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 198914 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386092 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 135438 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 113584 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6749 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5447 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12196 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 322616 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 312498 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635114 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 322616 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 312498 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635114 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2596085748 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2657791594 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5253877342 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6365986816 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5155346718 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11521333534 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84972752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62985504 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147958256 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 144499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8962072564 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7813138312 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16775210876 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8962072564 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7813138312 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16775210876 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91546998750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90791256750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182338255500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13710487847 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13068639684 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26779127531 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105257486597 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103859896434 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209117383031 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025475 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027721 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026585 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025161 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023465 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054371 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041108 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047523 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000047 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025342 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026006 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025342 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026006 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13869.609399 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.510975 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13607.837878 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47002.959406 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45387.965893 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46266.328011 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12590.421099 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11563.338351 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.703509 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 607907 # number of writebacks +system.cpu0.dcache.writebacks::total 607907 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 148329 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 214670 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362999 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1486511 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1226891 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2713402 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 703 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 661 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1364 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1634840 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1441561 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3076401 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1634840 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1441561 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3076401 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187197 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 198540 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 385737 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 134395 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 114579 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248974 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5469 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12163 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 321592 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 313119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 634711 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 321592 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 313119 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 634711 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2595681199 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2634071602 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5229752801 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6377279279 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5102642760 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11479922039 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 83521753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63731007 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147252760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 77000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8972960478 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7736714362 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16709674840 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8972960478 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7736714362 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16709674840 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91614967500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90722197000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182337164500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13706653581 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13072228739 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26778882320 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105321621081 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103794425739 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209116046820 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025366 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027805 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025015 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023619 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053874 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041306 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047391 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000039 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025651 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025651 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13866.040583 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13267.208633 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13557.819968 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47451.759954 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44533.839185 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46108.919160 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12477.106812 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11653.137137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12106.615144 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12041.583333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7323132 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5902490 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 346200 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4511574 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3765481 # Number of BTB hits +system.cpu1.branchPred.lookups 7300035 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5887077 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 345091 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4651296 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3771120 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 83.462690 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 676459 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34463 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.076758 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 673548 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34495 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1738,25 +1726,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25506602 # DTB read hits -system.cpu1.dtb.read_misses 36488 # DTB read misses -system.cpu1.dtb.write_hits 5558527 # DTB write hits -system.cpu1.dtb.write_misses 8439 # DTB write misses +system.cpu1.dtb.read_hits 25450161 # DTB read hits +system.cpu1.dtb.read_misses 36388 # DTB read misses +system.cpu1.dtb.write_hits 5568332 # DTB write hits +system.cpu1.dtb.write_misses 8538 # DTB write misses system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5463 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2276 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2244 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 247 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25543090 # DTB read accesses -system.cpu1.dtb.write_accesses 5566966 # DTB write accesses +system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25486549 # DTB read accesses +system.cpu1.dtb.write_accesses 5576870 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31065129 # DTB hits -system.cpu1.dtb.misses 44927 # DTB misses -system.cpu1.dtb.accesses 31110056 # DTB accesses +system.cpu1.dtb.hits 31018493 # DTB hits +system.cpu1.dtb.misses 44926 # DTB misses +system.cpu1.dtb.accesses 31063419 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1778,294 +1766,329 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5703436 # ITB inst hits -system.cpu1.itb.inst_misses 7020 # ITB inst misses +system.cpu1.itb.inst_hits 5679651 # ITB inst hits +system.cpu1.itb.inst_misses 6870 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2688 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2692 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1570 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5710456 # ITB inst accesses -system.cpu1.itb.hits 5703436 # DTB hits -system.cpu1.itb.misses 7020 # DTB misses -system.cpu1.itb.accesses 5710456 # DTB accesses -system.cpu1.numCycles 237056909 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5686521 # ITB inst accesses +system.cpu1.itb.hits 5679651 # DTB hits +system.cpu1.itb.misses 6870 # DTB misses +system.cpu1.itb.accesses 5686521 # DTB accesses +system.cpu1.numCycles 236844574 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14419718 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45234990 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7323132 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4441940 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9947853 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2287798 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84999 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49482147 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1272 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 44871 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1235484 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 189 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5701379 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 352457 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3064 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76794959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.726229 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.078871 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14466322 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45074741 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7300035 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4444668 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9928510 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2284755 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 83810 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49428019 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1865 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 44064 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1232877 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5677454 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 353029 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3058 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76760101 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.724873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076516 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66855647 87.06% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 632615 0.82% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 843009 1.10% 88.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1133482 1.48% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1002056 1.30% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 554704 0.72% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1272745 1.66% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 372184 0.48% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4128517 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66839787 87.08% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 628644 0.82% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 837705 1.09% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1128430 1.47% 90.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1025116 1.34% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 549692 0.72% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1265677 1.65% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 371391 0.48% 94.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4113659 5.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76794959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030892 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190819 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15530724 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50222847 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8895356 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 650267 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1493551 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 963840 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85500 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53154493 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286161 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1493551 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16374919 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19306160 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27715779 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8656578 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3245827 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50687701 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 339 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 605911 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2002092 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 648 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53113804 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 234485879 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 214384735 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5365 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39540919 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13572884 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 579809 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 536931 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6499660 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9772559 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6360216 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 888468 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1099515 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47171321 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 962588 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 61070577 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91971 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9248404 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23463374 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 229936 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76794959 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.795242 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.505673 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76760101 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030822 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190314 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15575790 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50164874 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8875530 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 651724 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1490012 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 958602 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85804 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53028773 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286820 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1490012 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16419373 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19259514 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27698423 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8639214 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3251470 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50560580 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 221 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 607469 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2007282 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 572 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 52946210 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 233908561 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 213841042 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5698 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39345682 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13600527 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 580708 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 537933 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6505084 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9729570 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6369599 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 877361 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1114434 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47034811 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 984793 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60942495 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91566 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9279731 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23349761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 250555 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76760101 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.793935 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.504235 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54534134 71.01% 71.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7328500 9.54% 80.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3483988 4.54% 85.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2874889 3.74% 88.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6131286 7.98% 96.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1377966 1.79% 98.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 776904 1.01% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 225300 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61992 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54532875 71.04% 71.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7326090 9.54% 80.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3469207 4.52% 85.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2884980 3.76% 88.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6118042 7.97% 96.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1370862 1.79% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 772587 1.01% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 222613 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62845 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76794959 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76760101 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29712 0.67% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4180230 94.88% 95.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 195658 4.44% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29035 0.66% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 5 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4177111 94.84% 95.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12649 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28971083 47.44% 47.46% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46630 0.08% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 875 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26162080 42.84% 90.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5877234 9.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13548 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28887832 47.40% 47.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46127 0.08% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 887 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26105748 42.84% 90.34% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5888317 9.66% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 61070577 # Type of FU issued -system.cpu1.iq.rate 0.257620 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4405603 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072140 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203466895 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57390461 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42382296 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11528 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6422 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5160 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65457468 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6063 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 311906 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60942495 # Type of FU issued +system.cpu1.iq.rate 0.257310 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4404233 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072269 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203173539 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57307144 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42269826 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12116 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6726 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5381 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65326800 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6380 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 306796 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1999074 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3048 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15122 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 750838 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1984154 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3003 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15089 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 749009 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17042744 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332080 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17027364 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 331342 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1493551 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14864582 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 222698 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48241525 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96453 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9772559 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6360216 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 687199 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 48610 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15122 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 168053 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 134565 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 302618 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60042253 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25845364 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1028324 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1490012 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14823463 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 222107 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48121220 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96425 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9729570 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6369599 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 709638 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 48371 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4239 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15089 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 167591 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133565 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 301156 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59912848 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25789830 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1029647 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 107616 # number of nop insts executed -system.cpu1.iew.exec_refs 31671376 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5872062 # Number of branches executed -system.cpu1.iew.exec_stores 5826012 # Number of stores executed -system.cpu1.iew.exec_rate 0.253282 # Inst execution rate -system.cpu1.iew.wb_sent 59578158 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42387456 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23643387 # num instructions producing a value -system.cpu1.iew.wb_consumers 43005248 # num instructions consuming a value +system.cpu1.iew.exec_nop 101616 # number of nop insts executed +system.cpu1.iew.exec_refs 31626536 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5854246 # Number of branches executed +system.cpu1.iew.exec_stores 5836706 # Number of stores executed +system.cpu1.iew.exec_rate 0.252963 # Inst execution rate +system.cpu1.iew.wb_sent 59450905 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42275207 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23556720 # num instructions producing a value +system.cpu1.iew.wb_consumers 42880647 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178807 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.549779 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178493 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549356 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9166908 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 732652 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 262014 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75301408 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.513681 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.486972 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9147109 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 734238 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 260548 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75270089 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.511960 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.483838 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60995111 81.00% 81.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7470337 9.92% 90.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1928698 2.56% 93.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1074141 1.43% 94.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 820415 1.09% 96.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 494186 0.66% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 699344 0.93% 97.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 371316 0.49% 98.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1447860 1.92% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60996835 81.04% 81.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7463530 9.92% 90.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1923766 2.56% 93.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1066165 1.42% 94.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 822611 1.09% 96.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 493470 0.66% 96.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 696092 0.92% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 369554 0.49% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1438066 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75301408 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30565527 # Number of instructions committed -system.cpu1.commit.committedOps 38680902 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75270089 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30381625 # Number of instructions committed +system.cpu1.commit.committedOps 38535309 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13382863 # Number of memory references committed -system.cpu1.commit.loads 7773485 # Number of loads committed -system.cpu1.commit.membars 194338 # Number of memory barriers committed -system.cpu1.commit.branches 5145142 # Number of branches committed -system.cpu1.commit.fp_insts 5126 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34406663 # Number of committed integer instructions. -system.cpu1.commit.function_calls 483721 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1447860 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13366006 # Number of memory references committed +system.cpu1.commit.loads 7745416 # Number of loads committed +system.cpu1.commit.membars 193947 # Number of memory barriers committed +system.cpu1.commit.branches 5114433 # Number of branches committed +system.cpu1.commit.fp_insts 5338 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34292499 # Number of committed integer instructions. +system.cpu1.commit.function_calls 482077 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 25125071 65.20% 65.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 43345 0.11% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 887 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 7745416 20.10% 85.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 5620590 14.59% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 38535309 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1438066 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120827478 # The number of ROB reads -system.cpu1.rob.rob_writes 97232532 # The number of ROB writes -system.cpu1.timesIdled 865086 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160261950 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2316983227 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30492768 # Number of Instructions Simulated -system.cpu1.committedOps 38608143 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30492768 # Number of Instructions Simulated -system.cpu1.cpi 7.774201 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.774201 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.128631 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.128631 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 272500909 # number of integer regfile reads -system.cpu1.int_regfile_writes 43779735 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45015 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42294 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133085319 # number of misc regfile reads -system.cpu1.misc_regfile_writes 592959 # number of misc regfile writes +system.cpu1.rob.rob_reads 120626402 # The number of ROB reads +system.cpu1.rob.rob_writes 96898257 # The number of ROB writes +system.cpu1.timesIdled 866184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160084473 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2317121408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30313431 # Number of Instructions Simulated +system.cpu1.committedOps 38467115 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30313431 # Number of Instructions Simulated +system.cpu1.cpi 7.813189 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.813189 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127989 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127989 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271901021 # number of integer regfile reads +system.cpu1.int_regfile_writes 43646883 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45279 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42402 # number of floating regfile writes +system.cpu1.misc_regfile_reads 133121444 # number of misc regfile reads +system.cpu1.misc_regfile_writes 593543 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2082,17 +2105,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736889440801 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736889440801 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1734475259291 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1734475259291 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83061 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83062 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 094868576..cce768d16 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,147 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629695 # Number of seconds simulated -sim_ticks 2629694709500 # Number of ticks simulated -final_tick 2629694709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.631271 # Number of seconds simulated +sim_ticks 2631271319500 # Number of ticks simulated +final_tick 2631271319500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 422902 # Simulator instruction rate (inst/s) -host_op_rate 538135 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18468797106 # Simulator tick rate (ticks/s) -host_mem_usage 466428 # Number of bytes of host memory used -host_seconds 142.39 # Real time elapsed on the host -sim_insts 60215255 # Number of instructions simulated -sim_ops 76622777 # Number of ops (including micro ops) simulated +host_inst_rate 354699 # Simulator instruction rate (inst/s) +host_op_rate 451347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15499898557 # Simulator tick rate (ticks/s) +host_mem_usage 465856 # Number of bytes of host memory used +host_seconds 169.76 # Real time elapsed on the host +sim_insts 60213853 # Number of instructions simulated +sim_ops 76620850 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 291720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4684888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 299528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4518680 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 412356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4375828 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 291720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 412356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704076 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3689664 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1522876 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1493404 # Number of bytes written to this memory -system.physmem.bytes_written::total 6705944 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 404800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4542464 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 299528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 404800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1524152 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1491920 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706696 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73237 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70640 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68407 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57651 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380719 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373351 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811721 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47251210 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 70976 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690868 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381038 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372980 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811684 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47222898 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 110933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1781533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1717299 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 156808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1664006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50964562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 110933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 156808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267741 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1403077 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 579108 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 567900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1403077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47251210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 153842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1726338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50934284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 153842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267676 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402601 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 579245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2548842 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47222898 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 110933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2360641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2296545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 156808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2231906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53514647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690908 # Number of read requests accepted -system.physmem.writeReqs 811721 # Number of write requests accepted -system.physmem.readBursts 15690908 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811721 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004216192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1920 # Total number of bytes read from write queue -system.physmem.bytesWritten 6737024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6705944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 30 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706455 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu1.inst 153842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2293334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53483126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690868 # Number of read requests accepted +system.physmem.writeReqs 811684 # Number of write requests accepted +system.physmem.readBursts 15690868 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811684 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004214848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6724608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706598 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980391 # Per bank write bursts system.physmem.perBankRdBursts::1 980206 # Per bank write bursts -system.physmem.perBankRdBursts::2 980218 # Per bank write bursts -system.physmem.perBankRdBursts::3 980431 # Per bank write bursts +system.physmem.perBankRdBursts::2 980222 # Per bank write bursts +system.physmem.perBankRdBursts::3 980428 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts system.physmem.perBankRdBursts::5 980708 # Per bank write bursts -system.physmem.perBankRdBursts::6 980610 # Per bank write bursts -system.physmem.perBankRdBursts::7 980421 # Per bank write bursts +system.physmem.perBankRdBursts::6 980611 # Per bank write bursts +system.physmem.perBankRdBursts::7 980420 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts -system.physmem.perBankRdBursts::11 979558 # Per bank write bursts -system.physmem.perBankRdBursts::12 980154 # Per bank write bursts -system.physmem.perBankRdBursts::13 980093 # Per bank write bursts -system.physmem.perBankRdBursts::14 980167 # Per bank write bursts +system.physmem.perBankRdBursts::11 979544 # Per bank write bursts +system.physmem.perBankRdBursts::12 980153 # Per bank write bursts +system.physmem.perBankRdBursts::13 980076 # Per bank write bursts +system.physmem.perBankRdBursts::14 980177 # Per bank write bursts system.physmem.perBankRdBursts::15 980110 # Per bank write bursts -system.physmem.perBankWrBursts::0 6645 # Per bank write bursts -system.physmem.perBankWrBursts::1 6506 # Per bank write bursts -system.physmem.perBankWrBursts::2 6513 # Per bank write bursts -system.physmem.perBankWrBursts::3 6561 # Per bank write bursts -system.physmem.perBankWrBursts::4 6643 # Per bank write bursts -system.physmem.perBankWrBursts::5 6949 # Per bank write bursts -system.physmem.perBankWrBursts::6 6933 # Per bank write bursts -system.physmem.perBankWrBursts::7 6786 # Per bank write bursts -system.physmem.perBankWrBursts::8 6904 # Per bank write bursts -system.physmem.perBankWrBursts::9 6725 # Per bank write bursts -system.physmem.perBankWrBursts::10 6221 # Per bank write bursts -system.physmem.perBankWrBursts::11 6029 # Per bank write bursts -system.physmem.perBankWrBursts::12 6513 # Per bank write bursts -system.physmem.perBankWrBursts::13 6297 # Per bank write bursts +system.physmem.perBankWrBursts::0 6626 # Per bank write bursts +system.physmem.perBankWrBursts::1 6496 # Per bank write bursts +system.physmem.perBankWrBursts::2 6497 # Per bank write bursts +system.physmem.perBankWrBursts::3 6558 # Per bank write bursts +system.physmem.perBankWrBursts::4 6634 # Per bank write bursts +system.physmem.perBankWrBursts::5 6937 # Per bank write bursts +system.physmem.perBankWrBursts::6 6920 # Per bank write bursts +system.physmem.perBankWrBursts::7 6772 # Per bank write bursts +system.physmem.perBankWrBursts::8 6893 # Per bank write bursts +system.physmem.perBankWrBursts::9 6718 # Per bank write bursts +system.physmem.perBankWrBursts::10 6212 # Per bank write bursts +system.physmem.perBankWrBursts::11 6014 # Per bank write bursts +system.physmem.perBankWrBursts::12 6499 # Per bank write bursts +system.physmem.perBankWrBursts::13 6274 # Per bank write bursts system.physmem.perBankWrBursts::14 6516 # Per bank write bursts -system.physmem.perBankWrBursts::15 6525 # Per bank write bursts +system.physmem.perBankWrBursts::15 6506 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2629690290000 # Total gap between requests +system.physmem.totGap 2631266900000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6718 # Read request sizes (log2) +system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152158 # Read request sizes (log2) +system.physmem.readPktSize::6 152172 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754070 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57651 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1128915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 971082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 971066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 973046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 971647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 972454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2865167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2865325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3808659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 25323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 23577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 23318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 22230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 22150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57666 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1139961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 987606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1093203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 997403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1062031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2774379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2684271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3510460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 111897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 101929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 96137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 92760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -157,60 +169,60 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 318 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -221,373 +233,350 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 990183 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1014.719065 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1002.794597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 86.877825 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3622 0.37% 0.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3291 0.33% 0.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1715 0.17% 0.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1178 0.12% 0.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 920 0.09% 1.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 703 0.07% 1.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 532 0.05% 1.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 420 0.04% 1.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 977802 98.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 990183 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4537 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3458.425832 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 54557.622307 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 4511 99.43% 99.43% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.18% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 4 0.09% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 2 0.04% 99.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 3 0.07% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.13% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1040545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.548041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.383017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.411888 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22983 2.21% 2.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22832 2.19% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9281 0.89% 5.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2277 0.22% 5.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2320 0.22% 5.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1623 0.16% 5.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9470 0.91% 6.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 703 0.07% 6.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 969056 93.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1040545 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6005 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2612.962531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47489.703553 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 5977 99.53% 99.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 11 0.18% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.77% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 3 0.05% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4537 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4537 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.201675 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.361663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.873768 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 5 0.11% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 7 0.15% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 5 0.11% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 2 0.04% 0.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.04% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 4 0.09% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 6 0.13% 0.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.07% 0.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 3 0.07% 0.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.07% 0.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.07% 0.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.04% 0.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 4 0.09% 1.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 7 0.15% 1.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 17 0.37% 1.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1491 32.86% 34.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 339 7.47% 41.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 208 4.58% 46.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1050 23.14% 69.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16 0.35% 70.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 12 0.26% 70.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.44% 70.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 24 0.53% 71.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.40% 71.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 14 0.31% 71.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 18 0.40% 72.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 18 0.40% 72.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 19 0.42% 73.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 13 0.29% 73.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 11 0.24% 73.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 12 0.26% 73.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.24% 74.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.07% 74.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.04% 74.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.02% 74.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1015 22.37% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 76 1.68% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 13 0.29% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 42 0.93% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 5 0.11% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 5 0.11% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 5 0.11% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4537 # Writes before turning the bus around for reads -system.physmem.totQLat 592300556750 # Total ticks spent queuing -system.physmem.totMemAccLat 700300341750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454390000 # Total ticks spent in databus transfers -system.physmem.totBankLat 29545395000 # Total ticks spent accessing banks -system.physmem.avgQLat 37748.08 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1882.97 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6005 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.497419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.315574 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.169730 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 7 0.12% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 6 0.10% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 6 0.10% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 4 0.07% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 3 0.05% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.02% 0.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.05% 0.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 3 0.05% 0.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 4 0.07% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 4 0.07% 0.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 8 0.13% 0.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 3 0.05% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 4 0.07% 0.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 16 0.27% 1.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1890 31.47% 32.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 59 0.98% 33.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3765 62.70% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 21 0.35% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 14 0.23% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.27% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 19 0.32% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 20 0.33% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 12 0.20% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.10% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 23 0.38% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 21 0.35% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 18 0.30% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.23% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 10 0.17% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 11 0.18% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 11 0.18% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6005 # Writes before turning the bus around for reads +system.physmem.totQLat 402822623250 # Total ticks spent queuing +system.physmem.totMemAccLat 697026192000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454285000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25672.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44631.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44422.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.89 # Average write queue length when enqueuing -system.physmem.readRowHits 14676487 # Number of row buffer hits during reads -system.physmem.writeRowHits 89750 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.26 # Row buffer hit rate for writes -system.physmem.avgGap 159349.78 # Average gap between requests -system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.16 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54426652 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743677 # Transaction distribution -system.membus.trans_dist::ReadResp 16743677 # Transaction distribution -system.membus.trans_dist::WriteReq 763441 # Transaction distribution -system.membus.trans_dist::WriteResp 763441 # Transaction distribution -system.membus.trans_dist::Writeback 57651 # Transaction distribution +system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.68 # Average write queue length when enqueuing +system.physmem.readRowHits 14667283 # Number of row buffer hits during reads +system.physmem.writeRowHits 88101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.84 # Row buffer hit rate for writes +system.physmem.avgGap 159446.06 # Average gap between requests +system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2257272287500 # Time in different power states +system.physmem.memoryStateTime::REF 87863880000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 286133845000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 54394584 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743630 # Transaction distribution +system.membus.trans_dist::ReadResp 16743630 # Transaction distribution +system.membus.trans_dist::WriteReq 763389 # Transaction distribution +system.membus.trans_dist::WriteResp 763389 # Transaction distribution +system.membus.trans_dist::Writeback 57666 # Transaction distribution system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131342 # Transaction distribution -system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.trans_dist::ReadExReq 131349 # Transaction distribution +system.membus.trans_dist::ReadExResp 131349 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892577 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892408 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279372 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343436 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16470928 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18869222 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870654 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143125478 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143125478 # Total data (bytes) +system.membus.tot_pkt_size::total 143126910 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143126910 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225762000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225776000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3755500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3753500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171181500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171055500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4987933108 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4987830629 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38819144750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 38455776750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62041 # number of replacements -system.l2c.tags.tagsinuse 51600.507824 # Cycle average of tags in use -system.l2c.tags.total_refs 1699332 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127423 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.336148 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574803290500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38204.625202 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2677.995545 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3048.557344 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4342.999627 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3326.329216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.582956 # Average percentage of cache occupancy +system.l2c.tags.replacements 62060 # number of replacements +system.l2c.tags.tagsinuse 51620.522057 # Cycle average of tags in use +system.l2c.tags.total_refs 1699511 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127448 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.334937 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2576403565500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38224.293292 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2572.111888 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3079.413643 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4449.101058 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3295.601290 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583256 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.040863 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046517 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.039247 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046988 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.066269 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050756 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787361 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65382 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6447 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56751 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997650 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17277037 # Number of tag accesses -system.l2c.tags.data_accesses 17277037 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9996 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3617 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 411271 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183421 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9883 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 433200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 187065 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241955 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596489 # number of Writeback hits -system.l2c.Writeback_hits::total 596489 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.067888 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050287 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787667 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65388 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6611 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56587 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.997742 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17278044 # Number of tag accesses +system.l2c.tags.data_accesses 17278044 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 10108 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3664 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 418356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 187332 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9807 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3568 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 426125 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 183124 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242084 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596476 # number of Writeback hits +system.l2c.Writeback_hits::total 596476 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55903 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58636 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114539 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9996 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 411271 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239324 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9883 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 433200 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 245701 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356494 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9996 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3617 # number of overall hits -system.l2c.overall_hits::cpu0.inst 411271 # number of overall hits -system.l2c.overall_hits::cpu0.data 239324 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9883 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3502 # number of overall hits -system.l2c.overall_hits::cpu1.inst 433200 # number of overall hits -system.l2c.overall_hits::cpu1.data 245701 # number of overall hits -system.l2c.overall_hits::total 1356494 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 57771 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56762 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114533 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 10108 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3664 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 418356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 245103 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9807 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3568 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 426125 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 239886 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356617 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 10108 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3664 # number of overall hits +system.l2c.overall_hits::cpu0.inst 418356 # number of overall hits +system.l2c.overall_hits::cpu0.data 245103 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9807 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3568 # number of overall hits +system.l2c.overall_hits::cpu1.inst 426125 # number of overall hits +system.l2c.overall_hits::cpu1.data 239886 # number of overall hits +system.l2c.overall_hits::total 1356617 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4144 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5204 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4266 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5262 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6442 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5023 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20816 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1406 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1477 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2883 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 68791 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 64185 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59680.965759 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.677048 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.346861 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57369.202308 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57588.717582 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57475.158179 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.814919 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.384562 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56810.083092 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57853.998478 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57134.782609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57158.678388 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57162.247256 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57804.054054 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57716.052382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57537.623066 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57145.430183 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58025.807203 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57988.084297 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57853.998478 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57134.782609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57158.678388 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57162.247256 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -729,7 +715,6 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate @@ -739,39 +724,39 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52790847 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471761 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471761 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763441 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763441 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596489 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247515 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754007 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20046 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50514 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549580 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54750240 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83796742 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28484 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138654986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138654986 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 168824 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808734000 # Layer occupancy (ticks) +system.toL2Bus.throughput 52759012 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471877 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471877 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596476 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2915 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2915 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247510 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247510 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725028 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753762 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20291 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50582 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549663 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54751132 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83793442 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138653174 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138653174 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 170100 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808682000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865148750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865303000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420266392 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420412121 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12925000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13057000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30634250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30666250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48160270 # Throughput (bytes/s) +system.iobus.throughput 48131413 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution @@ -881,7 +866,7 @@ system.iobus.reqLayer25.occupancy 15532032000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38823243250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 39139813250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -906,25 +891,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7344844 # DTB read hits -system.cpu0.dtb.read_misses 6860 # DTB read misses -system.cpu0.dtb.write_hits 5551128 # DTB write hits -system.cpu0.dtb.write_misses 1832 # DTB write misses -system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7447963 # DTB read hits +system.cpu0.dtb.read_misses 7119 # DTB read misses +system.cpu0.dtb.write_hits 5549645 # DTB write hits +system.cpu0.dtb.write_misses 1815 # DTB write misses +system.cpu0.dtb.flush_tlb 2495 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6351 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6552 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 220 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7351704 # DTB read accesses -system.cpu0.dtb.write_accesses 5552960 # DTB write accesses +system.cpu0.dtb.perms_faults 230 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7455082 # DTB read accesses +system.cpu0.dtb.write_accesses 5551460 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12895972 # DTB hits -system.cpu0.dtb.misses 8692 # DTB misses -system.cpu0.dtb.accesses 12904664 # DTB accesses +system.cpu0.dtb.hits 12997608 # DTB hits +system.cpu0.dtb.misses 8934 # DTB misses +system.cpu0.dtb.accesses 13006542 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -946,125 +931,160 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30211154 # ITB inst hits -system.cpu0.itb.inst_misses 3603 # ITB inst misses +system.cpu0.itb.inst_hits 30500446 # ITB inst hits +system.cpu0.itb.inst_misses 3756 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2495 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2758 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2854 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30214757 # ITB inst accesses -system.cpu0.itb.hits 30211154 # DTB hits -system.cpu0.itb.misses 3603 # DTB misses -system.cpu0.itb.accesses 30214757 # DTB accesses -system.cpu0.numCycles 2627736532 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30504202 # ITB inst accesses +system.cpu0.itb.hits 30500446 # DTB hits +system.cpu0.itb.misses 3756 # DTB misses +system.cpu0.itb.accesses 30504202 # DTB accesses +system.cpu0.numCycles 2629256644 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29624937 # Number of instructions committed -system.cpu0.committedOps 37728426 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34074958 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4583 # Number of float alu accesses -system.cpu0.num_func_calls 1045164 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3935196 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34074958 # number of integer instructions -system.cpu0.num_fp_insts 4583 # number of float instructions -system.cpu0.num_int_register_reads 197582111 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36713164 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3288 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written -system.cpu0.num_mem_refs 13470170 # number of memory refs -system.cpu0.num_load_insts 7667939 # Number of load instructions -system.cpu0.num_store_insts 5802231 # Number of store instructions -system.cpu0.num_idle_cycles 2282002616.045546 # Number of idle cycles -system.cpu0.num_busy_cycles 345733915.954454 # Number of busy cycles -system.cpu0.not_idle_fraction 0.131571 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.868429 # Percentage of idle cycles -system.cpu0.Branches 5074688 # Number of branches fetched +system.cpu0.committedInsts 29876886 # Number of instructions committed +system.cpu0.committedOps 37981807 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34283991 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4842 # Number of float alu accesses +system.cpu0.num_func_calls 1058651 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3976280 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34283991 # number of integer instructions +system.cpu0.num_fp_insts 4842 # number of float instructions +system.cpu0.num_int_register_reads 198984803 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36984019 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3491 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1354 # number of times the floating registers were written +system.cpu0.num_mem_refs 13572889 # number of memory refs +system.cpu0.num_load_insts 7771976 # Number of load instructions +system.cpu0.num_store_insts 5800913 # Number of store instructions +system.cpu0.num_idle_cycles 2280913483.245505 # Number of idle cycles +system.cpu0.num_busy_cycles 348343160.754495 # Number of busy cycles +system.cpu0.not_idle_fraction 0.132487 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.867513 # Percentage of idle cycles +system.cpu0.Branches 5129174 # Number of branches fetched +system.cpu0.op_class::No_OpClass 12846 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 24984996 64.70% 64.73% # Class of executed instruction +system.cpu0.op_class::IntMult 44336 0.11% 64.85% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 930 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::MemRead 7771976 20.13% 84.98% # Class of executed instruction +system.cpu0.op_class::MemWrite 5800913 15.02% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 38615997 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856147 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.849495 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60652706 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856659 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.801458 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20216402250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 158.742483 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 352.107012 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.310044 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.687709 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997753 # 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miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014075 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013927 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013775 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014075 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013927 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13629.900323 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13915.826171 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.929879 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13629.900323 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13915.826171 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13776.929879 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13769.143942 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1073,169 +1093,165 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 416146 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 440514 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856660 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 416146 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 440514 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856660 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 416146 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 440514 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856660 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4838197500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5246649750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10084847250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4838197500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5246649750 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4924249000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5154307000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10078556000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4924249000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5154307000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10078556000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 441046000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 441046000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 441046000 # 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average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627716 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.875867 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23661613 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628228 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.664053 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 671680250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 152.516115 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 359.359751 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.297883 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.701875 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 627683 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.876343 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23661001 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628195 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.665058 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 147.481748 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 364.394596 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.288050 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.711708 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999758 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97787592 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97787592 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6450546 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6749057 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13199603 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4919460 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 5055668 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9975128 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118398 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117802 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236200 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124425 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123348 # 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miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026897 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027205 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024995 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023998 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048462 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044947 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046712 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026433 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025657 # miss rate for demand accesses +system.cpu0.dcache.tags.tag_accesses 97784979 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97784979 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6545596 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6653610 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13199206 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4917377 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 5057557 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974934 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 119123 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117066 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236189 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125242 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 122515 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247757 # 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average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45165.669792 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44978.727232 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.798726 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14364.491557 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13876.307373 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26896.913371 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27144.523156 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 27019.869173 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26896.913371 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27144.523156 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27019.869173 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1244,77 +1260,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596489 # number of writebacks -system.cpu0.dcache.writebacks::total 596489 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182595 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186544 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369139 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126114 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 124310 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250424 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6030 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5544 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11574 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 308709 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 310854 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619563 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 308709 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 310854 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619563 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2355168000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2386207250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741375250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5543852798 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5262622685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10806475483 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68990000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68208750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137198750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7899020798 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7648829935 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15547850733 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7899020798 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7648829935 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15547850733 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90318421750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91762441000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080862750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13218125626 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13022508499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26240634125 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103536547376 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104784949499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208321496875 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027528 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026897 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027205 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024995 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023998 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048462 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044947 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046712 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026433 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025657 # mshr miss rate for demand accesses +system.cpu0.dcache.writebacks::writebacks 596476 # number of writebacks +system.cpu0.dcache.writebacks::total 596476 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186473 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182643 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369116 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 125422 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 125003 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250425 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6121 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5448 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11569 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 311895 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 307646 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619541 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 311895 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 307646 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619541 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2396807750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2338699250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4735507000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5342161454 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5370757779 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10712919233 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70030750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67311250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137342000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7738969204 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7709457029 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15448426233 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7738969204 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7709457029 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15448426233 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90834275250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91243928750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078204000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13255943399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12983118997 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239062396 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104090218649 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104227047747 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317266396 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027699 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026717 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024872 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024120 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048873 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044468 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046695 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026433 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025657 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12898.315945 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12791.659072 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12844.417008 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43959.059248 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42334.668852 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43152.714927 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.127695 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12303.165584 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.047866 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12853.376896 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12804.757094 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12829.319238 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42593.495990 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42965.031071 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42778.952712 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.063552 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12355.222100 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11871.553289 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1348,25 +1364,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7655819 # DTB read hits -system.cpu1.dtb.read_misses 7243 # DTB read misses -system.cpu1.dtb.write_hits 5681899 # DTB write hits -system.cpu1.dtb.write_misses 1828 # DTB write misses +system.cpu1.dtb.read_hits 7552227 # DTB read hits +system.cpu1.dtb.read_misses 6971 # DTB read misses +system.cpu1.dtb.write_hits 5683121 # DTB write hits +system.cpu1.dtb.write_misses 1859 # DTB write misses system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6603 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7663062 # DTB read accesses -system.cpu1.dtb.write_accesses 5683727 # DTB write accesses +system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7559198 # DTB read accesses +system.cpu1.dtb.write_accesses 5684980 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13337718 # DTB hits -system.cpu1.dtb.misses 9071 # DTB misses -system.cpu1.dtb.accesses 13346789 # DTB accesses +system.cpu1.dtb.hits 13235348 # DTB hits +system.cpu1.dtb.misses 8830 # DTB misses +system.cpu1.dtb.accesses 13244178 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1388,50 +1404,85 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 31298229 # ITB inst hits -system.cpu1.itb.inst_misses 3696 # ITB inst misses +system.cpu1.itb.inst_hits 31007524 # ITB inst hits +system.cpu1.itb.inst_misses 3606 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2898 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2820 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31301925 # ITB inst accesses -system.cpu1.itb.hits 31298229 # DTB hits -system.cpu1.itb.misses 3696 # DTB misses -system.cpu1.itb.accesses 31301925 # DTB accesses -system.cpu1.numCycles 2631652887 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31011130 # ITB inst accesses +system.cpu1.itb.hits 31007524 # DTB hits +system.cpu1.itb.misses 3606 # DTB misses +system.cpu1.itb.accesses 31011130 # DTB accesses +system.cpu1.numCycles 2633285995 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30590318 # Number of instructions committed -system.cpu1.committedOps 38894351 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35148183 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5686 # Number of float alu accesses -system.cpu1.num_func_calls 1095318 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4014750 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35148183 # number of integer instructions -system.cpu1.num_fp_insts 5686 # number of float instructions -system.cpu1.num_int_register_reads 203876321 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37823170 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4205 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1482 # number of times the floating registers were written -system.cpu1.num_mem_refs 13931138 # number of memory refs -system.cpu1.num_load_insts 7996929 # Number of load instructions -system.cpu1.num_store_insts 5934209 # Number of store instructions -system.cpu1.num_idle_cycles 2293790821.520695 # Number of idle cycles -system.cpu1.num_busy_cycles 337862065.479305 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128384 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871616 # Percentage of idle cycles -system.cpu1.Branches 5235663 # Number of branches fetched +system.cpu1.committedInsts 30336967 # Number of instructions committed +system.cpu1.committedOps 38639043 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34937438 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5427 # Number of float alu accesses +system.cpu1.num_func_calls 1081754 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3973481 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34937438 # number of integer instructions +system.cpu1.num_fp_insts 5427 # number of float instructions +system.cpu1.num_int_register_reads 202463130 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37550545 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4002 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1426 # number of times the floating registers were written +system.cpu1.num_mem_refs 13827657 # number of memory refs +system.cpu1.num_load_insts 7892397 # Number of load instructions +system.cpu1.num_store_insts 5935260 # Number of store instructions +system.cpu1.num_idle_cycles 2291893093.755996 # Number of idle cycles +system.cpu1.num_busy_cycles 341392901.244004 # Number of busy cycles +system.cpu1.not_idle_fraction 0.129645 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.870355 # Percentage of idle cycles +system.cpu1.Branches 5180924 # Number of branches fetched +system.cpu1.op_class::No_OpClass 15672 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 25411566 64.66% 64.70% # Class of executed instruction +system.cpu1.op_class::IntMult 43588 0.11% 64.81% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1181 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::MemRead 7892397 20.08% 84.90% # Class of executed instruction +system.cpu1.op_class::MemWrite 5935260 15.10% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 39299664 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1450,10 +1501,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1783080197250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1783080197250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1779915025250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1779915025250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 6ae80aee8..e98e38022 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137972 # Number of seconds simulated -sim_ticks 5137971999000 # Number of ticks simulated -final_tick 5137971999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.141960 # Number of seconds simulated +sim_ticks 5141959613000 # Number of ticks simulated +final_tick 5141959613000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151274 # Simulator instruction rate (inst/s) -host_op_rate 299020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1905679647 # Simulator tick rate (ticks/s) -host_mem_usage 770140 # Number of bytes of host memory used -host_seconds 2696.14 # Real time elapsed on the host -sim_insts 407854776 # Number of instructions simulated -sim_ops 806198141 # Number of ops (including micro ops) simulated +host_inst_rate 152486 # Simulator instruction rate (inst/s) +host_op_rate 301416 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1922658876 # Simulator tick rate (ticks/s) +host_mem_usage 770128 # Number of bytes of host memory used +host_seconds 2674.40 # Real time elapsed on the host +sim_insts 407807707 # Number of instructions simulated +sim_ops 806107146 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2477120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1034624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10750336 # Number of bytes read from this memory -system.physmem.bytes_read::total 14265472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1034624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1034624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9529024 # Number of bytes written to this memory -system.physmem.bytes_written::total 9529024 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38705 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16166 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167974 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222898 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148891 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148891 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2092331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2776479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201368 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201368 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1854627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1854627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1854627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2092331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4631107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222898 # Number of read requests accepted -system.physmem.writeReqs 148891 # Number of write requests accepted -system.physmem.readBursts 222898 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148891 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14252672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12800 # Total number of bytes read from write queue -system.physmem.bytesWritten 9527360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14265472 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9529024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 200 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::pc.south_bridge.ide 2476992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1035072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10749056 # Number of bytes read from this memory +system.physmem.bytes_read::total 14265280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1035072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1035072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9521344 # Number of bytes written to this memory +system.physmem.bytes_written::total 9521344 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38703 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16173 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222895 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148771 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148771 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 481721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2090459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2774289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1851696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1851696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1851696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 481721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2090459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4625984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222895 # Number of read requests accepted +system.physmem.writeReqs 148771 # Number of write requests accepted +system.physmem.readBursts 222895 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148771 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14256576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 9520064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14265280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9521344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1701 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14548 # Per bank write bursts -system.physmem.perBankRdBursts::1 13887 # Per bank write bursts -system.physmem.perBankRdBursts::2 14162 # Per bank write bursts -system.physmem.perBankRdBursts::3 13520 # Per bank write bursts -system.physmem.perBankRdBursts::4 14300 # Per bank write bursts -system.physmem.perBankRdBursts::5 13581 # Per bank write bursts -system.physmem.perBankRdBursts::6 13426 # Per bank write bursts -system.physmem.perBankRdBursts::7 13413 # Per bank write bursts -system.physmem.perBankRdBursts::8 13607 # Per bank write bursts -system.physmem.perBankRdBursts::9 13662 # Per bank write bursts -system.physmem.perBankRdBursts::10 13602 # Per bank write bursts -system.physmem.perBankRdBursts::11 13631 # Per bank write bursts -system.physmem.perBankRdBursts::12 14336 # Per bank write bursts -system.physmem.perBankRdBursts::13 14588 # Per bank write bursts -system.physmem.perBankRdBursts::14 14340 # Per bank write bursts -system.physmem.perBankRdBursts::15 14095 # Per bank write bursts -system.physmem.perBankWrBursts::0 9881 # Per bank write bursts -system.physmem.perBankWrBursts::1 9301 # Per bank write bursts -system.physmem.perBankWrBursts::2 9417 # Per bank write bursts -system.physmem.perBankWrBursts::3 9104 # Per bank write bursts -system.physmem.perBankWrBursts::4 9702 # Per bank write bursts -system.physmem.perBankWrBursts::5 8858 # Per bank write bursts -system.physmem.perBankWrBursts::6 8862 # Per bank write bursts -system.physmem.perBankWrBursts::7 8906 # Per bank write bursts -system.physmem.perBankWrBursts::8 8978 # Per bank write bursts -system.physmem.perBankWrBursts::9 9056 # Per bank write bursts -system.physmem.perBankWrBursts::10 9081 # Per bank write bursts -system.physmem.perBankWrBursts::11 9102 # Per bank write bursts -system.physmem.perBankWrBursts::12 9605 # Per bank write bursts -system.physmem.perBankWrBursts::13 9854 # Per bank write bursts -system.physmem.perBankWrBursts::14 9646 # Per bank write bursts -system.physmem.perBankWrBursts::15 9512 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1680 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14406 # Per bank write bursts +system.physmem.perBankRdBursts::1 13692 # Per bank write bursts +system.physmem.perBankRdBursts::2 14137 # Per bank write bursts +system.physmem.perBankRdBursts::3 13444 # Per bank write bursts +system.physmem.perBankRdBursts::4 14027 # Per bank write bursts +system.physmem.perBankRdBursts::5 13372 # Per bank write bursts +system.physmem.perBankRdBursts::6 13359 # Per bank write bursts +system.physmem.perBankRdBursts::7 13805 # Per bank write bursts +system.physmem.perBankRdBursts::8 13762 # Per bank write bursts +system.physmem.perBankRdBursts::9 13592 # Per bank write bursts +system.physmem.perBankRdBursts::10 13956 # Per bank write bursts +system.physmem.perBankRdBursts::11 13564 # Per bank write bursts +system.physmem.perBankRdBursts::12 14528 # Per bank write bursts +system.physmem.perBankRdBursts::13 14698 # Per bank write bursts +system.physmem.perBankRdBursts::14 14291 # Per bank write bursts +system.physmem.perBankRdBursts::15 14126 # Per bank write bursts +system.physmem.perBankWrBursts::0 9807 # Per bank write bursts +system.physmem.perBankWrBursts::1 9166 # Per bank write bursts +system.physmem.perBankWrBursts::2 9421 # Per bank write bursts +system.physmem.perBankWrBursts::3 8835 # Per bank write bursts +system.physmem.perBankWrBursts::4 9422 # Per bank write bursts +system.physmem.perBankWrBursts::5 8917 # Per bank write bursts +system.physmem.perBankWrBursts::6 8763 # Per bank write bursts +system.physmem.perBankWrBursts::7 9221 # Per bank write bursts +system.physmem.perBankWrBursts::8 9116 # Per bank write bursts +system.physmem.perBankWrBursts::9 9134 # Per bank write bursts +system.physmem.perBankWrBursts::10 9470 # Per bank write bursts +system.physmem.perBankWrBursts::11 8904 # Per bank write bursts +system.physmem.perBankWrBursts::12 9718 # Per bank write bursts +system.physmem.perBankWrBursts::13 9806 # Per bank write bursts +system.physmem.perBankWrBursts::14 9580 # Per bank write bursts +system.physmem.perBankWrBursts::15 9471 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 5137971883500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 5141959559500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222898 # Read request sizes (log2) +system.physmem.readPktSize::6 222895 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148891 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 173419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 836 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 25 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148771 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 173187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,224 +156,223 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.994064 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.175651 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 374.202346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15813 31.71% 31.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11064 22.19% 53.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5080 10.19% 64.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2824 5.66% 69.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1980 3.97% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1284 2.57% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 922 1.85% 78.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 716 1.44% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10185 20.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49868 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 8142 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.350037 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 531.765782 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 8141 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 9176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 74587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.776409 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.138812 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.199277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28275 37.91% 37.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16828 22.56% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7503 10.06% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4244 5.69% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3057 4.10% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2068 2.77% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1382 1.85% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1175 1.58% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10055 13.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74587 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8285 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.884007 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 527.034010 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 8284 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 8142 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 8142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.283591 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.627324 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.611364 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 6056 74.38% 74.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 1276 15.67% 90.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 101 1.24% 91.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 41 0.50% 91.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 52 0.64% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 70 0.86% 93.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 65 0.80% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 71 0.87% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 51 0.63% 95.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 44 0.54% 96.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 56 0.69% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 33 0.41% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 34 0.42% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 29 0.36% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 35 0.43% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 23 0.28% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 19 0.23% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 12 0.15% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 12 0.15% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 9 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 6 0.07% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 7 0.09% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 2 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 13 0.16% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 13 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 1 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 4 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::74-75 3 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 2 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-81 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 8142 # Writes before turning the bus around for reads -system.physmem.totQLat 5275412250 # Total ticks spent queuing -system.physmem.totMemAccLat 9510468500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1113490000 # Total ticks spent in databus transfers -system.physmem.totBankLat 3121566250 # Total ticks spent accessing banks -system.physmem.avgQLat 23688.64 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14017.04 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 8285 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8285 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.954255 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.428609 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.676130 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 6158 74.33% 74.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1338 16.15% 90.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 52 0.63% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 77 0.93% 92.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 47 0.57% 92.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 55 0.66% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 103 1.24% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 89 1.07% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 47 0.57% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 58 0.70% 96.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 37 0.45% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 45 0.54% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 69 0.83% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 27 0.33% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 11 0.13% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 16 0.19% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 22 0.27% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 4 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 7 0.08% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 2 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 3 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 5 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 4 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 3 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-81 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-89 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8285 # Writes before turning the bus around for reads +system.physmem.totQLat 4923822749 # Total ticks spent queuing +system.physmem.totMemAccLat 9100553999 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1113795000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22103.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42705.68 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 40853.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.02 # Average write queue length when enqueuing -system.physmem.readRowHits 186969 # Number of row buffer hits during reads -system.physmem.writeRowHits 110725 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes -system.physmem.avgGap 13819590.91 # Average gap between requests -system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 5100645 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662331 # Transaction distribution -system.membus.trans_dist::ReadResp 662323 # Transaction distribution -system.membus.trans_dist::WriteReq 13764 # Transaction distribution -system.membus.trans_dist::WriteResp 13764 # Transaction distribution -system.membus.trans_dist::Writeback 148891 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1718 # Transaction distribution -system.membus.trans_dist::ReadExReq 179464 # Transaction distribution -system.membus.trans_dist::ReadExResp 179461 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 8 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721276 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 133006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 133006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1857568 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550149 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18330624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20122575 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463872 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5463872 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25593019 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25593019 # Total data (bytes) -system.membus.snoop_data_through_bus 613952 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250521000 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing +system.physmem.readRowHits 186870 # Number of row buffer hits during reads +system.physmem.writeRowHits 110052 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.97 # Row buffer hit rate for writes +system.physmem.avgGap 13834893.59 # Average gap between requests +system.physmem.pageHitRate 79.92 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4934274417750 # Time in different power states +system.physmem.memoryStateTime::REF 171701140000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 35983950250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 5095093 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662466 # Transaction distribution +system.membus.trans_dist::ReadResp 662464 # Transaction distribution +system.membus.trans_dist::WriteReq 13782 # Transaction distribution +system.membus.trans_dist::WriteResp 13782 # Transaction distribution +system.membus.trans_dist::Writeback 148771 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution +system.membus.trans_dist::ReadExReq 179320 # Transaction distribution +system.membus.trans_dist::ReadExResp 179319 # Transaction distribution +system.membus.trans_dist::MessageReq 1645 # Transaction distribution +system.membus.trans_dist::MessageResp 1645 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475021 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721191 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132996 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132996 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1857477 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550161 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20114933 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5463680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25585193 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25585193 # Total data (bytes) +system.membus.snoop_data_through_bus 613568 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250592000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583253500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583283000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1611616249 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1610033997 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3152435901 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3152758703 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429736248 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429601748 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47579 # number of replacements -system.iocache.tags.tagsinuse 0.116331 # Cycle average of tags in use +system.iocache.tags.replacements 47571 # number of replacements +system.iocache.tags.tagsinuse 0.128712 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992993838000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116331 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007271 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007271 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992977133000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128712 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008045 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.008045 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428697 # Number of tag accesses -system.iocache.tags.data_accesses 428697 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses -system.iocache.ReadReq_misses::total 913 # number of ReadReq misses +system.iocache.tags.tag_accesses 428634 # Number of tag accesses +system.iocache.tags.data_accesses 428634 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses +system.iocache.ReadReq_misses::total 906 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47633 # number of demand (read+write) misses -system.iocache.demand_misses::total 47633 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47633 # number of overall misses -system.iocache.overall_misses::total 47633 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149265435 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149265435 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11474717915 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11474717915 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11623983350 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11623983350 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11623983350 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11623983350 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses +system.iocache.demand_misses::total 47626 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses +system.iocache.overall_misses::total 47626 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147491196 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 147491196 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11109159898 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11109159898 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11256651094 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11256651094 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11256651094 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11256651094 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -382,40 +381,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163488.975904 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 163488.975904 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245606.119756 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 245606.119756 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244032.148930 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 244032.148930 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244032.148930 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 244032.148930 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 177888 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162793.814570 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162793.814570 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 237781.675899 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 237781.675899 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 236355.165120 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 236355.165120 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 159859 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 14382 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 14672 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.368794 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.895515 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 913 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 913 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47633 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47633 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47633 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47633 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101762935 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 101762935 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9043225919 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9043225919 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9144988854 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9144988854 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9144988854 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9144988854 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100353196 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100353196 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8677810402 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8677810402 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8778163598 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8778163598 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -424,18 +423,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111459.950712 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 111459.950712 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193562.198609 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 193562.198609 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 191988.513300 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 191988.513300 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110765.116998 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 110765.116998 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 185740.804837 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 185740.804837 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -445,16 +444,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 637649 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225561 # Transaction distribution -system.iobus.trans_dist::ReadResp 225561 # Transaction distribution -system.iobus.trans_dist::WriteReq 57591 # Transaction distribution -system.iobus.trans_dist::WriteResp 57591 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.throughput 637150 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225562 # Transaction distribution +system.iobus.trans_dist::ReadResp 225562 # Transaction distribution +system.iobus.trans_dist::WriteReq 57606 # Transaction distribution +system.iobus.trans_dist::WriteResp 57606 # Transaction distribution +system.iobus.trans_dist::MessageReq 1645 # Transaction distribution +system.iobus.trans_dist::MessageResp 1645 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -470,15 +469,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569626 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -494,20 +493,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276222 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276222 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3918904 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276200 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3930346 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -537,155 +536,155 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 425268102 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424685346 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53403752 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53671252 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 85606951 # Number of BP lookups -system.cpu.branchPred.condPredicted 85606951 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 878900 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79252981 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77536604 # Number of BTB hits +system.cpu.branchPred.lookups 85633263 # Number of BP lookups +system.cpu.branchPred.condPredicted 85633263 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 884686 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79267379 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77548662 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.834306 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1442152 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 179942 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.831747 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1440338 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180105 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 453123649 # number of cpu cycles simulated +system.cpu.numCycles 453234333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25513299 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422793316 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85606951 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78978756 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162666775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3977899 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 109317 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 70887668 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43514 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89257 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8479758 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 384207 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2414 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262364646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.182537 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25483623 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422835891 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85633263 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78989000 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162683938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4002747 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 108573 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 70983982 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43526 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 92374 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8487571 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 384793 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2466 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262469836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.181706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411661 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100112047 38.16% 38.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1537808 0.59% 38.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71834602 27.38% 66.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 894624 0.34% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1560586 0.59% 67.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2393199 0.91% 67.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1018516 0.39% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1331320 0.51% 68.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81681944 31.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100201994 38.18% 38.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1531970 0.58% 38.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71824716 27.36% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 909581 0.35% 66.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1572022 0.60% 67.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2391233 0.91% 67.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1015593 0.39% 68.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1327813 0.51% 68.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81694914 31.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262364646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.933064 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29407134 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68048451 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158512522 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3341909 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3054630 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832669874 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 887 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3054630 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32105381 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42832622 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12466754 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158806940 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13098319 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829768905 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20738 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6073581 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5148249 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991466417 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800660067 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1107048961 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 106 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964157062 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27309353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 454429 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 460129 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29597584 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16731616 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9822119 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1090956 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 912656 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824999655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1185445 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 821065367 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 147374 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19153823 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29264539 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 130709 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262364646 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.129482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.399412 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262469836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188938 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.932930 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29410093 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68121182 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158520657 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3344277 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3073627 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832752013 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3073627 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32108860 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 42947155 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12423337 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158815296 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13101561 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829828808 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20476 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6069323 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5155919 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991491995 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800757525 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1107104494 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964043985 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27448008 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 454148 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459927 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29603104 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16744391 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9834089 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1098610 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 922271 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 825029586 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1184674 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 821050392 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 152353 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19282759 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29404306 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 129800 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262469836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.128170 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.399623 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75980319 28.96% 28.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15750588 6.00% 34.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10556494 4.02% 38.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7365908 2.81% 41.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75746368 28.87% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3736962 1.42% 72.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72307682 27.56% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 774907 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 145418 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76068971 28.98% 28.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15764450 6.01% 34.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10561557 4.02% 39.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7380977 2.81% 41.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75732754 28.85% 70.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3744713 1.43% 72.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72297753 27.55% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 770490 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 148171 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262364646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262469836 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 352804 33.38% 33.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 33.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 895 0.08% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 548620 51.91% 85.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 154313 14.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 351121 33.32% 33.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 242 0.02% 33.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 235 0.02% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548827 52.08% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153397 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 307554 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793584898 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150109 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124066 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 310274 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793553745 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150127 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124319 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -712,297 +711,332 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17676623 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9222117 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17682976 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9228951 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 821065367 # Type of FU issued -system.cpu.iq.rate 1.812012 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1056873 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905808819 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845349453 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817155578 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 173 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821814606 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 80 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1693534 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 821050392 # Type of FU issued +system.cpu.iq.rate 1.811536 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1053822 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905885622 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845507474 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817131376 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 174 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 198 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821793858 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694774 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2731831 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17734 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12108 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1395931 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2743773 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18703 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12097 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1404751 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932011 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12232 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931902 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12205 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3054630 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30960729 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2157350 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826185100 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241589 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16731616 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9822119 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 690497 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620390 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12858 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12108 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 495281 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1001721 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819661058 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17373288 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1404308 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3073627 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31062869 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2159597 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826214260 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 248339 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16744391 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9834089 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 689465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620816 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13300 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12097 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498594 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 510068 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1008662 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819639552 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17378500 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1410839 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26412112 # number of memory reference insts executed -system.cpu.iew.exec_branches 83101028 # Number of branches executed -system.cpu.iew.exec_stores 9038824 # Number of stores executed -system.cpu.iew.exec_rate 1.808913 # Inst execution rate -system.cpu.iew.wb_sent 819257147 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817155626 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638657480 # num instructions producing a value -system.cpu.iew.wb_consumers 1044041746 # num instructions consuming a value +system.cpu.iew.exec_refs 26423310 # number of memory reference insts executed +system.cpu.iew.exec_branches 83104184 # Number of branches executed +system.cpu.iew.exec_stores 9044810 # Number of stores executed +system.cpu.iew.exec_rate 1.808423 # Inst execution rate +system.cpu.iew.wb_sent 819235043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817131426 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638623234 # num instructions producing a value +system.cpu.iew.wb_consumers 1043962608 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.803383 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611716 # average fanout of values written-back +system.cpu.iew.wb_rate 1.802890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19877862 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054736 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 888910 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259310016 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.109013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863250 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19998130 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054874 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 894775 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259396209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.107629 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863349 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87730314 33.83% 33.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11862694 4.57% 38.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3835821 1.48% 39.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74768182 28.83% 68.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2381229 0.92% 69.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1479438 0.57% 70.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 861979 0.33% 70.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70857593 27.33% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5532766 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87828444 33.86% 33.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11868241 4.58% 38.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3842531 1.48% 39.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74752258 28.82% 68.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2384729 0.92% 69.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1479281 0.57% 70.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 859408 0.33% 70.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70845236 27.31% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5536081 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259310016 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407854776 # Number of instructions committed -system.cpu.commit.committedOps 806198141 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259396209 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407807707 # Number of instructions committed +system.cpu.commit.committedOps 806107146 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22425972 # Number of memory references committed -system.cpu.commit.loads 13999784 # Number of loads committed -system.cpu.commit.membars 474669 # Number of memory barriers committed -system.cpu.commit.branches 82177261 # Number of branches committed +system.cpu.commit.refs 22429955 # Number of memory references committed +system.cpu.commit.loads 14000617 # Number of loads committed +system.cpu.commit.membars 474711 # Number of memory barriers committed +system.cpu.commit.branches 82167469 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735033306 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155486 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5532766 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734952495 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155627 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174437 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783236239 97.16% 97.18% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144862 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121653 0.02% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14000617 1.74% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8429338 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 806107146 # Class of committed instruction +system.cpu.commit.bw_lim_events 5536081 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079774887 # The number of ROB reads -system.cpu.rob.rob_writes 1655221365 # The number of ROB writes -system.cpu.timesIdled 1257777 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190759003 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9822826051 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407854776 # Number of Instructions Simulated -system.cpu.committedOps 806198141 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407854776 # Number of Instructions Simulated -system.cpu.cpi 1.110993 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.110993 # CPI: Total CPI of All Threads -system.cpu.ipc 0.900096 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.900096 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088904390 # number of integer regfile reads -system.cpu.int_regfile_writes 653903158 # number of integer regfile writes -system.cpu.fp_regfile_reads 48 # number of floating regfile reads -system.cpu.cc_regfile_reads 415697548 # number of cc regfile reads -system.cpu.cc_regfile_writes 321557341 # number of cc regfile writes -system.cpu.misc_regfile_reads 264102486 # number of misc regfile reads -system.cpu.misc_regfile_writes 402568 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53587278 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3014875 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3014340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1579042 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 336648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 289942 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1911181 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6131826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18757 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 150026 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8211790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61153920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207959183 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 582080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5191488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 274886671 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274861071 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 468864 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4035423910 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1079887016 # The number of ROB reads +system.cpu.rob.rob_writes 1655298855 # The number of ROB writes +system.cpu.timesIdled 1259672 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190764497 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9830690598 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407807707 # Number of Instructions Simulated +system.cpu.committedOps 806107146 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407807707 # Number of Instructions Simulated +system.cpu.cpi 1.111392 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.111392 # CPI: Total CPI of All Threads +system.cpu.ipc 0.899772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.899772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088844162 # number of integer regfile reads +system.cpu.int_regfile_writes 653876789 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.cc_regfile_reads 415644137 # number of cc regfile reads +system.cpu.cc_regfile_writes 321521730 # number of cc regfile writes +system.cpu.misc_regfile_reads 264115519 # number of misc regfile reads +system.cpu.misc_regfile_writes 402672 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53624827 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3015737 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3015197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1584798 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 336401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 289692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6128379 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8215578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61059136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207801717 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 607680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5615104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 275083637 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 275059381 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 677312 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4044441846 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 600000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 568500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1436807344 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1434613560 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3142634309 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3141764506 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 14495745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 14738244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 103414152 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 107967138 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 955079 # number of replacements -system.cpu.icache.tags.tagsinuse 509.954947 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7470392 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 955591 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.817562 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147668859250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.954947 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996006 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 953583 # number of replacements +system.cpu.icache.tags.tagsinuse 509.342760 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7479724 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 954095 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.839601 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147639960250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.342760 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994810 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994810 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9435405 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9435405 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7470392 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7470392 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7470392 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7470392 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7470392 # number of overall hits -system.cpu.icache.overall_hits::total 7470392 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1009362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1009362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1009362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1009362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1009362 # number of overall misses -system.cpu.icache.overall_misses::total 1009362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14063763284 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14063763284 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14063763284 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14063763284 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14063763284 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14063763284 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8479754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8479754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8479754 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8479754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8479754 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8479754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13933.319546 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13933.319546 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13933.319546 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13933.319546 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13933.319546 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13933.319546 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4512 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9441724 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9441724 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7479724 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7479724 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7479724 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7479724 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7479724 # number of overall hits +system.cpu.icache.overall_hits::total 7479724 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1007844 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1007844 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1007844 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1007844 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1007844 # number of overall misses +system.cpu.icache.overall_misses::total 1007844 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14035582232 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14035582232 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14035582232 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14035582232 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14035582232 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14035582232 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8487568 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8487568 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8487568 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8487568 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8487568 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8487568 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118744 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118744 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118744 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.118744 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.118744 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.118744 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13926.343990 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13926.343990 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13926.343990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13926.343990 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4168 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 173 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.080925 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.936842 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 955651 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 955651 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11613116903 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11613116903 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11613116903 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11613116903 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11613116903 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11613116903 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112698 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112698 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112698 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12152.048083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12152.048083 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12152.048083 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12152.048083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12152.048083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12152.048083 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53688 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53688 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53688 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53688 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53688 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53688 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954156 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 954156 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 954156 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 954156 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 954156 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 954156 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112418 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12144.301809 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12144.301809 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8788 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 5.050842 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 20362 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8802 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.313338 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5105053160000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 5.050842 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.315678 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.315678 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 8939 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.031288 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21114 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 8953 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.358316 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5104803925000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031288 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376956 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376956 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 69716 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 69716 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20363 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 20363 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 71741 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 71741 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21134 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21134 # 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number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21136 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21136 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 107949749 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 107949749 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 107949749 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 107949749 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 107949749 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 107949749 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30957 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30957 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30027 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30027 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30027 # 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average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11351.117574 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11351.117574 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11351.117574 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30959 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30959 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30959 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30959 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.317311 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.317311 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.317291 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.317291 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.317291 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.317291 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10989.488853 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10989.488853 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10989.488853 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10989.488853 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1011,85 +1045,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1311 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1311 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9662 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9662 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9662 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9662 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9662 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9662 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 90345008 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 90345008 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 90345008 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 90345008 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 90345008 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 90345008 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.321799 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.321799 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.321777 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.321777 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.321777 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.321777 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9350.549369 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9350.549369 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9350.549369 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1983 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1983 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88296261 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 88296261 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 88296261 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 88296261 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 88296261 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 88296261 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.317311 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.317311 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.317291 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.317291 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8988.726560 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 67950 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 13.831671 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92323 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 67966 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.358370 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101646178000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.831671 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.864479 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.864479 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 70861 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 12.940736 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 90199 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 70877 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.272613 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101635052500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 12.940736 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.808796 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.808796 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 391373 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 391373 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92323 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92323 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92323 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92323 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92323 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92323 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68909 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 68909 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68909 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 68909 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68909 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 68909 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 862549215 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 862549215 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 862549215 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 862549215 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 862549215 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 862549215 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161232 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 161232 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161232 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 161232 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161232 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 161232 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.427390 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.427390 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.427390 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.427390 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.427390 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.427390 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12517.221481 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12517.221481 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12517.221481 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12517.221481 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12517.221481 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12517.221481 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 396218 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 396218 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90199 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 90199 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90199 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 90199 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90199 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 90199 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71940 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 71940 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71940 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 71940 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71940 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 71940 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 878693205 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 878693205 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 878693205 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 878693205 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 878693205 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 878693205 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162139 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 162139 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162139 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 162139 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162139 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 162139 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.443693 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.443693 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.443693 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.443693 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.443693 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.443693 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12214.250834 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12214.250834 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12214.250834 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12214.250834 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1098,153 +1132,153 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 16529 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 16529 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68909 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68909 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68909 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 68909 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68909 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 68909 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 724629911 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 724629911 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 724629911 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 724629911 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 724629911 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 724629911 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.427390 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.427390 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.427390 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.751368 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.751368 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.751368 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 22838 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 22838 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71940 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71940 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71940 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 71940 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71940 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 71940 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 734698929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 734698929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 734698929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 734698929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 734698929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 734698929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.443693 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.443693 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.443693 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10212.662344 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1659840 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996448 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18992605 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1660352 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.438903 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40084250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996448 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1658766 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994288 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19002910 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1659278 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.452517 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 39778250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994288 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87845319 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87845319 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10889826 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10889826 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8100117 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8100117 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18989943 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18989943 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18989943 # number of overall hits -system.cpu.dcache.overall_hits::total 18989943 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2239768 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2239768 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316527 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316527 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2556295 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2556295 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2556295 # number of overall misses -system.cpu.dcache.overall_misses::total 2556295 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32903838390 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32903838390 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11976667737 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11976667737 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 44880506127 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 44880506127 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 44880506127 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 44880506127 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13129594 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13129594 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8416644 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8416644 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21546238 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21546238 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21546238 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21546238 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170589 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170589 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118642 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118642 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118642 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118642 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14690.735107 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14690.735107 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37837.744448 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37837.744448 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17556.857142 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17556.857142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17556.857142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17556.857142 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 388578 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87874474 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87874474 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10896738 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10896738 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8103479 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8103479 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19000217 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19000217 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19000217 # number of overall hits +system.cpu.dcache.overall_hits::total 19000217 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2237270 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2237270 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316309 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316309 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2553579 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2553579 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2553579 # number of overall misses +system.cpu.dcache.overall_misses::total 2553579 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32758938054 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32758938054 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12034849454 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12034849454 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 44793787508 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 44793787508 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 44793787508 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 44793787508 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13134008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13134008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8419788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8419788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21553796 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21553796 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21553796 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21553796 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170342 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170342 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037567 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037567 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118475 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118475 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118475 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118475 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14642.371307 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14642.371307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38047.761695 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38047.761695 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17541.571069 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17541.571069 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 388234 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42350 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42159 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.175396 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.208805 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1561202 # number of writebacks -system.cpu.dcache.writebacks::total 1561202 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 869210 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 869210 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24502 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24502 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 893712 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 893712 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 893712 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 893712 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1370558 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1370558 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292025 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 292025 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1662583 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1662583 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1662583 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1662583 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17741695710 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17741695710 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11080104948 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11080104948 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28821800658 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28821800658 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28821800658 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28821800658 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363380000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363380000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536381000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536381000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899761000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99899761000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104387 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104387 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034696 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034696 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077163 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077163 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077163 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077163 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12944.870418 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12944.870418 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.316404 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.316404 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17335.555974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17335.555974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17335.555974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17335.555974 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1559977 # number of writebacks +system.cpu.dcache.writebacks::total 1559977 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867558 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 867558 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24476 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 24476 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 892034 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 892034 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 892034 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 892034 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369712 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1369712 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291833 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291833 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1661545 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1661545 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1661545 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1661545 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17680675970 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17680675970 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11138475501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11138475501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28819151471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28819151471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28819151471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28819151471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364609500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364609500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539074000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539074000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903683500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903683500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104287 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104287 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034660 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034660 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.316471 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.316471 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38167.292599 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38167.292599 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1252,150 +1286,150 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111989 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64821.159717 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3780351 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176044 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.473899 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111887 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64820.177016 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3787056 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176012 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.515897 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50592.226872 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.121398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.097025 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2916.382816 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11302.331606 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.771976 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000154 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.044500 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.172460 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64055 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69506.318084 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84445.833333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75650 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76243.275611 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71193.706248 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71639.322125 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84445.833333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75650 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76243.275611 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71193.706248 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71639.322125 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1404,8 +1438,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102223 # number of writebacks -system.cpu.l2cache.writebacks::total 102223 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 102104 # number of writebacks +system.cpu.l2cache.writebacks::total 102104 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits @@ -1415,88 +1449,88 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16166 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35906 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 52125 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1443 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1443 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 315250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1030094767 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9906472112 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10941206879 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251381500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251381500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373144500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373144500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624526000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624526000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026314 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021817 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814626 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814626 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.458657 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.458657 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068946 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068946 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63692.250479 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64941.993254 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64563.238983 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10640.164927 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10640.164927 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56955.740006 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56955.740006 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index cc51e20ce..69bdeab1f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.304497 # Nu sim_ticks 5304496750000 # Number of ticks simulated final_tick 5304496750000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156851 # Simulator instruction rate (inst/s) -host_op_rate 300747 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7785889362 # Simulator tick rate (ticks/s) -host_mem_usage 816820 # Number of bytes of host memory used -host_seconds 681.30 # Real time elapsed on the host +host_inst_rate 145026 # Simulator instruction rate (inst/s) +host_op_rate 278074 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7198918941 # Simulator tick rate (ticks/s) +host_mem_usage 818088 # Number of bytes of host memory used +host_seconds 736.85 # Real time elapsed on the host sim_insts 106862058 # Number of instructions simulated sim_ops 204897478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -234,9 +234,7 @@ system.physmem.wrQLenPdf::63 0 # Wh system.physmem.totQLat 0 # Total ticks spent queuing system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 0 # Total ticks spent in databus transfers -system.physmem.totBankLat 0 # Total ticks spent accessing banks system.physmem.avgQLat nan # Average queueing delay per DRAM burst -system.physmem.avgBankLat nan # Average bank access latency per DRAM burst system.physmem.avgBusLat nan # Average bus latency per DRAM burst system.physmem.avgMemAccLat nan # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.00 # Average DRAM read bandwidth in MiByte/s @@ -255,137 +253,11 @@ system.physmem.readRowHitRate nan # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state -system.iobus.throughput 383259 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 858443 # Transaction distribution -system.iobus.trans_dist::ReadResp 858443 # Transaction distribution -system.iobus.trans_dist::WriteReq 37726 # Transaction distribution -system.iobus.trans_dist::WriteResp 37726 # Transaction distribution -system.iobus.trans_dist::MessageReq 1924 # Transaction distribution -system.iobus.trans_dist::MessageResp 1924 # Transaction distribution -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6438 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 980 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14492 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703384 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4650 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 354 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 89454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1796186 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3666 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1960 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7246 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 484 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972069 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 708 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10485 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2032994 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2032994 # Total data (bytes) -system.iobus.reqLayer0.occupancy 45000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10111500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1076000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 95000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 57500 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 30321000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 467293000 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1240500 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 41494500 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 23487000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 469626032 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 7795368 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1328500 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2413900 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1790216000 # Layer occupancy (ticks) -system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 80190500 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.physmem.memoryStateTime::IDLE 5127363440000 # Time in different power states +system.physmem.memoryStateTime::REF 177128640000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 0 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 2 # delay histogram for all message system.ruby.delayHist::max_bucket 19 # delay histogram for all message @@ -590,6 +462,136 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.throughput 383259 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 858443 # Transaction distribution +system.iobus.trans_dist::ReadResp 858443 # Transaction distribution +system.iobus.trans_dist::WriteReq 37726 # Transaction distribution +system.iobus.trans_dist::WriteResp 37726 # Transaction distribution +system.iobus.trans_dist::MessageReq 1924 # Transaction distribution +system.iobus.trans_dist::MessageResp 1924 # Transaction distribution +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6438 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 354 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 89454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1796186 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3666 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1960 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7246 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 484 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972069 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3020 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 708 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10485 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2032994 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2032994 # Total data (bytes) +system.iobus.reqLayer0.occupancy 45000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 10111500 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 1076000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 95000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 57500 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 30321000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 467293000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 1240500 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 41494500 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 23487000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 469626032 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 7795368 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 1328500 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2413900 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1790216000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 80190500 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu0.numCycles 10608993500 # number of cpu cycles simulated @@ -617,6 +619,41 @@ system.cpu0.num_busy_cycles 526834059.049901 system.cpu0.not_idle_fraction 0.049659 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.950341 # Percentage of idle cycles system.cpu0.Branches 11678784 # Number of branches fetched +system.cpu0.op_class::No_OpClass 146088 0.13% 0.13% # Class of executed instruction +system.cpu0.op_class::IntAlu 102315691 88.54% 88.66% # Class of executed instruction +system.cpu0.op_class::IntMult 88423 0.08% 88.74% # Class of executed instruction +system.cpu0.op_class::IntDiv 60803 0.05% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::MemRead 7847946 6.79% 95.58% # Class of executed instruction +system.cpu0.op_class::MemWrite 5106253 4.42% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 115565204 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks @@ -645,6 +682,41 @@ system.cpu1.num_busy_cycles 320373991.077311 system.cpu1.not_idle_fraction 0.030207 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969793 # Percentage of idle cycles system.cpu1.Branches 10261767 # Number of branches fetched +system.cpu1.op_class::No_OpClass 160875 0.18% 0.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 75501866 84.52% 84.70% # Class of executed instruction +system.cpu1.op_class::IntMult 96299 0.11% 84.80% # Class of executed instruction +system.cpu1.op_class::IntDiv 67676 0.08% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::MemRead 8734970 9.78% 94.66% # Class of executed instruction +system.cpu1.op_class::MemWrite 4772103 5.34% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 89333789 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.ruby.network.routers0.throttle0.link_utilization 0.041639 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 4c7c80e7e..66a37e2a3 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.139775 # Number of seconds simulated -sim_ticks 5139775442500 # Number of ticks simulated -final_tick 5139775442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133875 # Number of seconds simulated +sim_ticks 5133874673500 # Number of ticks simulated +final_tick 5133874673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235748 # Simulator instruction rate (inst/s) -host_op_rate 468611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4967362364 # Simulator tick rate (ticks/s) -host_mem_usage 954112 # Number of bytes of host memory used -host_seconds 1034.71 # Real time elapsed on the host -sim_insts 243931071 # Number of instructions simulated -sim_ops 484875903 # Number of ops (including micro ops) simulated +host_inst_rate 230895 # Simulator instruction rate (inst/s) +host_op_rate 458967 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4861072606 # Simulator tick rate (ticks/s) +host_mem_usage 966208 # Number of bytes of host memory used +host_seconds 1056.12 # Real time elapsed on the host +sim_insts 243852608 # Number of instructions simulated +sim_ops 484724489 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2452480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 439552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5834944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 98048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1717440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 432064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2820032 # Number of bytes read from this memory -system.physmem.bytes_read::total 13796608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 439552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 98048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 432064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9118784 # Number of bytes written to this memory -system.physmem.bytes_written::total 9118784 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38320 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6868 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 91171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1532 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 26835 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 44063 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215572 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142481 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142481 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 477157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 85520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1135253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 19076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 334147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 84063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 548668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2684282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 85520 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 19076 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 84063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1774160 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1774160 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1774160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 477157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 85520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1135253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 19076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 334147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 84063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 548668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4458442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98736 # Number of read requests accepted -system.physmem.writeReqs 74818 # Number of write requests accepted -system.physmem.readBursts 98736 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 74818 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6312704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6400 # Total number of bytes read from write queue -system.physmem.bytesWritten 4788352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6319104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4788352 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::pc.south_bridge.ide 2445440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 500480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5911104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 139776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1689280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 309696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2752128 # Number of bytes read from this memory +system.physmem.bytes_read::total 13749568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 500480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 139776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 309696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 949952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9083392 # Number of bytes written to this memory +system.physmem.bytes_written::total 9083392 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38210 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7820 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 92361 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 26395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4839 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 43002 # Number of read requests responded to by this memory +system.physmem.num_reads::total 214837 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141928 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141928 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 97486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1151392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 27226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 329046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 60324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 536072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2678205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 97486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 27226 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 60324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 185036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1769305 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1769305 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1769305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 97486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1151392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 27226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 329046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 60324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 536072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4447510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 96612 # Number of read requests accepted +system.physmem.writeReqs 73475 # Number of write requests accepted +system.physmem.readBursts 96612 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 73475 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6177024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.physmem.bytesWritten 4701248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6183168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4702400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 734 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6153 # Per bank write bursts -system.physmem.perBankRdBursts::1 6286 # Per bank write bursts -system.physmem.perBankRdBursts::2 6219 # Per bank write bursts -system.physmem.perBankRdBursts::3 6279 # Per bank write bursts -system.physmem.perBankRdBursts::4 6331 # Per bank write bursts -system.physmem.perBankRdBursts::5 6377 # Per bank write bursts -system.physmem.perBankRdBursts::6 5798 # Per bank write bursts -system.physmem.perBankRdBursts::7 6202 # Per bank write bursts -system.physmem.perBankRdBursts::8 5707 # Per bank write bursts -system.physmem.perBankRdBursts::9 6391 # Per bank write bursts -system.physmem.perBankRdBursts::10 5673 # Per bank write bursts -system.physmem.perBankRdBursts::11 6223 # Per bank write bursts -system.physmem.perBankRdBursts::12 6101 # Per bank write bursts -system.physmem.perBankRdBursts::13 6086 # Per bank write bursts -system.physmem.perBankRdBursts::14 6643 # Per bank write bursts -system.physmem.perBankRdBursts::15 6167 # Per bank write bursts -system.physmem.perBankWrBursts::0 4924 # Per bank write bursts -system.physmem.perBankWrBursts::1 4781 # Per bank write bursts -system.physmem.perBankWrBursts::2 4796 # Per bank write bursts -system.physmem.perBankWrBursts::3 4885 # Per bank write bursts -system.physmem.perBankWrBursts::4 4841 # Per bank write bursts -system.physmem.perBankWrBursts::5 4959 # Per bank write bursts -system.physmem.perBankWrBursts::6 4374 # Per bank write bursts -system.physmem.perBankWrBursts::7 4731 # Per bank write bursts -system.physmem.perBankWrBursts::8 4283 # Per bank write bursts -system.physmem.perBankWrBursts::9 4855 # Per bank write bursts -system.physmem.perBankWrBursts::10 4375 # Per bank write bursts -system.physmem.perBankWrBursts::11 4455 # Per bank write bursts -system.physmem.perBankWrBursts::12 4488 # Per bank write bursts -system.physmem.perBankWrBursts::13 4484 # Per bank write bursts -system.physmem.perBankWrBursts::14 5021 # Per bank write bursts -system.physmem.perBankWrBursts::15 4566 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 831 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5404 # Per bank write bursts +system.physmem.perBankRdBursts::1 5964 # Per bank write bursts +system.physmem.perBankRdBursts::2 6149 # Per bank write bursts +system.physmem.perBankRdBursts::3 6338 # Per bank write bursts +system.physmem.perBankRdBursts::4 5414 # Per bank write bursts +system.physmem.perBankRdBursts::5 6001 # Per bank write bursts +system.physmem.perBankRdBursts::6 5201 # Per bank write bursts +system.physmem.perBankRdBursts::7 6053 # Per bank write bursts +system.physmem.perBankRdBursts::8 5779 # Per bank write bursts +system.physmem.perBankRdBursts::9 5783 # Per bank write bursts +system.physmem.perBankRdBursts::10 5919 # Per bank write bursts +system.physmem.perBankRdBursts::11 5801 # Per bank write bursts +system.physmem.perBankRdBursts::12 6766 # Per bank write bursts +system.physmem.perBankRdBursts::13 6809 # Per bank write bursts +system.physmem.perBankRdBursts::14 6844 # Per bank write bursts +system.physmem.perBankRdBursts::15 6291 # Per bank write bursts +system.physmem.perBankWrBursts::0 4307 # Per bank write bursts +system.physmem.perBankWrBursts::1 4604 # Per bank write bursts +system.physmem.perBankWrBursts::2 4694 # Per bank write bursts +system.physmem.perBankWrBursts::3 4750 # Per bank write bursts +system.physmem.perBankWrBursts::4 4088 # Per bank write bursts +system.physmem.perBankWrBursts::5 4371 # Per bank write bursts +system.physmem.perBankWrBursts::6 3767 # Per bank write bursts +system.physmem.perBankWrBursts::7 4522 # Per bank write bursts +system.physmem.perBankWrBursts::8 4168 # Per bank write bursts +system.physmem.perBankWrBursts::9 4368 # Per bank write bursts +system.physmem.perBankWrBursts::10 4606 # Per bank write bursts +system.physmem.perBankWrBursts::11 4444 # Per bank write bursts +system.physmem.perBankWrBursts::12 5448 # Per bank write bursts +system.physmem.perBankWrBursts::13 5248 # Per bank write bursts +system.physmem.perBankWrBursts::14 5481 # Per bank write bursts +system.physmem.perBankWrBursts::15 4591 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 5135962999500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 5132874544500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98736 # Read request sizes (log2) +system.physmem.readPktSize::6 96612 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 74818 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 76556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 73475 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 73469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1564 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 587 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,474 +161,464 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 371.369637 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.870030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 366.414967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7224 31.60% 31.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5292 23.15% 54.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2324 10.16% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1423 6.22% 71.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 882 3.86% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 607 2.65% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 442 1.93% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 389 1.70% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4280 18.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22863 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.004867 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 117.614100 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 4100 99.78% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 6 0.15% 99.93% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.633118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.344584 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.042030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13828 38.72% 38.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8395 23.51% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3582 10.03% 72.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1962 5.49% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1409 3.95% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 988 2.77% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 701 1.96% 86.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 566 1.59% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4278 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35709 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4100 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.539756 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 117.618727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 4089 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.20% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4109 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.208323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.187975 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.583219 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1 44 1.07% 1.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2-3 6 0.15% 1.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-5 4 0.10% 1.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6-7 4 0.10% 1.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-9 2 0.05% 1.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14-15 4 0.10% 1.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2755 67.05% 68.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 853 20.76% 89.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 55 1.34% 90.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 41 1.00% 91.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 36 0.88% 92.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 45 1.10% 93.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 25 0.61% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 36 0.88% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 20 0.49% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 26 0.63% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 28 0.68% 96.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 10 0.24% 97.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 24 0.58% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 13 0.32% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 21 0.51% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 18 0.44% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 6 0.15% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 4 0.10% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 10 0.24% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 2 0.05% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 4 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 9 0.22% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4109 # Writes before turning the bus around for reads -system.physmem.totQLat 2553947750 # Total ticks spent queuing -system.physmem.totMemAccLat 4444375250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 493180000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1397247500 # Total ticks spent accessing banks -system.physmem.avgQLat 25892.65 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14165.70 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 4100 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4100 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.916341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.808533 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.372443 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1 61 1.49% 1.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2-3 8 0.20% 1.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-5 2 0.05% 1.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6-7 3 0.07% 1.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-9 1 0.02% 1.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10-11 1 0.02% 1.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-13 1 0.02% 1.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14-15 5 0.12% 2.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2769 67.54% 69.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 821 20.02% 89.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 36 0.88% 90.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 38 0.93% 91.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 31 0.76% 92.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 30 0.73% 92.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 54 1.32% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 53 1.29% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 24 0.59% 96.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 28 0.68% 96.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 12 0.29% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 22 0.54% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 34 0.83% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 16 0.39% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 10 0.24% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 6 0.15% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 8 0.20% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 2 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 4 0.10% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 5 0.12% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 2 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 2 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 8 0.20% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4100 # Writes before turning the bus around for reads +system.physmem.totQLat 2438372750 # Total ticks spent queuing +system.physmem.totMemAccLat 4248047750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 482580000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25263.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45058.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.23 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44013.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.06 # Average write queue length when enqueuing -system.physmem.readRowHits 80976 # Number of row buffer hits during reads -system.physmem.writeRowHits 55952 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.78 # Row buffer hit rate for writes -system.physmem.avgGap 29592881.75 # Average gap between requests -system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6444852 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 422305 # Transaction distribution -system.membus.trans_dist::ReadResp 422303 # Transaction distribution -system.membus.trans_dist::WriteReq 6370 # Transaction distribution -system.membus.trans_dist::WriteResp 6370 # Transaction distribution -system.membus.trans_dist::Writeback 74818 # Transaction distribution -system.membus.trans_dist::UpgradeReq 747 # Transaction distribution -system.membus.trans_dist::UpgradeResp 747 # Transaction distribution -system.membus.trans_dist::ReadExReq 78043 # Transaction distribution -system.membus.trans_dist::ReadExResp 78043 # Transaction distribution -system.membus.trans_dist::MessageReq 885 # Transaction distribution -system.membus.trans_dist::MessageResp 885 # Transaction distribution +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.46 # Average write queue length when enqueuing +system.physmem.readRowHits 79177 # Number of row buffer hits during reads +system.physmem.writeRowHits 55086 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.97 # Row buffer hit rate for writes +system.physmem.avgGap 30177935.67 # Average gap between requests +system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4939989046000 # Time in different power states +system.physmem.memoryStateTime::REF 171431260000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22454250000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 6437004 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 422289 # Transaction distribution +system.membus.trans_dist::ReadResp 422287 # Transaction distribution +system.membus.trans_dist::WriteReq 6118 # Transaction distribution +system.membus.trans_dist::WriteResp 6118 # Transaction distribution +system.membus.trans_dist::Writeback 73475 # Transaction distribution +system.membus.trans_dist::UpgradeReq 843 # Transaction distribution +system.membus.trans_dist::UpgradeResp 843 # Transaction distribution +system.membus.trans_dist::ReadExReq 76388 # Transaction distribution +system.membus.trans_dist::ReadExResp 76388 # Transaction distribution +system.membus.trans_dist::MessageReq 850 # Transaction distribution +system.membus.trans_dist::MessageResp 850 # Transaction distribution system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 309432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 212160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308658 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497514 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 204215 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1019134 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 66106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 66106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1087010 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158682 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995073 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8391680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9545435 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2715776 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2715776 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12264751 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32837413 # Total data (bytes) -system.membus.snoop_data_through_bus 287680 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 162853500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::total 1010391 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 69253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 69253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1081344 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158115 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995025 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8047552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9200692 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2838016 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2838016 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12042108 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32720690 # Total data (bytes) +system.membus.snoop_data_through_bus 326080 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 162128500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315156500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315102000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1770000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 821391499 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 806327999 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 885000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 850000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1625485201 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1598914090 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 213559749 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 224687998 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 104632 # number of replacements -system.l2c.tags.tagsinuse 64756.494280 # Cycle average of tags in use -system.l2c.tags.total_refs 3664896 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168700 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.724339 # Average number of references to valid blocks. +system.l2c.tags.replacements 103794 # number of replacements +system.l2c.tags.tagsinuse 64810.608353 # Cycle average of tags in use +system.l2c.tags.total_refs 3657966 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167984 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.775681 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51511.220399 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131167 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1228.361726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4265.224240 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 282.161159 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1465.784470 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.322385 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.042344 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1365.490726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4627.755664 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.785999 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51486.278563 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125055 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1295.377972 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4270.696448 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 302.542141 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1483.932036 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.824361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1349.140567 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4614.691210 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.785618 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.018743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.065082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004305 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022366 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000158 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020836 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.070614 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988106 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64068 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2732 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7219 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53790 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977600 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33688290 # Number of tag accesses -system.l2c.tags.data_accesses 33688290 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 22061 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11615 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 344470 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 519863 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10165 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5243 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 139799 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 221175 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 54188 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 10719 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 354261 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 566062 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2259621 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.019766 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.065166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004616 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.022643 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.020586 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.070415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.988931 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64190 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3206 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7166 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53256 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979462 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33587388 # Number of tag accesses +system.l2c.tags.data_accesses 33587388 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 20605 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 339595 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 520668 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10906 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 151391 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 219548 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 53731 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 8985 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 345046 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 563659 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2251830 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1545523 # number of Writeback hits -system.l2c.Writeback_hits::total 1545523 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 137 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 93 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 276 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 73996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 34699 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 57996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166691 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22061 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 344470 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 593859 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10165 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5243 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 139799 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 255874 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 54188 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 10719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 354261 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 624058 # number of demand (read+write) hits -system.l2c.demand_hits::total 2426314 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22061 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11617 # number of overall hits -system.l2c.overall_hits::cpu0.inst 344470 # number of overall hits -system.l2c.overall_hits::cpu0.data 593859 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10165 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5243 # number of overall hits -system.l2c.overall_hits::cpu1.inst 139799 # number of overall hits -system.l2c.overall_hits::cpu1.data 255874 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 54188 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10719 # number of overall hits -system.l2c.overall_hits::cpu2.inst 354261 # number of overall hits -system.l2c.overall_hits::cpu2.data 624058 # number of overall hits -system.l2c.overall_hits::total 2426314 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6868 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 16704 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1533 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3888 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 26 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 6752 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 12246 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48023 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 754 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 206 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1331 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 74862 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 23137 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 32148 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130147 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6868 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 91566 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1533 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 27025 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 26 # 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miss rate for WriteReq accesses @@ -822,56 +796,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 141998.660419 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 141998.660419 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 121322.581464 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 121322.581464 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 121716.332983 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121716.332983 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 121716.332983 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121716.332983 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 88529 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144535.209890 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 144535.209890 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 124665.724658 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 124665.724658 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125045.343208 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125045.343208 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 88795 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7334 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8200 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.071039 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.828659 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 744 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 744 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 22928 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 22928 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 23672 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 23672 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 23672 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 23672 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90079785 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90079785 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4474936508 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4474936508 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4565016293 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4565016293 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4565016293 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4565016293 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.820287 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.820287 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.490753 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.490753 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.497029 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.497029 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.497029 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.497029 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121074.979839 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 121074.979839 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195173.434578 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 195173.434578 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 192844.554453 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 192844.554453 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 733 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24176 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 24176 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 24909 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 24909 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 24909 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 24909 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93385041 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93385041 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4566242660 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4566242660 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4659627701 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4659627701 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.805495 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.805495 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.517466 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.517466 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.522969 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.522969 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127401.147340 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127401.147340 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 188875.027300 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 188875.027300 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -885,476 +859,510 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52329028 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1794981 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1794440 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6370 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6370 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 902417 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 716 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 716 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 170908 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 147982 # Transaction distribution +system.toL2Bus.throughput 52260442 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1795853 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1795321 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 6118 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 6118 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 903975 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 804 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 804 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 176511 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 152342 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1004724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3613728 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 35279 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 136436 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4790167 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32150080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119808027 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 127712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 515032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152600851 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268845429 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 114024 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5038805323 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1006951 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3618137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34540 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 139444 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4799072 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32221504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120018356 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 123320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 517264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 152880444 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268161042 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 137520 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5048228823 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 931500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2262930320 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2267749080 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4696428413 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4703679799 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19332464 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 19140467 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 72173756 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 74891774 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1276348 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 149977 # Transaction distribution -system.iobus.trans_dist::ReadResp 149977 # Transaction distribution -system.iobus.trans_dist::WriteReq 28411 # Transaction distribution -system.iobus.trans_dist::WriteResp 28411 # Transaction distribution -system.iobus.trans_dist::MessageReq 885 # Transaction distribution -system.iobus.trans_dist::MessageResp 885 # Transaction distribution +system.iobus.throughput 1277477 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 149797 # Transaction distribution +system.iobus.trans_dist::ReadResp 149797 # Transaction distribution +system.iobus.trans_dist::WriteReq 29441 # Transaction distribution +system.iobus.trans_dist::WriteResp 29441 # Transaction distribution +system.iobus.trans_dist::MessageReq 850 # Transaction distribution +system.iobus.trans_dist::MessageResp 850 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5752 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5466 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 558 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287032 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287110 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 224 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 309432 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 47344 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 47344 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1770 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1770 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 358546 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 308658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49818 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49818 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 360176 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3245 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 279 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143516 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143555 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 448 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6724 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6513 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 158682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1503808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1503808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3540 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3540 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1666030 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6560144 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2116890 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 158115 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1583592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1583592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1745107 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6558405 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2044244 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4753000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4518000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 383000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 367000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 33000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143517000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143556000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 264000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 178000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10048000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9750000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 209101042 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 220209699 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303949000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 303393000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 28759251 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 30099002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 885000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 850000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1144797664 # number of cpu cycles simulated +system.cpu0.numCycles 1160444400 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72999922 # Number of instructions committed -system.cpu0.committedOps 148305710 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 136279674 # Number of integer alu accesses +system.cpu0.committedInsts 72635405 # Number of instructions committed +system.cpu0.committedOps 147758080 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 135731001 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1016299 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14345558 # number of instructions that are conditional controls -system.cpu0.num_int_insts 136279674 # number of integer instructions +system.cpu0.num_func_calls 1010341 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14309822 # number of instructions that are conditional controls +system.cpu0.num_int_insts 135731001 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 250792350 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116890419 # number of times the integer registers were written +system.cpu0.num_int_register_reads 249546871 # number of times the integer registers were read +system.cpu0.num_int_register_writes 116495894 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84577193 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56435831 # number of times the CC registers were written -system.cpu0.num_mem_refs 14370687 # number of memory refs -system.cpu0.num_load_insts 10454117 # Number of load instructions -system.cpu0.num_store_insts 3916570 # Number of store instructions -system.cpu0.num_idle_cycles 1087719763.352511 # Number of idle cycles -system.cpu0.num_busy_cycles 57077900.647489 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049859 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950141 # Percentage of idle cycles -system.cpu0.Branches 15728655 # Number of branches fetched +system.cpu0.num_cc_register_reads 84252648 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 56217158 # number of times the CC registers were written +system.cpu0.num_mem_refs 14168966 # number of memory refs +system.cpu0.num_load_insts 10366088 # Number of load instructions +system.cpu0.num_store_insts 3802878 # Number of store instructions +system.cpu0.num_idle_cycles 1101978015.213226 # Number of idle cycles +system.cpu0.num_busy_cycles 58466384.786774 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050383 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949617 # Percentage of idle cycles +system.cpu0.Branches 15683494 # Number of branches fetched +system.cpu0.op_class::No_OpClass 100234 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 133376064 90.27% 90.33% # Class of executed instruction +system.cpu0.op_class::IntMult 62929 0.04% 90.38% # Class of executed instruction +system.cpu0.op_class::IntDiv 50413 0.03% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::MemRead 10366088 7.02% 97.43% # Class of executed instruction +system.cpu0.op_class::MemWrite 3802878 2.57% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 147758606 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 853193 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.838528 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129757026 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 853705 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 151.992815 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147468978000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 295.878537 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 138.959383 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 76.000608 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.577888 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.271405 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.148439 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997732 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 850385 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.795763 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129494150 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 850897 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 152.185458 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147465545000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 306.120317 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.033154 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 67.642292 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.597891 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.267643 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.132114 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997648 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131484548 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131484548 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 88843413 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38144708 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2768905 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129757026 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 88843413 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38144708 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2768905 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129757026 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 88843413 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38144708 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2768905 # number of overall hits -system.cpu0.icache.overall_hits::total 129757026 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 351339 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 141332 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 381133 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 873804 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 351339 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 141332 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 381133 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 873804 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 351339 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 141332 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 381133 # number of overall misses -system.cpu0.icache.overall_misses::total 873804 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1941508750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5443063468 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7384572218 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1941508750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5443063468 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7384572218 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1941508750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5443063468 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7384572218 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 89194752 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 38286040 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3150038 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130630830 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 89194752 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 38286040 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3150038 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130630830 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 89194752 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 38286040 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3150038 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130630830 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003939 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003691 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120993 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006689 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003939 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003691 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120993 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006689 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003939 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003691 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120993 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006689 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13737.219809 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14281.270496 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8451.062501 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13737.219809 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14281.270496 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8451.062501 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13737.219809 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14281.270496 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8451.062501 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4847 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 131214877 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 131214877 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 88330268 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38415628 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2748254 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129494150 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 88330268 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38415628 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2748254 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129494150 # 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number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 389134 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 389134 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 389134 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 223619 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 577178 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 800797 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62158 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 90935 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 153093 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 285777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 668113 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 953890 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 285777 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 668113 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 953890 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2734176493 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8368429033 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11102605526 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032053179 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2876927496 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4908980675 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4766229672 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11245356529 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16011586201 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4766229672 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11245356529 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16011586201 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30475246000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33186567000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63661813000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 395642000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 753351500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1148993500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30870888000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33939918500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64810806500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086110 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118022 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060483 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036684 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031302 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.044084 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.044084 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12226.941776 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14498.870423 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13864.444455 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32691.740066 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31637.185858 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32065.350310 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1365,307 +1373,377 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608015730 # number of cpu cycles simulated +system.cpu1.numCycles 2606021866 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34716890 # Number of instructions committed -system.cpu1.committedOps 67541836 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62669042 # Number of integer alu accesses +system.cpu1.committedInsts 34914128 # Number of instructions committed +system.cpu1.committedOps 67869824 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 62995293 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 430919 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6413966 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62669042 # number of integer instructions +system.cpu1.num_func_calls 438942 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6428622 # number of instructions that are conditional controls +system.cpu1.num_int_insts 62995293 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 115548964 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54160900 # number of times the integer registers were written +system.cpu1.num_int_register_reads 116271698 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54373004 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35562537 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26614034 # number of times the CC registers were written -system.cpu1.num_mem_refs 4364452 # number of memory refs -system.cpu1.num_load_insts 2756893 # Number of load instructions -system.cpu1.num_store_insts 1607559 # Number of store instructions -system.cpu1.num_idle_cycles 2483429860.768801 # Number of idle cycles -system.cpu1.num_busy_cycles 124585869.231199 # Number of busy cycles -system.cpu1.not_idle_fraction 0.047770 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.952230 # Percentage of idle cycles -system.cpu1.Branches 7003911 # Number of branches fetched +system.cpu1.num_cc_register_reads 35773637 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26686134 # number of times the CC registers were written +system.cpu1.num_mem_refs 4480510 # number of memory refs +system.cpu1.num_load_insts 2784988 # Number of load instructions +system.cpu1.num_store_insts 1695522 # Number of store instructions +system.cpu1.num_idle_cycles 2483027078.364504 # Number of idle cycles +system.cpu1.num_busy_cycles 122994787.635496 # Number of busy cycles +system.cpu1.not_idle_fraction 0.047196 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.952804 # Percentage of idle cycles +system.cpu1.Branches 7029914 # Number of branches fetched +system.cpu1.op_class::No_OpClass 31008 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 63308001 93.28% 93.32% # Class of executed instruction +system.cpu1.op_class::IntMult 28040 0.04% 93.37% # Class of executed instruction +system.cpu1.op_class::IntDiv 22580 0.03% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::MemRead 2784988 4.10% 97.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 1695522 2.50% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 67870139 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28782114 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28782114 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 316524 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26348266 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25752004 # Number of BTB hits +system.cpu2.branchPred.lookups 28758894 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28758894 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 306803 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26351534 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25737629 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.736997 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 537542 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63717 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155552038 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.670325 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 530881 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 61512 # Number of incorrect RAS predictions. +system.cpu2.numCycles 154845080 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9686701 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141772190 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28782114 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26289546 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54340809 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1470890 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 70055 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24627328 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7901 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 23768 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 376 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3150040 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 144648 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2015 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 89899907 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.110146 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.408280 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9460785 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 141747704 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28758894 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26268510 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54302787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1434244 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 58972 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 24471854 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6545 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 20028 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3117082 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 139514 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1749 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 89437217 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.124405 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.409858 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 35694732 39.70% 39.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 594255 0.66% 40.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23712499 26.38% 66.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 314699 0.35% 67.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 599600 0.67% 67.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 812421 0.90% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 338881 0.38% 69.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 517837 0.58% 69.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27314983 30.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 35270123 39.44% 39.44% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 589507 0.66% 40.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23704151 26.50% 66.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 307246 0.34% 66.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 603965 0.68% 67.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 802586 0.90% 68.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 334965 0.37% 68.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 517417 0.58% 69.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27307257 30.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 89899907 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185032 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.911413 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 11154829 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 23540580 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 30801007 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1287318 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1141583 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278785410 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 11 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1141583 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12143079 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13933433 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4524497 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 30930733 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5252059 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277791777 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 7238 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2464468 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2117220 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 331976691 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 604531856 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371338716 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321781805 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10194886 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 148461 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 149473 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11392573 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6171654 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3395563 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 345995 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 292325 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276091246 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 414813 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274477250 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 60541 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7173454 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11041443 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 56132 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 89899907 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.053143 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.400877 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 89437217 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185727 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.915416 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10926187 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 23367960 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 31523393 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1298286 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1115198 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278635226 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 49 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1115198 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11921655 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13834152 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4411879 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 31656208 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5292001 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277656292 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6764 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2483668 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2130930 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 331880087 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 604361998 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371268132 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 6 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321920244 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 9959841 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 147988 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 148926 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11485411 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6218482 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3410117 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 341148 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 274139 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276004640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 412430 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274449569 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 59781 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7023554 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10820295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 55045 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 89437217 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.068628 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.396853 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 26563563 29.55% 29.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6130901 6.82% 36.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3934206 4.38% 40.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2710119 3.01% 43.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25036419 27.85% 71.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1342117 1.49% 73.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23840310 26.52% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 288717 0.32% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 53555 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 26098480 29.18% 29.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6131096 6.86% 36.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3936751 4.40% 40.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2730796 3.05% 43.49% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25025448 27.98% 71.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1337810 1.50% 72.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23830586 26.65% 99.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 291775 0.33% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 54475 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 89899907 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 89437217 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 122290 33.50% 33.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 245 0.07% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 189949 52.03% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 52573 14.40% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 125312 33.75% 33.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 120 0.03% 33.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 109 0.03% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 191005 51.44% 85.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 54802 14.76% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 80536 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264658650 96.42% 96.45% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54855 0.02% 96.47% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48402 0.02% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6455691 2.35% 98.84% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3179116 1.16% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 76601 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264560846 96.40% 96.42% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54414 0.02% 96.44% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50942 0.02% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6508971 2.37% 98.83% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3197795 1.17% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274477250 # Type of FU issued -system.cpu2.iq.rate 1.764537 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 365057 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001330 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 639321511 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 283683445 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273115126 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 61 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274761742 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 29 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 634301 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274449569 # Type of FU issued +system.cpu2.iq.rate 1.772414 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 371348 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001353 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 638809448 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 283444416 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 273102485 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 12 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 274744310 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 6 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 641561 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1002623 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6718 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4440 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 510444 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 993516 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6753 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4280 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 500329 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656391 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10280 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656426 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10045 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1141583 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9227965 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 815382 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 276506059 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 71664 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6171654 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3395563 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 234992 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 633068 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3849 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4440 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 176570 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 182317 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 358887 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273973436 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6342946 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 503814 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1115198 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9119918 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 823405 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 276417070 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 70631 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6218482 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3410117 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 233790 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 637954 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3900 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4280 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 173413 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 173644 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 347057 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273959168 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6398525 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 490400 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9455734 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27867681 # Number of branches executed -system.cpu2.iew.exec_stores 3112788 # Number of stores executed -system.cpu2.iew.exec_rate 1.761298 # Inst execution rate -system.cpu2.iew.wb_sent 273823666 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273115144 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212986974 # num instructions producing a value -system.cpu2.iew.wb_consumers 348231532 # num instructions consuming a value +system.cpu2.iew.exec_refs 9531292 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27864904 # Number of branches executed +system.cpu2.iew.exec_stores 3132767 # Number of stores executed +system.cpu2.iew.exec_rate 1.769247 # Inst execution rate +system.cpu2.iew.wb_sent 273810478 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 273102491 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212979431 # num instructions producing a value +system.cpu2.iew.wb_consumers 348314367 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.755780 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611625 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.763714 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611457 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7474898 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 358681 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 318992 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 88758324 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.031021 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.870805 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7316358 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357385 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 309115 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 88322018 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.046767 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.870309 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 31301057 35.27% 35.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4393147 4.95% 40.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1229186 1.38% 41.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24655081 27.78% 69.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 868070 0.98% 70.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 585819 0.66% 71.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 347474 0.39% 71.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23302544 26.25% 97.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2075946 2.34% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 30852434 34.93% 34.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4395307 4.98% 39.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1238857 1.40% 41.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24650858 27.91% 69.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 865215 0.98% 70.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 585749 0.66% 70.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 347954 0.39% 71.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23291491 26.37% 97.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2094153 2.37% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 88758324 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136214259 # Number of instructions committed -system.cpu2.commit.committedOps 269028357 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 88322018 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136303075 # Number of instructions committed +system.cpu2.commit.committedOps 269096585 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8054150 # Number of memory references committed -system.cpu2.commit.loads 5169031 # Number of loads committed -system.cpu2.commit.membars 165004 # Number of memory barriers committed -system.cpu2.commit.branches 27530478 # Number of branches committed +system.cpu2.commit.refs 8134753 # Number of memory references committed +system.cpu2.commit.loads 5224965 # Number of loads committed +system.cpu2.commit.membars 164376 # Number of memory barriers committed +system.cpu2.commit.branches 27532187 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245624895 # Number of committed integer instructions. -system.cpu2.commit.function_calls 430032 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2075946 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 245708361 # Number of committed integer instructions. +system.cpu2.commit.function_calls 429087 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 43848 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 260815603 96.92% 96.94% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52558 0.02% 96.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 49823 0.02% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5224965 1.94% 98.92% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2909788 1.08% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 269096585 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2094153 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 363157720 # The number of ROB reads -system.cpu2.rob.rob_writes 554152180 # The number of ROB writes -system.cpu2.timesIdled 477715 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65652131 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4906975665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136214259 # Number of Instructions Simulated -system.cpu2.committedOps 269028357 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136214259 # Number of Instructions Simulated -system.cpu2.cpi 1.141966 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.141966 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.875683 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.875683 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364409735 # number of integer regfile reads -system.cpu2.int_regfile_writes 218808578 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73042 # number of floating regfile reads -system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139320542 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107246688 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88724841 # number of misc regfile reads -system.cpu2.misc_regfile_writes 132896 # number of misc regfile writes +system.cpu2.rob.rob_reads 362613065 # The number of ROB reads +system.cpu2.rob.rob_writes 553944877 # The number of ROB writes +system.cpu2.timesIdled 473034 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65407863 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4900873955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136303075 # Number of Instructions Simulated +system.cpu2.committedOps 269096585 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 136303075 # Number of Instructions Simulated +system.cpu2.cpi 1.136035 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.136035 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.880254 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.880254 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364552649 # number of integer regfile reads +system.cpu2.int_regfile_writes 218803003 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72918 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 139316304 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107298284 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88761943 # number of misc regfile reads +system.cpu2.misc_regfile_writes 132629 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |