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-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini1552
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr10
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout17
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt1579
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal184
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini1169
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr10
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout16
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt781
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal183
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini1608
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr11
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout17
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt3203
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal184
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini1229
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr11
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout16
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt1550
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal183
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini1320
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr570
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout11
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt1111
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal183
25 files changed, 16708 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
new file mode 100644
index 000000000..6a2ebe226
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
@@ -0,0 +1,1552 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=atomic
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=6
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=16
+cpu_side=system.cpu0.dcache_port
+mem_side=system.cpu0.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.dtb
+
+[system.cpu0.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.cpu0.toL2Bus.slave[0]
+
+[system.cpu0.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu0.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu0.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.itb
+
+[system.cpu0.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.istage2_mmu.stage2_tlb.walker
+
+[system.cpu0.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+cache_snoop=false
+clk_domain=system.cpu_clk_domain
+degree=8
+eventq_index=0
+latency=1
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
+sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.cpu0.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu1.dstage2_mmu
+dtb=system.cpu1.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+istage2_mmu=system.cpu1.istage2_mmu
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu1.tracer
+width=1
+workload=
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=6
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.dcache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=16
+cpu_side=system.cpu1.dcache_port
+mem_side=system.cpu1.toL2Bus.slave[1]
+
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu1.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.dtb
+
+[system.cpu1.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[3]
+
+[system.cpu1.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.cpu1.toL2Bus.slave[0]
+
+[system.cpu1.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+cache_snoop=false
+clk_domain=system.cpu_clk_domain
+degree=8
+eventq_index=0
+latency=1
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
+sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=true
+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2415919103
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.l2c.cpu_side
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr
new file mode 100644
index 000000000..0a1da41f0
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr
@@ -0,0 +1,10 @@
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout
new file mode 100644
index 000000000..03afdc9d6
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout
@@ -0,0 +1,17 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:01:47
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x52fab00 0x52fab00
+ 0: system.cpu1.isa: ISA system set to: 0x52fab00 0x52fab00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 47256535568000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
new file mode 100644
index 000000000..b412f009d
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
@@ -0,0 +1,1579 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 47.216814 # Number of seconds simulated
+sim_ticks 47216814145000 # Number of ticks simulated
+final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1225013 # Simulator instruction rate (inst/s)
+host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59296512316 # Simulator tick rate (ticks/s)
+host_mem_usage 723320 # Number of bytes of host memory used
+host_seconds 796.28 # Real time elapsed on the host
+sim_insts 975457230 # Number of instructions simulated
+sim_ops 1147538415 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3911220 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 221184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2638152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 38475968 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 412928 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3911220 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2638152 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
+system.physmem.bytes_written::total 100583888 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 101520 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 550562 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3483 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 3456 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 41328 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 601205 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6452 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1312424 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1571298 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1573901 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3263 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 82835 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 4721 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 4684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 55873 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2130256 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2129815 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3263 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.walks 125229 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 92662773 # DTB read hits
+system.cpu0.dtb.read_misses 88786 # DTB read misses
+system.cpu0.dtb.write_hits 85694958 # DTB write hits
+system.cpu0.dtb.write_misses 36443 # DTB write misses
+system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 92751559 # DTB read accesses
+system.cpu0.dtb.write_accesses 85731401 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 178357731 # DTB hits
+system.cpu0.dtb.misses 125229 # DTB misses
+system.cpu0.dtb.accesses 178482960 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.walks 61377 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 497696393 # ITB inst hits
+system.cpu0.itb.inst_misses 61377 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses
+system.cpu0.itb.hits 497696393 # DTB hits
+system.cpu0.itb.misses 61377 # DTB misses
+system.cpu0.itb.accesses 497757770 # DTB accesses
+system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 497466384 # Number of instructions committed
+system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses
+system.cpu0.num_func_calls 28869117 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 536103359 # number of integer instructions
+system.cpu0.num_fp_insts 526132 # number of float instructions
+system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written
+system.cpu0.num_mem_refs 178459396 # number of memory refs
+system.cpu0.num_load_insts 92737001 # Number of load instructions
+system.cpu0.num_store_insts 85722395 # Number of store instructions
+system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles
+system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
+system.cpu0.Branches 111287587 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction
+system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction
+system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction
+system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::total 585300003 # Class of executed instruction
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements 6272759 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 172015744 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 6273271 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 27.420423 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 363162158 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 363162158 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 86214905 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 86214905 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 80919887 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 80919887 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215655 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 215655 # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036774 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 2036774 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 167134792 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 167134792 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 167350447 # number of overall hits
+system.cpu0.dcache.overall_hits::total 167350447 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 3309378 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 3309378 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1475526 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1475526 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772138 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 772138 # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158369 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 158369 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 4784904 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 4784904 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 5557042 # number of overall misses
+system.cpu0.dcache.overall_misses::total 5557042 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524283 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 89524283 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395413 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 82395413 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093720 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 171919696 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 171919696 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 172907489 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 172907489 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017908 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.017908 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781680 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781680 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072145 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072145 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027832 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.027832 # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses
+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 4469723 # number of writebacks
+system.cpu0.dcache.writebacks::total 4469723 # number of writebacks
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.tags.replacements 5539081 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
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+system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
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+system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses
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+system.cpu0.icache.overall_misses::total 5539598 # number of overall misses
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+system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
+system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
+system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements 2710840 # number of replacements
+system.cpu0.l2cache.tags.tagsinuse 16208.843540 # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs 11548798 # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs 2726836 # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs 4.235237 # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 5735.641953 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.550576 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.046098 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4528.763909 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5835.841004 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks 0.350076 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003268 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003360 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276414 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.356191 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total 0.989309 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15944 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1162 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4591 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5299 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4659 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973145 # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses 278654950 # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses 278654950 # Number of data accesses
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+system.cpu0.l2cache.Writeback_hits::total 4469723 # number of Writeback hits
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+system.cpu0.l2cache.UpgradeReq_hits::total 3521 # number of UpgradeReq hits
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+system.cpu0.l2cache.overall_hits::cpu0.data 3578889 # number of overall hits
+system.cpu0.l2cache.overall_hits::total 8961389 # number of overall hits
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+system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608598 # number of WriteInvalidateReq misses
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+system.cpu0.l2cache.SCUpgradeReq_misses::total 158369 # number of SCUpgradeReq misses
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+system.cpu0.l2cache.demand_misses::cpu0.data 1966666 # number of demand (read+write) misses
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+system.cpu0.l2cache.overall_misses::cpu0.data 1966666 # number of overall misses
+system.cpu0.l2cache.overall_misses::total 2554776 # number of overall misses
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+system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201332 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total 10171942 # number of ReadReq accesses(hits+misses)
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+system.cpu0.l2cache.Writeback_accesses::total 4469723 # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831335 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831335 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131664 # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total 131664 # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158369 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total 158369 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344223 # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total 1344223 # number of ReadExReq accesses(hits+misses)
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+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150346 # number of demand (read+write) accesses
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+system.cpu0.l2cache.demand_accesses::cpu0.data 5545555 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total 11516165 # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.data 5545555 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total 11516165 # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057155 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102571 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299252 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total 0.181417 # miss rate for ReadReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.732073 # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.732073 # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973258 # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973258 # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527747 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527747 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057155 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102571 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354638 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total 0.221843 # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057155 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102571 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354638 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total 0.221843 # miss rate for overall accesses
+system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu0.l2cache.writebacks::writebacks 1573452 # number of writebacks
+system.cpu0.l2cache.writebacks::total 1573452 # number of writebacks
+system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.toL2Bus.trans_dist::ReadReq 10363949 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 10363949 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 32448 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 32448 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 4469723 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831335 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831335 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 131664 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158369 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 290033 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1344223 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1344223 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165446 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17933523 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.walks 144041 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 90153061 # DTB read hits
+system.cpu1.dtb.read_misses 111753 # DTB read misses
+system.cpu1.dtb.write_hits 81132787 # DTB write hits
+system.cpu1.dtb.write_misses 32288 # DTB write misses
+system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 90264814 # DTB read accesses
+system.cpu1.dtb.write_accesses 81165075 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 171285848 # DTB hits
+system.cpu1.dtb.misses 144041 # DTB misses
+system.cpu1.dtb.accesses 171429889 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.walks 60885 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 478248118 # ITB inst hits
+system.cpu1.itb.inst_misses 60885 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses
+system.cpu1.itb.hits 478248118 # DTB hits
+system.cpu1.itb.misses 60885 # DTB misses
+system.cpu1.itb.accesses 478309003 # DTB accesses
+system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 477990846 # Number of instructions committed
+system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses
+system.cpu1.num_func_calls 28237407 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 516282159 # number of integer instructions
+system.cpu1.num_fp_insts 374678 # number of float instructions
+system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written
+system.cpu1.num_mem_refs 171406825 # number of memory refs
+system.cpu1.num_load_insts 90251973 # Number of load instructions
+system.cpu1.num_store_insts 81154852 # Number of store instructions
+system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
+system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
+system.cpu1.Branches 106497601 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction
+system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction
+system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
+system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction
+system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 562879339 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements 5945049 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 76990336 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 76990336 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63447 # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total 63447 # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048907 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 2048907 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 160687900 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 160687900 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 160875754 # number of overall hits
+system.cpu1.dcache.overall_hits::total 160875754 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1453140 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1453140 # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427052 # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total 427052 # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158842 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 158842 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 4811362 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 4811362 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 5603713 # number of overall misses
+system.cpu1.dcache.overall_misses::total 5603713 # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total 490499 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870648 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870648 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071947 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071947 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks 4030826 # number of writebacks
+system.cpu1.dcache.writebacks::total 4030826 # number of writebacks
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements 4741297 # number of replacements
+system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits
+system.cpu1.icache.overall_hits::total 473560604 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses
+system.cpu1.icache.overall_misses::total 4741809 # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses
+system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
+system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
+system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements 2278914 # number of replacements
+system.cpu1.l2cache.tags.tagsinuse 13451.937852 # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs 10861278 # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs 2294953 # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs 4.732680 # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 5180.760257 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.434503 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.707533 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2828.453932 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5282.581627 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks 0.316209 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004177 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005597 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.172635 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322423 # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1583 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5963 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4534 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3771 # Occupied blocks per task id
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+system.cpu1.l2cache.tags.tag_accesses 254019378 # Number of tag accesses
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+system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265480 # number of WriteInvalidateReq misses
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+system.cpu1.l2cache.demand_misses::total 2488114 # number of demand (read+write) misses
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+system.cpu1.l2cache.overall_misses::cpu1.data 1941201 # number of overall misses
+system.cpu1.l2cache.overall_misses::total 2488114 # number of overall misses
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337607 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150938 # number of ReadReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total 9527747 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks 4030826 # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total 4030826 # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137456 # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total 137456 # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158842 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total 158842 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337607 # number of demand (read+write) accesses
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+system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total 10843637 # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337607 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150938 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total 10843637 # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064795 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110642 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288431 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total 0.187496 # miss rate for ReadReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.621957 # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.621957 # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971882 # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971882 # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533250 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533250 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064795 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110642 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345823 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total 0.229454 # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064795 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110642 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345823 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total 0.229454 # miss rate for overall accesses
+system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu1.l2cache.writebacks::writebacks 1183487 # number of writebacks
+system.cpu1.l2cache.writebacks::total 1183487 # number of writebacks
+system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 137456 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16729164 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 27412486 # Packet count per connected master and slave (bytes)
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+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644579516 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 19274314 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29906 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements 115585 # number of replacements
+system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1040793 # Number of tag accesses
+system.iocache.tags.data_accesses 1040793 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8876 # number of overall misses
+system.iocache.overall_misses::total 8916 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
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+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215456868 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 215667865 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 229897305 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 4414869 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4414869 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 4414869 # Request fanout histogram
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 117306 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal
new file mode 100644
index 000000000..4a0363ec3
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal
@@ -0,0 +1,184 @@
+[ 0.000000] Initializing cgroup subsys cpu
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
+[ 0.000000] Memory limited to 256MB
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
+[ 0.000000] On node 0 totalpages: 65536
+[ 0.000000] DMA zone: 896 pages used for memmap
+[ 0.000000] DMA zone: 0 pages reserved
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
+[ 0.000000] Virtual kernel memory layout:
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[ 0.000000] Preemptible hierarchical RCU implementation.
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000013] Console: colour dummy device 80x25
+[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000015] pid_max: default: 32768 minimum: 301
+[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000066] hw perfevents: no hardware support available
+[ 0.060015] CPU1: Booted secondary processor
+[ 1.080050] CPU2: failed to come online
+[ 2.100100] CPU3: failed to come online
+[ 2.100101] Brought up 2 CPUs
+[ 2.100102] SMP: Total of 2 processors activated.
+[ 2.100134] devtmpfs: initialized
+[ 2.100536] atomic64_test: passed
+[ 2.100559] regulator-dummy: no parameters
+[ 2.100800] NET: Registered protocol family 16
+[ 2.100894] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.100898] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.100937] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.100938] Serial: AMBA PL011 UART driver
+[ 2.101059] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.101082] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.101116] console [ttyAMA0] enabled
+[ 2.101154] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.101168] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.101183] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.101195] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.140179] 3V3: 3300 mV
+[ 2.140202] vgaarb: loaded
+[ 2.140232] SCSI subsystem initialized
+[ 2.140246] libata version 3.00 loaded.
+[ 2.140272] usbcore: registered new interface driver usbfs
+[ 2.140279] usbcore: registered new interface driver hub
+[ 2.140288] usbcore: registered new device driver usb
+[ 2.140300] pps_core: LinuxPPS API ver. 1 registered
+[ 2.140301] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.140304] PTP clock support registered
+[ 2.140381] Switched to clocksource arch_sys_counter
+[ 2.141215] NET: Registered protocol family 2
+[ 2.141272] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.141277] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.141282] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.141285] TCP: reno registered
+[ 2.141286] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141288] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141303] NET: Registered protocol family 1
+[ 2.141330] RPC: Registered named UNIX socket transport module.
+[ 2.141331] RPC: Registered udp transport module.
+[ 2.141331] RPC: Registered tcp transport module.
+[ 2.141332] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.141334] PCI: CLS 0 bytes, default 64
+[ 2.141433] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.141477] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.143024] fuse init (API version 7.23)
+[ 2.143091] msgmni has been set to 469
+[ 2.143142] io scheduler noop registered
+[ 2.143175] io scheduler cfq registered (default)
+[ 2.143447] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.143448] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.143450] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.143451] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.143453] pci_bus 0000:00: scanning bus
+[ 2.143455] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.143457] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.143460] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.143476] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.143477] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.143479] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.143481] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.143482] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.143484] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.143486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.143503] pci_bus 0000:00: fixups for bus
+[ 2.143505] pci_bus 0000:00: bus scan returning with max=00
+[ 2.143506] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.143511] pci 0000:00:00.0: fixup irq: got 33
+[ 2.143512] pci 0000:00:00.0: assigning IRQ 33
+[ 2.143515] pci 0000:00:01.0: fixup irq: got 34
+[ 2.143516] pci 0000:00:01.0: assigning IRQ 34
+[ 2.143519] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.143520] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.143522] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.143524] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.143525] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.143527] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.143529] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.143531] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.143891] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.144060] ata_piix 0000:00:01.0: version 2.13
+[ 2.144062] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.144068] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.144250] scsi0 : ata_piix
+[ 2.144297] scsi1 : ata_piix
+[ 2.144314] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.144315] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.144376] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.144377] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.144381] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.144382] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290388] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290389] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290395] ata1.00: configured for UDMA/33
+[ 2.290412] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.290466] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.290469] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.290484] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.290486] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.290493] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.290548] sda: sda1
+[ 2.290610] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.410644] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.410646] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.410652] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.410653] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.410661] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.410662] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.410706] usbcore: registered new interface driver usb-storage
+[ 2.410735] mousedev: PS/2 mouse device common for all mice
+[ 2.410834] usbcore: registered new interface driver usbhid
+[ 2.410835] usbhid: USB HID core driver
+[ 2.410850] TCP: cubic registered
+[ 2.410852] NET: Registered protocol family 17
+
+[ 2.411050] devtmpfs: mounted
+[ 2.411057] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+
+
+[ 2.446370] udevd[609]: starting version 182
+Starting Bootlog daemon: bootlogd.
+[ 2.512067] random: dd urandom read with 17 bits of entropy available
+Populating dev cache
+net.ipv4.conf.default.rp_filter = 1
+net.ipv4.conf.all.rp_filter = 1
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+Mon Jan 27 08:00:00 UTC 2014
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+ INIT: Entering runlevel: 5
+Configuring network interfaces... udhcpc (v1.21.1) started
+[ 2.610614] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Sending discover...
+Sending discover...
+Sending discover...
+No lease, forking to background
+done.
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6
+rpcbind: cannot create socket for tcp6
+rpcbind: cannot get uid of '': Success
+done.
+creating NFS state directory: done
+starting statd: done
+Starting auto-serial-console: \ No newline at end of file
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
new file mode 100644
index 000000000..f454bf736
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
@@ -0,0 +1,1169 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=atomic
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=true
+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2415919103
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr
new file mode 100644
index 000000000..0a1da41f0
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr
@@ -0,0 +1,10 @@
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
new file mode 100644
index 000000000..0ec7f4b0f
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
@@ -0,0 +1,16 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:00:57
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x54cdb00 0x54cdb00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 51111167186000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
new file mode 100644
index 000000000..b381100ef
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
@@ -0,0 +1,781 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.111153 # Number of seconds simulated
+sim_ticks 51111152682000 # Number of ticks simulated
+final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1276359 # Simulator instruction rate (inst/s)
+host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 66258489115 # Simulator tick rate (ticks/s)
+host_mem_usage 712024 # Number of bytes of host memory used
+host_seconds 771.39 # Real time elapsed on the host
+sim_insts 984570519 # Number of instructions simulated
+sim_ops 1157031967 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
+system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 265715 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 184014035 # DTB read hits
+system.cpu.dtb.read_misses 194198 # DTB read misses
+system.cpu.dtb.write_hits 168232768 # DTB write hits
+system.cpu.dtb.write_misses 71517 # DTB write misses
+system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 184208233 # DTB read accesses
+system.cpu.dtb.write_accesses 168304285 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 352246803 # DTB hits
+system.cpu.dtb.misses 265715 # DTB misses
+system.cpu.dtb.accesses 352512518 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 126837 # Table walker walks requested
+system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 985047321 # ITB inst hits
+system.cpu.itb.inst_misses 126837 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 985174158 # ITB inst accesses
+system.cpu.itb.hits 985047321 # DTB hits
+system.cpu.itb.misses 126837 # DTB misses
+system.cpu.itb.accesses 985174158 # DTB accesses
+system.cpu.numCycles 102222322140 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 984570519 # Number of instructions committed
+system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses
+system.cpu.num_func_calls 57056367 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1060455466 # number of integer instructions
+system.cpu.num_fp_insts 880805 # number of float instructions
+system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read
+system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written
+system.cpu.num_mem_refs 352465606 # number of memory refs
+system.cpu.num_load_insts 184180431 # Number of load instructions
+system.cpu.num_store_insts 168285175 # Number of store instructions
+system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
+system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
+system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
+system.cpu.Branches 220088562 # Number of branches fetched
+system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction
+system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction
+system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
+system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 1157666593 # Class of executed instruction
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements 11612141 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits
+system.cpu.dcache.overall_hits::total 331514149 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses
+system.cpu.dcache.overall_misses::total 10164734 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
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+system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks
+system.cpu.dcache.writebacks::total 8921315 # number of writebacks
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements 14295641 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits
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+system.cpu.icache.overall_hits::total 970865862 # number of overall hits
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+system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::total 14296158 # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements 1722692 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use
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+system.cpu.l2cache.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245349 # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses
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+system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks
+system.cpu.l2cache.writebacks::total 1503415 # number of writebacks
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29851 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements 115463 # number of replacements
+system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
+system.iocache.tags.data_accesses 1039686 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8817 # number of overall misses
+system.iocache.overall_misses::total 8857 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks::writebacks 106631 # number of writebacks
+system.iocache.writebacks::total 106631 # number of writebacks
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 526062 # Transaction distribution
+system.membus.trans_dist::ReadResp 526062 # Transaction distribution
+system.membus.trans_dist::WriteReq 33606 # Transaction distribution
+system.membus.trans_dist::WriteResp 33606 # Transaction distribution
+system.membus.trans_dist::Writeback 1610046 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
+system.membus.trans_dist::ReadExReq 825948 # Transaction distribution
+system.membus.trans_dist::ReadExResp 825948 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 3583537 # Request fanout histogram
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal
new file mode 100644
index 000000000..a8a62831d
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal
@@ -0,0 +1,183 @@
+[ 0.000000] Initializing cgroup subsys cpu
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
+[ 0.000000] Memory limited to 256MB
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
+[ 0.000000] On node 0 totalpages: 65536
+[ 0.000000] DMA zone: 896 pages used for memmap
+[ 0.000000] DMA zone: 0 pages reserved
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
+[ 0.000000] Virtual kernel memory layout:
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[ 0.000000] Preemptible hierarchical RCU implementation.
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000013] Console: colour dummy device 80x25
+[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000015] pid_max: default: 32768 minimum: 301
+[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000066] hw perfevents: no hardware support available
+[ 1.060049] CPU1: failed to come online
+[ 2.080098] CPU2: failed to come online
+[ 3.100148] CPU3: failed to come online
+[ 3.100150] Brought up 1 CPUs
+[ 3.100151] SMP: Total of 1 processors activated.
+[ 3.100177] devtmpfs: initialized
+[ 3.100579] atomic64_test: passed
+[ 3.100603] regulator-dummy: no parameters
+[ 3.100844] NET: Registered protocol family 16
+[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.100981] Serial: AMBA PL011 UART driver
+[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.101160] console [ttyAMA0] enabled
+[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130356] 3V3: 3300 mV
+[ 3.130377] vgaarb: loaded
+[ 3.130406] SCSI subsystem initialized
+[ 3.130425] libata version 3.00 loaded.
+[ 3.130450] usbcore: registered new interface driver usbfs
+[ 3.130457] usbcore: registered new interface driver hub
+[ 3.130471] usbcore: registered new device driver usb
+[ 3.130482] pps_core: LinuxPPS API ver. 1 registered
+[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130487] PTP clock support registered
+[ 3.130559] Switched to clocksource arch_sys_counter
+[ 3.131204] NET: Registered protocol family 2
+[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131263] TCP: reno registered
+[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131281] NET: Registered protocol family 1
+[ 3.131310] RPC: Registered named UNIX socket transport module.
+[ 3.131311] RPC: Registered udp transport module.
+[ 3.131312] RPC: Registered tcp transport module.
+[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.131315] PCI: CLS 0 bytes, default 64
+[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.132687] fuse init (API version 7.23)
+[ 3.132738] msgmni has been set to 469
+[ 3.133992] io scheduler noop registered
+[ 3.134024] io scheduler cfq registered (default)
+[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.134302] pci_bus 0000:00: scanning bus
+[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134354] pci_bus 0000:00: fixups for bus
+[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
+[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
+[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
+[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
+[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
+[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.134813] ata_piix 0000:00:01.0: version 2.13
+[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.135009] scsi0 : ata_piix
+[ 3.135063] scsi1 : ata_piix
+[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.135150] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290572] ata1.00: configured for UDMA/33
+[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.290733] sda: sda1
+[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.410886] usbcore: registered new interface driver usb-storage
+[ 3.410912] mousedev: PS/2 mouse device common for all mice
+[ 3.411009] usbcore: registered new interface driver usbhid
+[ 3.411010] usbhid: USB HID core driver
+[ 3.411025] TCP: cubic registered
+[ 3.411026] NET: Registered protocol family 17
+
+[ 3.411214] devtmpfs: mounted
+[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+
+
+[ 3.446950] udevd[607]: starting version 182
+Starting Bootlog daemon: bootlogd.
+[ 3.532262] random: dd urandom read with 19 bits of entropy available
+Populating dev cache
+net.ipv4.conf.default.rp_filter = 1
+net.ipv4.conf.all.rp_filter = 1
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+Mon Jan 27 08:00:00 UTC 2014
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+ INIT: Entering runlevel: 5
+Configuring network interfaces... udhcpc (v1.21.1) started
+[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Sending discover...
+Sending discover...
+Sending discover...
+No lease, forking to background
+done.
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6
+rpcbind: cannot create socket for tcp6
+done.
+rpcbind: cannot get uid of '': Success
+creating NFS state directory: done
+starting statd: done
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
new file mode 100644
index 000000000..1dec8a2fa
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
@@ -0,0 +1,1608 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=timing
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=6
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=16
+cpu_side=system.cpu0.dcache_port
+mem_side=system.cpu0.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.dtb
+
+[system.cpu0.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.cpu0.toL2Bus.slave[0]
+
+[system.cpu0.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu0.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu0.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.itb
+
+[system.cpu0.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.istage2_mmu.stage2_tlb.walker
+
+[system.cpu0.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+cache_snoop=false
+clk_domain=system.cpu_clk_domain
+degree=8
+eventq_index=0
+latency=1
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
+sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.cpu0.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu1.dstage2_mmu
+dtb=system.cpu1.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+istage2_mmu=system.cpu1.istage2_mmu
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu1.tracer
+workload=
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=6
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.dcache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=16
+cpu_side=system.cpu1.dcache_port
+mem_side=system.cpu1.toL2Bus.slave[1]
+
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu1.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.dtb
+
+[system.cpu1.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[3]
+
+[system.cpu1.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.cpu1.toL2Bus.slave[0]
+
+[system.cpu1.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+cache_snoop=false
+clk_domain=system.cpu_clk_domain
+degree=8
+eventq_index=0
+latency=1
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
+sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=true
+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.l2c.cpu_side
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr
new file mode 100644
index 000000000..744db2c76
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr
@@ -0,0 +1,11 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
new file mode 100644
index 000000000..1e0022357
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
@@ -0,0 +1,17 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:01:57
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x5b5eb00 0x5b5eb00
+ 0: system.cpu1.isa: ISA system set to: 0x5b5eb00 0x5b5eb00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 47438274662000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
new file mode 100644
index 000000000..fb0fbc4a7
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -0,0 +1,3203 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 47.367818 # Number of seconds simulated
+sim_ticks 47367817574000 # Number of ticks simulated
+final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 678056 # Simulator instruction rate (inst/s)
+host_op_rate 798173 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38043399524 # Simulator tick rate (ticks/s)
+host_mem_usage 751768 # Number of bytes of host memory used
+host_seconds 1245.10 # Real time elapsed on the host
+sim_insts 844246943 # Number of instructions simulated
+sim_ops 993804803 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 9568064 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 72256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
+system.physmem.bytes_written::total 61313296 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 577 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 684685 # Number of read requests accepted
+system.physmem.writeReqs 1596629 # Number of write requests accepted
+system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue
+system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 42136 # Per bank write bursts
+system.physmem.perBankRdBursts::1 44080 # Per bank write bursts
+system.physmem.perBankRdBursts::2 34958 # Per bank write bursts
+system.physmem.perBankRdBursts::3 41288 # Per bank write bursts
+system.physmem.perBankRdBursts::4 39326 # Per bank write bursts
+system.physmem.perBankRdBursts::5 49165 # Per bank write bursts
+system.physmem.perBankRdBursts::6 40428 # Per bank write bursts
+system.physmem.perBankRdBursts::7 47118 # Per bank write bursts
+system.physmem.perBankRdBursts::8 36254 # Per bank write bursts
+system.physmem.perBankRdBursts::9 81044 # Per bank write bursts
+system.physmem.perBankRdBursts::10 36070 # Per bank write bursts
+system.physmem.perBankRdBursts::11 40557 # Per bank write bursts
+system.physmem.perBankRdBursts::12 34453 # Per bank write bursts
+system.physmem.perBankRdBursts::13 38158 # Per bank write bursts
+system.physmem.perBankRdBursts::14 37145 # Per bank write bursts
+system.physmem.perBankRdBursts::15 42231 # Per bank write bursts
+system.physmem.perBankWrBursts::0 97165 # Per bank write bursts
+system.physmem.perBankWrBursts::1 99476 # Per bank write bursts
+system.physmem.perBankWrBursts::2 95543 # Per bank write bursts
+system.physmem.perBankWrBursts::3 98326 # Per bank write bursts
+system.physmem.perBankWrBursts::4 92692 # Per bank write bursts
+system.physmem.perBankWrBursts::5 102230 # Per bank write bursts
+system.physmem.perBankWrBursts::6 96747 # Per bank write bursts
+system.physmem.perBankWrBursts::7 98806 # Per bank write bursts
+system.physmem.perBankWrBursts::8 93672 # Per bank write bursts
+system.physmem.perBankWrBursts::9 100275 # Per bank write bursts
+system.physmem.perBankWrBursts::10 92352 # Per bank write bursts
+system.physmem.perBankWrBursts::11 96579 # Per bank write bursts
+system.physmem.perBankWrBursts::12 94667 # Per bank write bursts
+system.physmem.perBankWrBursts::13 97213 # Per bank write bursts
+system.physmem.perBankWrBursts::14 92658 # Per bank write bursts
+system.physmem.perBankWrBursts::15 99164 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 352 # Number of times write queue was full causing retry
+system.physmem.totGap 47367814519500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 43195 # Read request sizes (log2)
+system.physmem.readPktSize::3 37 # Read request sizes (log2)
+system.physmem.readPktSize::4 5 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 641448 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 2 # Write request sizes (log2)
+system.physmem.writePktSize::3 2601 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 1594026 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 510577 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 50448 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 25290 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::58 541 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads
+system.physmem.totQLat 20326500723 # Total ticks spent queuing
+system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing
+system.physmem.readRowHits 509481 # Number of row buffer hits during reads
+system.physmem.writeRowHits 909439 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes
+system.physmem.avgGap 20763390.98 # Average gap between requests
+system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.635370 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.605711 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.walks 95467 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 81219280 # DTB read hits
+system.cpu0.dtb.read_misses 71070 # DTB read misses
+system.cpu0.dtb.write_hits 73504932 # DTB write hits
+system.cpu0.dtb.write_misses 24397 # DTB write misses
+system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 81290350 # DTB read accesses
+system.cpu0.dtb.write_accesses 73529329 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 154724212 # DTB hits
+system.cpu0.dtb.misses 95467 # DTB misses
+system.cpu0.dtb.accesses 154819679 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.walks 56383 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 434853798 # ITB inst hits
+system.cpu0.itb.inst_misses 56383 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses
+system.cpu0.itb.hits 434853798 # DTB hits
+system.cpu0.itb.misses 56383 # DTB misses
+system.cpu0.itb.accesses 434910181 # DTB accesses
+system.cpu0.numCycles 94735635148 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 434594659 # Number of instructions committed
+system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses
+system.cpu0.num_func_calls 25685063 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 468245604 # number of integer instructions
+system.cpu0.num_fp_insts 368958 # number of float instructions
+system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written
+system.cpu0.num_mem_refs 154715442 # number of memory refs
+system.cpu0.num_load_insts 81215665 # Number of load instructions
+system.cpu0.num_store_insts 73499777 # Number of store instructions
+system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles
+system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles
+system.cpu0.Branches 96525602 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction
+system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction
+system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction
+system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::total 510121531 # Class of executed instruction
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements 5284481 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits
+system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses
+system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027731 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks
+system.cpu0.dcache.writebacks::total 3634622 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28612 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 28612 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21357 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 21357 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 38145 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 38145 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.demand_mshr_hits::total 49969 # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency
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+system.cpu0.icache.tags.warmup_cycle 33435593250 # Cycle when the warmup percentage was hit.
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+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency
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+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu0.l2cache.prefetcher.pfIdentified 7625539 # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
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+system.cpu0.l2cache.prefetcher.pfSpanPage 975949 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements 2276475 # number of replacements
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+system.cpu0.l2cache.tags.sampled_refs 2292579 # Sample count of references to valid blocks.
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+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3718.900652 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3598.062438 # Average occupied blocks per requestor
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+system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id
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+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 592 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 515 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 17 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
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+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 811 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4617 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5283 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3880 # Occupied blocks per task id
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+system.cpu0.l2cache.ReadReq_hits::total 6955118 # number of ReadReq hits
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 65337441291 # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4307274002 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7775525002 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3933705500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3933705500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8240979502 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11709230502 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.248646 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.168188 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
+system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.766299 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.766299 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.553879 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.553879 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832725 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832725 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205169 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205169 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172480 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239706 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24493.654964 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23901.499212 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 36215.315810 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42441.441675 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42441.441675 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20873.741897 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.walks 92509 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 78277454 # DTB read hits
+system.cpu1.dtb.read_misses 68245 # DTB read misses
+system.cpu1.dtb.write_hits 71517077 # DTB write hits
+system.cpu1.dtb.write_misses 24264 # DTB write misses
+system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 78345699 # DTB read accesses
+system.cpu1.dtb.write_accesses 71541341 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 149794531 # DTB hits
+system.cpu1.dtb.misses 92509 # DTB misses
+system.cpu1.dtb.accesses 149887040 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.walks 60524 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 409921957 # ITB inst hits
+system.cpu1.itb.inst_misses 60524 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses
+system.cpu1.itb.hits 409921957 # DTB hits
+system.cpu1.itb.misses 60524 # DTB misses
+system.cpu1.itb.accesses 409982481 # DTB accesses
+system.cpu1.numCycles 94735635148 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 409652284 # Number of instructions committed
+system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses
+system.cpu1.num_func_calls 25682090 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 446181756 # number of integer instructions
+system.cpu1.num_fp_insts 565626 # number of float instructions
+system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written
+system.cpu1.num_mem_refs 149782083 # number of memory refs
+system.cpu1.num_load_insts 78271508 # Number of load instructions
+system.cpu1.num_store_insts 71510575 # Number of store instructions
+system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles
+system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles
+system.cpu1.Branches 91673037 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction
+system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction
+system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction
+system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction
+system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 484255317 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements 4752540 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits
+system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses
+system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 75812564 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 144853988 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 144853988 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 145536809 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027078 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks
+system.cpu1.dcache.writebacks::total 3063492 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits
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+system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits
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+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits
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+system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses
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+system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses
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+system.cpu1.dcache.SoftPFReq_mshr_misses::total 498783 # number of SoftPFReq MSHR misses
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+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 496292 # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 3910492 # number of demand (read+write) MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1936116751 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2164016499 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016721 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.730474 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.724271 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency
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+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
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+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency
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+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements 5523110 # number of replacements
+system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor
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+system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses
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+system.cpu1.icache.overall_hits::total 404398330 # number of overall hits
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+system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles
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+system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles
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+system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses
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+system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses
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+system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency
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+system.cpu1.icache.fast_writes 0 # number of fast writes performed
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+system.cpu1.icache.ReadReq_mshr_miss_latency::total 49075741422 # number of ReadReq MSHR miss cycles
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+system.cpu1.icache.demand_mshr_miss_latency::total 49075741422 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9805750 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9805750 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 9805750 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013475 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.013475 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.013475 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8884.695042 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.l2cache.prefetcher.num_hwpf_issued 5870481 # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified 5870524 # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
+system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
+system.cpu1.l2cache.prefetcher.pfSpanPage 773012 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements 1638473 # number of replacements
+system.cpu1.l2cache.tags.tagsinuse 13410.207774 # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs 10772955 # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs 1654198 # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs 6.512494 # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle 10040948806000 # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 5186.730932 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.626422 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.861590 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3789.090493 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3453.027216 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 821.871120 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks 0.316573 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004311 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005424 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.231268 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.210756 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050163 # Average percentage of cache occupancy
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+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2380480811 # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2176947075 # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2176947075 # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1480998 # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1480998 # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6436785468 # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6436785468 # number of ReadExReq MSHR miss cycles
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+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10375497328 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25150532637 # number of overall MSHR miss cycles
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+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8938250 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1841380999 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1850319249 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2067303001 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2067303001 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8938250 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3908684000 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3917622250 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.230439 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133350 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
+system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464080 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.464080 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.703753 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.703753 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.839473 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839473 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208148 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208148 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140548 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40336 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40336 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29895 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
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+system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution
+system.membus.trans_dist::ReadExReq 123220 # Transaction distribution
+system.membus.trans_dist::ReadExResp 104410 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 581158 # Total snoops (count)
+system.membus.snoop_fanout::samples 2928688 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 2928688 # Request fanout histogram
+system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1518303 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
new file mode 100644
index 000000000..2b30f017d
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
@@ -0,0 +1,184 @@
+[ 0.000000] Initializing cgroup subsys cpu
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
+[ 0.000000] Memory limited to 256MB
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
+[ 0.000000] On node 0 totalpages: 65536
+[ 0.000000] DMA zone: 896 pages used for memmap
+[ 0.000000] DMA zone: 0 pages reserved
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
+[ 0.000000] Virtual kernel memory layout:
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[ 0.000000] Preemptible hierarchical RCU implementation.
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000024] Console: colour dummy device 80x25
+[ 0.000026] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000028] pid_max: default: 32768 minimum: 301
+[ 0.000041] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000043] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000177] hw perfevents: no hardware support available
+[ 0.060047] CPU1: Booted secondary processor
+[ 1.080090] CPU2: failed to come online
+[ 2.100176] CPU3: failed to come online
+[ 2.100179] Brought up 2 CPUs
+[ 2.100180] SMP: Total of 2 processors activated.
+[ 2.100246] devtmpfs: initialized
+[ 2.101156] atomic64_test: passed
+[ 2.101216] regulator-dummy: no parameters
+[ 2.101757] NET: Registered protocol family 16
+[ 2.101938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101944] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.102749] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.102752] Serial: AMBA PL011 UART driver
+[ 2.102985] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.103030] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.103571] console [ttyAMA0] enabled
+[ 2.103651] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.103687] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.103724] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.103758] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.130471] 3V3: 3300 mV
+[ 2.130527] vgaarb: loaded
+[ 2.130588] SCSI subsystem initialized
+[ 2.130625] libata version 3.00 loaded.
+[ 2.130697] usbcore: registered new interface driver usbfs
+[ 2.130719] usbcore: registered new interface driver hub
+[ 2.130747] usbcore: registered new device driver usb
+[ 2.130780] pps_core: LinuxPPS API ver. 1 registered
+[ 2.130789] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.130808] PTP clock support registered
+[ 2.130983] Switched to clocksource arch_sys_counter
+[ 2.132484] NET: Registered protocol family 2
+[ 2.132575] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.132613] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.132639] TCP: reno registered
+[ 2.132646] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132659] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132700] NET: Registered protocol family 1
+[ 2.132760] RPC: Registered named UNIX socket transport module.
+[ 2.132769] RPC: Registered udp transport module.
+[ 2.132777] RPC: Registered tcp transport module.
+[ 2.132785] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.132797] PCI: CLS 0 bytes, default 64
+[ 2.133009] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.133115] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.136052] fuse init (API version 7.23)
+[ 2.136196] msgmni has been set to 469
+[ 2.136706] io scheduler noop registered
+[ 2.136791] io scheduler cfq registered (default)
+[ 2.137366] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.137378] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.137389] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.137401] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.137411] pci_bus 0000:00: scanning bus
+[ 2.137421] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.137433] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.137448] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.137496] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.137508] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.137518] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.137529] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.137540] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.137551] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.137562] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.137612] pci_bus 0000:00: fixups for bus
+[ 2.137620] pci_bus 0000:00: bus scan returning with max=00
+[ 2.137631] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.137651] pci 0000:00:00.0: fixup irq: got 33
+[ 2.137660] pci 0000:00:00.0: assigning IRQ 33
+[ 2.137670] pci 0000:00:01.0: fixup irq: got 34
+[ 2.137679] pci 0000:00:01.0: assigning IRQ 34
+[ 2.137690] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.137702] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.137715] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.137727] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.137739] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.137750] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.137761] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.137773] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.138657] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.139057] ata_piix 0000:00:01.0: version 2.13
+[ 2.139067] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.139093] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.139456] scsi0 : ata_piix
+[ 2.139567] scsi1 : ata_piix
+[ 2.139611] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.139623] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.139769] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.139781] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.139797] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.139808] e1000 0000:00:00.0: enabling bus mastering
+[ 2.291018] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.291027] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.291054] ata1.00: configured for UDMA/33
+[ 2.291104] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.291261] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.291294] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.291338] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.291347] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.291369] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.291545] sda: sda1
+[ 2.291741] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.411341] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.411354] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.411387] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.411399] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.411432] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.411446] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.411610] usbcore: registered new interface driver usb-storage
+[ 2.411699] mousedev: PS/2 mouse device common for all mice
+[ 2.412097] usbcore: registered new interface driver usbhid
+[ 2.412108] usbhid: USB HID core driver
+[ 2.412141] TCP: cubic registered
+[ 2.412149] NET: Registered protocol family 17
+
+[ 2.412601] devtmpfs: mounted
+[ 2.412656] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+
+
+[ 2.452574] udevd[608]: starting version 182
+Starting Bootlog daemon: bootlogd.
+[ 2.544108] random: dd urandom read with 18 bits of entropy available
+Populating dev cache
+net.ipv4.conf.default.rp_filter = 1
+net.ipv4.conf.all.rp_filter = 1
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+Mon Jan 27 08:00:00 UTC 2014
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+ INIT: Entering runlevel: 5
+Configuring network interfaces... udhcpc (v1.21.1) started
+[ 2.681213] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Sending discover...
+Sending discover...
+Sending discover...
+No lease, forking to background
+done.
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6
+rpcbind: cannot create socket for tcp6
+rpcbind: cannot get uid of '': Success
+done.
+creating NFS state directory: done
+starting statd: done
+Starting auto-serial-console: \ No newline at end of file
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
new file mode 100644
index 000000000..9587f8b73
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
@@ -0,0 +1,1229 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=timing
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=true
+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr
new file mode 100755
index 000000000..744db2c76
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr
@@ -0,0 +1,11 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
new file mode 100644
index 000000000..86944f7db
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
@@ -0,0 +1,16 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:01:52
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x500ab00 0x500ab00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 51781056074000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
new file mode 100644
index 000000000..d577712e0
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -0,0 +1,1550 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.824462 # Number of seconds simulated
+sim_ticks 51824462100500 # Number of ticks simulated
+final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 723017 # Simulator instruction rate (inst/s)
+host_op_rate 849578 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41937024652 # Simulator tick rate (ticks/s)
+host_mem_usage 712044 # Number of bytes of host memory used
+host_seconds 1235.77 # Real time elapsed on the host
+sim_insts 893481288 # Number of instructions simulated
+sim_ops 1049881338 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory
+system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
+system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 923811 # Number of read requests accepted
+system.physmem.writeReqs 1833124 # Number of write requests accepted
+system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue
+system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 57129 # Per bank write bursts
+system.physmem.perBankRdBursts::1 60965 # Per bank write bursts
+system.physmem.perBankRdBursts::2 52485 # Per bank write bursts
+system.physmem.perBankRdBursts::3 50413 # Per bank write bursts
+system.physmem.perBankRdBursts::4 54002 # Per bank write bursts
+system.physmem.perBankRdBursts::5 59718 # Per bank write bursts
+system.physmem.perBankRdBursts::6 51713 # Per bank write bursts
+system.physmem.perBankRdBursts::7 51669 # Per bank write bursts
+system.physmem.perBankRdBursts::8 50247 # Per bank write bursts
+system.physmem.perBankRdBursts::9 101235 # Per bank write bursts
+system.physmem.perBankRdBursts::10 59848 # Per bank write bursts
+system.physmem.perBankRdBursts::11 58323 # Per bank write bursts
+system.physmem.perBankRdBursts::12 55369 # Per bank write bursts
+system.physmem.perBankRdBursts::13 55988 # Per bank write bursts
+system.physmem.perBankRdBursts::14 51743 # Per bank write bursts
+system.physmem.perBankRdBursts::15 52477 # Per bank write bursts
+system.physmem.perBankWrBursts::0 110630 # Per bank write bursts
+system.physmem.perBankWrBursts::1 112240 # Per bank write bursts
+system.physmem.perBankWrBursts::2 108805 # Per bank write bursts
+system.physmem.perBankWrBursts::3 108103 # Per bank write bursts
+system.physmem.perBankWrBursts::4 111102 # Per bank write bursts
+system.physmem.perBankWrBursts::5 113339 # Per bank write bursts
+system.physmem.perBankWrBursts::6 105567 # Per bank write bursts
+system.physmem.perBankWrBursts::7 107723 # Per bank write bursts
+system.physmem.perBankWrBursts::8 108849 # Per bank write bursts
+system.physmem.perBankWrBursts::9 115780 # Per bank write bursts
+system.physmem.perBankWrBursts::10 115663 # Per bank write bursts
+system.physmem.perBankWrBursts::11 113049 # Per bank write bursts
+system.physmem.perBankWrBursts::12 112494 # Per bank write bursts
+system.physmem.perBankWrBursts::13 116984 # Per bank write bursts
+system.physmem.perBankWrBursts::14 111502 # Per bank write bursts
+system.physmem.perBankWrBursts::15 110389 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 145 # Number of times write queue was full causing retry
+system.physmem.totGap 51824459475500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 43101 # Read request sizes (log2)
+system.physmem.readPktSize::3 13 # Read request sizes (log2)
+system.physmem.readPktSize::4 2 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 880695 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 1 # Write request sizes (log2)
+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 1830551 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads
+system.physmem.totQLat 12043609520 # Total ticks spent queuing
+system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing
+system.physmem.readRowHits 694872 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes
+system.physmem.avgGap 18797853.22 # Average gap between requests
+system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.655841 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.672178 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 211321 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 167775531 # DTB read hits
+system.cpu.dtb.read_misses 155743 # DTB read misses
+system.cpu.dtb.write_hits 152648275 # DTB write hits
+system.cpu.dtb.write_misses 55578 # DTB write misses
+system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 167931274 # DTB read accesses
+system.cpu.dtb.write_accesses 152703853 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 320423806 # DTB hits
+system.cpu.dtb.misses 211321 # DTB misses
+system.cpu.dtb.accesses 320635127 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 122916 # Table walker walks requested
+system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 894030670 # ITB inst hits
+system.cpu.itb.inst_misses 122916 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 894153586 # ITB inst accesses
+system.cpu.itb.hits 894030670 # DTB hits
+system.cpu.itb.misses 122916 # DTB misses
+system.cpu.itb.accesses 894153586 # DTB accesses
+system.cpu.numCycles 103648924201 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 893481288 # Number of instructions committed
+system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses
+system.cpu.num_func_calls 52999943 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls
+system.cpu.num_int_insts 963989017 # number of integer instructions
+system.cpu.num_fp_insts 895873 # number of float instructions
+system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read
+system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written
+system.cpu.num_mem_refs 320407593 # number of memory refs
+system.cpu.num_load_insts 167768846 # Number of load instructions
+system.cpu.num_store_insts 152638747 # Number of store instructions
+system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles
+system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles
+system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.969376 # Percentage of idle cycles
+system.cpu.Branches 199584978 # Number of branches fetched
+system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction
+system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction
+system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction
+system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 1050473844 # Class of executed instruction
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements 10213653 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits
+system.cpu.dcache.overall_hits::total 301988446 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses
+system.cpu.dcache.overall_misses::total 8832117 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles
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+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5180093000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 470306 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40333 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40333 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29907 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 115493 # number of replacements
+system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039965 # Number of tag accesses
+system.iocache.tags.data_accesses 1039965 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8888 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8848 # number of overall misses
+system.iocache.overall_misses::total 8888 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks::writebacks 106630 # number of writebacks
+system.iocache.writebacks::total 106630 # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 448489 # Transaction distribution
+system.membus.trans_dist::ReadResp 448489 # Transaction distribution
+system.membus.trans_dist::WriteReq 33710 # Transaction distribution
+system.membus.trans_dist::WriteResp 33710 # Transaction distribution
+system.membus.trans_dist::Writeback 1214153 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution
+system.membus.trans_dist::ReadExReq 512353 # Transaction distribution
+system.membus.trans_dist::ReadExResp 512353 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 3324 # Total snoops (count)
+system.membus.snoop_fanout::samples 2750930 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 2750930 # Request fanout histogram
+system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
new file mode 100644
index 000000000..5957040e9
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
@@ -0,0 +1,183 @@
+[ 0.000000] Initializing cgroup subsys cpu
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
+[ 0.000000] Memory limited to 256MB
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
+[ 0.000000] On node 0 totalpages: 65536
+[ 0.000000] DMA zone: 896 pages used for memmap
+[ 0.000000] DMA zone: 0 pages reserved
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
+[ 0.000000] Virtual kernel memory layout:
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[ 0.000000] Preemptible hierarchical RCU implementation.
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
+[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000039] Console: colour dummy device 80x25
+[ 0.000042] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000045] pid_max: default: 32768 minimum: 301
+[ 0.000065] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000068] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000254] hw perfevents: no hardware support available
+[ 1.060134] CPU1: failed to come online
+[ 2.080264] CPU2: failed to come online
+[ 3.100395] CPU3: failed to come online
+[ 3.100400] Brought up 1 CPUs
+[ 3.100402] SMP: Total of 1 processors activated.
+[ 3.100500] devtmpfs: initialized
+[ 3.101762] atomic64_test: passed
+[ 3.101843] regulator-dummy: no parameters
+[ 3.102644] NET: Registered protocol family 16
+[ 3.102917] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.102927] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.103581] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.103585] Serial: AMBA PL011 UART driver
+[ 3.103931] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.103997] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.104547] console [ttyAMA0] enabled
+[ 3.104647] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.104695] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.104744] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.104789] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130966] 3V3: 3300 mV
+[ 3.131042] vgaarb: loaded
+[ 3.131134] SCSI subsystem initialized
+[ 3.131205] libata version 3.00 loaded.
+[ 3.131293] usbcore: registered new interface driver usbfs
+[ 3.131321] usbcore: registered new interface driver hub
+[ 3.131375] usbcore: registered new device driver usb
+[ 3.131420] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131429] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131451] PTP clock support registered
+[ 3.131688] Switched to clocksource arch_sys_counter
+[ 3.133862] NET: Registered protocol family 2
+[ 3.134013] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.134040] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.134072] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.134099] TCP: reno registered
+[ 3.134107] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134124] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134187] NET: Registered protocol family 1
+[ 3.134256] RPC: Registered named UNIX socket transport module.
+[ 3.134266] RPC: Registered udp transport module.
+[ 3.134274] RPC: Registered tcp transport module.
+[ 3.134283] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.134296] PCI: CLS 0 bytes, default 64
+[ 3.134626] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.134832] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.138917] fuse init (API version 7.23)
+[ 3.139097] msgmni has been set to 469
+[ 3.143447] io scheduler noop registered
+[ 3.143560] io scheduler cfq registered (default)
+[ 3.144375] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.144389] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.144401] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.144415] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.144425] pci_bus 0000:00: scanning bus
+[ 3.144438] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.144452] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.144469] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.144534] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.144547] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.144560] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.144572] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.144584] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.144596] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.144609] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.144672] pci_bus 0000:00: fixups for bus
+[ 3.144681] pci_bus 0000:00: bus scan returning with max=00
+[ 3.144694] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.144718] pci 0000:00:00.0: fixup irq: got 33
+[ 3.144728] pci 0000:00:00.0: assigning IRQ 33
+[ 3.144741] pci 0000:00:01.0: fixup irq: got 34
+[ 3.144750] pci 0000:00:01.0: assigning IRQ 34
+[ 3.144764] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.144778] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.144792] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.144806] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.144818] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.144831] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.144844] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.144856] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.145803] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.146345] ata_piix 0000:00:01.0: version 2.13
+[ 3.146356] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.146386] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.146981] scsi0 : ata_piix
+[ 3.147177] scsi1 : ata_piix
+[ 3.147237] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.147249] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.147450] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.147462] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.147484] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.147496] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301720] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301730] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301764] ata1.00: configured for UDMA/33
+[ 3.301835] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.302052] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.302087] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.302146] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.302156] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.302186] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.302399] sda: sda1
+[ 3.302620] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.422060] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.422074] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.422105] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.422115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.422148] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.422160] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.422304] usbcore: registered new interface driver usb-storage
+[ 3.422400] mousedev: PS/2 mouse device common for all mice
+[ 3.422718] usbcore: registered new interface driver usbhid
+[ 3.422728] usbhid: USB HID core driver
+[ 3.422776] TCP: cubic registered
+[ 3.422785] NET: Registered protocol family 17
+
+[ 3.423415] devtmpfs: mounted
+[ 3.423469] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+
+
+[ 3.470498] udevd[607]: starting version 182
+Starting Bootlog daemon: bootlogd.
+[ 3.596627] random: dd urandom read with 22 bits of entropy available
+Populating dev cache
+net.ipv4.conf.default.rp_filter = 1
+net.ipv4.conf.all.rp_filter = 1
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+Mon Jan 27 08:00:00 UTC 2014
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+ INIT: Entering runlevel: 5
+Configuring network interfaces... udhcpc (v1.21.1) started
+[ 3.801922] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Sending discover...
+Sending discover...
+Sending discover...
+No lease, forking to background
+done.
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6
+rpcbind: cannot create socket for tcp6
+done.
+rpcbind: cannot get uid of '': Success
+creating NFS state directory: done
+starting statd: done
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
new file mode 100644
index 000000000..7b6dda94d
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
@@ -0,0 +1,1320 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=atomic
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.dtb
+
+[system.cpu0.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu0.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu0.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.itb
+
+[system.cpu0.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.istage2_mmu.stage2_tlb.walker
+
+[system.cpu0.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dstage2_mmu dtb isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu1.dstage2_mmu
+dtb=system.cpu1.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=Null
+isa=system.cpu1.isa
+istage2_mmu=system.cpu1.istage2_mmu
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+width=1
+workload=
+
+[system.cpu1.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.dtb
+
+[system.cpu1.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=true
+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2415919103
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr
new file mode 100644
index 000000000..3137dc2c1
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr
@@ -0,0 +1,570 @@
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
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+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
new file mode 100644
index 000000000..3cdd0b0b9
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:13:02
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu0.isa: ISA system set to: 0x5318b00 0x5318b00
+ 0: system.cpu1.isa: ISA system set to: 0x5318b00 0x5318b00
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
new file mode 100644
index 000000000..f36b7859c
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -0,0 +1,1111 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.111153 # Number of seconds simulated
+sim_ticks 51111152682000 # Number of ticks simulated
+final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1095499 # Simulator instruction rate (inst/s)
+host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56869697369 # Simulator tick rate (ticks/s)
+host_mem_usage 728040 # Number of bytes of host memory used
+host_seconds 898.74 # Real time elapsed on the host
+sim_insts 984570519 # Number of instructions simulated
+sim_ops 1157031967 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3328564 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 37865864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 188288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2234176 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 36967936 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81626364 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3328564 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2234176 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 103043072 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
+system.physmem.bytes_written::total 103063652 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 92416 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 591667 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2942 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 34909 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 577624 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1315832 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1610048 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1612621 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 65124 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 740853 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 3684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 43712 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 723285 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1597036 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 65124 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 43712 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2016058 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2016461 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2016058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 65124 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 741256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 3684 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 43712 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 723285 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3613497 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.walks 144734 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 144734 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 144734 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 144734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 144734 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 107995 85.62% 85.62% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 18140 14.38% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 126135 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144734 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144734 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126135 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126135 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 270869 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 91873100 # DTB read hits
+system.cpu0.dtb.read_misses 107254 # DTB read misses
+system.cpu0.dtb.write_hits 84300346 # DTB write hits
+system.cpu0.dtb.write_misses 37480 # DTB write misses
+system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 56998 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 5021 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 11101 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 91980354 # DTB read accesses
+system.cpu0.dtb.write_accesses 84337826 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 176173446 # DTB hits
+system.cpu0.dtb.misses 144734 # DTB misses
+system.cpu0.dtb.accesses 176318180 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.walks 70623 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 70623 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 70623 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 70623 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 70623 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 62003 96.05% 96.05% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 2552 3.95% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 64555 # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70623 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70623 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64555 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64555 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 135178 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 493558289 # ITB inst hits
+system.cpu0.itb.inst_misses 70623 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 40618 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 493628912 # ITB inst accesses
+system.cpu0.itb.hits 493558289 # DTB hits
+system.cpu0.itb.misses 70623 # DTB misses
+system.cpu0.itb.accesses 493628912 # DTB accesses
+system.cpu0.numCycles 98036732821 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 493343054 # Number of instructions committed
+system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 453665 # Number of float alu accesses
+system.cpu0.num_func_calls 28504103 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 76145406 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 530703417 # number of integer instructions
+system.cpu0.num_fp_insts 453665 # number of float instructions
+system.cpu0.num_int_register_reads 784985742 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 421507499 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 741739 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 362084 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 133043946 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 132723498 # number of times the CC registers were written
+system.cpu0.num_mem_refs 176296730 # number of memory refs
+system.cpu0.num_load_insts 91967123 # Number of load instructions
+system.cpu0.num_store_insts 84329607 # Number of store instructions
+system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles
+system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles
+system.cpu0.Branches 110281342 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 402074699 69.37% 69.37% # Class of executed instruction
+system.cpu0.op_class::IntMult 1168928 0.20% 69.57% # Class of executed instruction
+system.cpu0.op_class::IntDiv 50558 0.01% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatMisc 52783 0.01% 69.59% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction
+system.cpu0.op_class::MemRead 91967123 15.87% 85.45% # Class of executed instruction
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+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
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+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.walks 143589 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 143589 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples 143589 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 143589 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 143589 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 106707 85.51% 85.51% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 18085 14.49% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 124792 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143589 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143589 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124792 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124792 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 268381 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 92120843 # DTB read hits
+system.cpu1.dtb.read_misses 106565 # DTB read misses
+system.cpu1.dtb.write_hits 83929435 # DTB write hits
+system.cpu1.dtb.write_misses 37024 # DTB write misses
+system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 56458 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 4753 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 10550 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 92227408 # DTB read accesses
+system.cpu1.dtb.write_accesses 83966459 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 176050278 # DTB hits
+system.cpu1.dtb.misses 143589 # DTB misses
+system.cpu1.dtb.accesses 176193867 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.walks 69863 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 69863 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walkWaitTime::samples 69863 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 69863 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 69863 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 61226 95.98% 95.98% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 2567 4.02% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 63793 # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69863 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69863 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63793 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63793 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 133656 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 491475383 # ITB inst hits
+system.cpu1.itb.inst_misses 69863 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 40934 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 491545246 # ITB inst accesses
+system.cpu1.itb.hits 491475383 # DTB hits
+system.cpu1.itb.misses 69863 # DTB misses
+system.cpu1.itb.accesses 491545246 # DTB accesses
+system.cpu1.numCycles 97463064529 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 491227465 # Number of instructions committed
+system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 427140 # Number of float alu accesses
+system.cpu1.num_func_calls 28552264 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 75795428 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 529752049 # number of integer instructions
+system.cpu1.num_fp_insts 427140 # number of float instructions
+system.cpu1.num_int_register_reads 779016428 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 420937292 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 677260 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 385836 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 131363112 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 131105905 # number of times the CC registers were written
+system.cpu1.num_mem_refs 176168876 # number of memory refs
+system.cpu1.num_load_insts 92213308 # Number of load instructions
+system.cpu1.num_store_insts 83955568 # Number of store instructions
+system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles
+system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles
+system.cpu1.Branches 109807220 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 400561917 69.30% 69.30% # Class of executed instruction
+system.cpu1.op_class::IntMult 1185819 0.21% 69.50% # Class of executed instruction
+system.cpu1.op_class::IntDiv 51201 0.01% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 55039 0.01% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::MemRead 92213308 15.95% 85.48% # Class of executed instruction
+system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 578022895 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29851 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements 115463 # number of replacements
+system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
+system.iocache.tags.data_accesses 1039686 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8817 # number of overall misses
+system.iocache.overall_misses::total 8857 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks::writebacks 106631 # number of writebacks
+system.iocache.writebacks::total 106631 # number of writebacks
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.tags.replacements 1722682 # number of replacements
+system.l2c.tags.tagsinuse 65341.862498 # Cycle average of tags in use
+system.l2c.tags.total_refs 30065488 # Total number of references to valid blocks.
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+system.membus.snoop_fanout::mean 1 # Request fanout histogram
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+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
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+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
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+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
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+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
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+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
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+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 23464706 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28678566 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32383249 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 63549157 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 116338 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal
new file mode 100644
index 000000000..a8a62831d
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal
@@ -0,0 +1,183 @@
+[ 0.000000] Initializing cgroup subsys cpu
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
+[ 0.000000] Memory limited to 256MB
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
+[ 0.000000] On node 0 totalpages: 65536
+[ 0.000000] DMA zone: 896 pages used for memmap
+[ 0.000000] DMA zone: 0 pages reserved
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
+[ 0.000000] Virtual kernel memory layout:
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[ 0.000000] Preemptible hierarchical RCU implementation.
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000013] Console: colour dummy device 80x25
+[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000015] pid_max: default: 32768 minimum: 301
+[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000066] hw perfevents: no hardware support available
+[ 1.060049] CPU1: failed to come online
+[ 2.080098] CPU2: failed to come online
+[ 3.100148] CPU3: failed to come online
+[ 3.100150] Brought up 1 CPUs
+[ 3.100151] SMP: Total of 1 processors activated.
+[ 3.100177] devtmpfs: initialized
+[ 3.100579] atomic64_test: passed
+[ 3.100603] regulator-dummy: no parameters
+[ 3.100844] NET: Registered protocol family 16
+[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.100981] Serial: AMBA PL011 UART driver
+[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.101160] console [ttyAMA0] enabled
+[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130356] 3V3: 3300 mV
+[ 3.130377] vgaarb: loaded
+[ 3.130406] SCSI subsystem initialized
+[ 3.130425] libata version 3.00 loaded.
+[ 3.130450] usbcore: registered new interface driver usbfs
+[ 3.130457] usbcore: registered new interface driver hub
+[ 3.130471] usbcore: registered new device driver usb
+[ 3.130482] pps_core: LinuxPPS API ver. 1 registered
+[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130487] PTP clock support registered
+[ 3.130559] Switched to clocksource arch_sys_counter
+[ 3.131204] NET: Registered protocol family 2
+[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131263] TCP: reno registered
+[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131281] NET: Registered protocol family 1
+[ 3.131310] RPC: Registered named UNIX socket transport module.
+[ 3.131311] RPC: Registered udp transport module.
+[ 3.131312] RPC: Registered tcp transport module.
+[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.131315] PCI: CLS 0 bytes, default 64
+[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.132687] fuse init (API version 7.23)
+[ 3.132738] msgmni has been set to 469
+[ 3.133992] io scheduler noop registered
+[ 3.134024] io scheduler cfq registered (default)
+[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.134302] pci_bus 0000:00: scanning bus
+[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134354] pci_bus 0000:00: fixups for bus
+[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
+[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
+[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
+[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
+[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
+[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.134813] ata_piix 0000:00:01.0: version 2.13
+[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.135009] scsi0 : ata_piix
+[ 3.135063] scsi1 : ata_piix
+[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.135150] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290572] ata1.00: configured for UDMA/33
+[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.290733] sda: sda1
+[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.410886] usbcore: registered new interface driver usb-storage
+[ 3.410912] mousedev: PS/2 mouse device common for all mice
+[ 3.411009] usbcore: registered new interface driver usbhid
+[ 3.411010] usbhid: USB HID core driver
+[ 3.411025] TCP: cubic registered
+[ 3.411026] NET: Registered protocol family 17
+
+[ 3.411214] devtmpfs: mounted
+[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+
+
+[ 3.446950] udevd[607]: starting version 182
+Starting Bootlog daemon: bootlogd.
+[ 3.532262] random: dd urandom read with 19 bits of entropy available
+Populating dev cache
+net.ipv4.conf.default.rp_filter = 1
+net.ipv4.conf.all.rp_filter = 1
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+Mon Jan 27 08:00:00 UTC 2014
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+ INIT: Entering runlevel: 5
+Configuring network interfaces... udhcpc (v1.21.1) started
+[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Sending discover...
+Sending discover...
+Sending discover...
+No lease, forking to background
+done.
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6
+rpcbind: cannot create socket for tcp6
+done.
+rpcbind: cannot get uid of '': Success
+creating NFS state directory: done
+starting statd: done