diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot')
4 files changed, 3301 insertions, 3321 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 14c60d4c9..05077073e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,244 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.867374 # Number of seconds simulated -sim_ticks 1867373908500 # Number of ticks simulated -final_tick 1867373908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.855236 # Number of seconds simulated +sim_ticks 1855236450500 # Number of ticks simulated +final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123272 # Simulator instruction rate (inst/s) -host_op_rate 123272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4349339718 # Simulator tick rate (ticks/s) -host_mem_usage 299108 # Number of bytes of host memory used -host_seconds 429.35 # Real time elapsed on the host -sim_insts 52926469 # Number of instructions simulated -sim_ops 52926469 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory +host_inst_rate 87142 # Simulator instruction rate (inst/s) +host_op_rate 87142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3050446700 # Simulator tick rate (ticks/s) +host_mem_usage 299400 # Number of bytes of host memory used +host_seconds 608.19 # Real time elapsed on the host +sim_insts 52998368 # Number of instructions simulated +sim_ops 52998368 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28501568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7518720 # Number of bytes written to this memory -system.physmem.bytes_written::total 7518720 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory +system.physmem.bytes_written::total 7522688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445337 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117480 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117480 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13323249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1420330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15262914 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4026360 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4026360 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4026360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13323249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1420330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19289275 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 338398 # number of replacements -system.cpu.l2cache.tagsinuse 65348.140689 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2559915 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403567 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.343222 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4870006000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 53844.889123 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 5363.726417 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6139.525149 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.821608 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.081844 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.093682 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997133 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 1007783 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1835554 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 841020 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 841020 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185546 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185546 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1007783 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1013317 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2021100 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1007783 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1013317 # number of overall hits -system.cpu.l2cache.overall_hits::total 2021100 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15155 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273854 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 289009 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 54 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 54 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115395 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15155 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389249 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404404 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15155 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389249 # number of overall misses -system.cpu.l2cache.overall_misses::total 404404 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 807128998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14259763500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15066892498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 376500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 376500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6225363497 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6225363497 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 807128998 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20485126997 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21292255995 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 807128998 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20485126997 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21292255995 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1022938 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1101625 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2124563 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 841020 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 841020 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 300941 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 300941 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1022938 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1402566 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2425504 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1022938 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1402566 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2425504 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248591 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136032 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.635294 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.635294 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383447 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383447 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014815 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277526 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166730 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014815 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277526 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166730 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.264467 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52070.678172 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52132.952600 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6972.222222 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6972.222222 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53948.294961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53948.294961 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52650.952995 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52650.952995 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75968 # number of writebacks -system.cpu.l2cache.writebacks::total 75968 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15154 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273854 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 289008 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 54 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 54 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15154 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389249 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404403 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15154 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389249 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404403 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 621904998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10983272500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11605177498 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2245000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2245000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4831334497 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4831334497 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 621904998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15814606997 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16436511995 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 621904998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15814606997 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16436511995 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333882500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884635500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218518000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218518000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248591 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136032 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.635294 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.635294 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383447 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383447 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.166729 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.166729 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40155.211960 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41574.074074 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41867.797539 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.num_reads::total 445360 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117542 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.309507 # Cycle average of tags in use +system.iocache.tagsinuse 1.255779 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1711308479000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.309507 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.081844 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.081844 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -249,12 +57,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11464497806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11464497806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11485170804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11485170804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11485170804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11485170804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -273,17 +81,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275907.244080 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275907.244080 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 275258.737064 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 275258.737064 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199587000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24660 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8093.552311 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -299,12 +107,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9303643992 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9303643992 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9315319992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9315319992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9315319992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9315319992 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -315,12 +123,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223903.638621 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223903.638621 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -338,22 +146,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9950205 # DTB read hits -system.cpu.dtb.read_misses 43861 # DTB read misses -system.cpu.dtb.read_acv 493 # DTB read access violations -system.cpu.dtb.read_accesses 957335 # DTB read accesses -system.cpu.dtb.write_hits 6626699 # DTB write hits -system.cpu.dtb.write_misses 9966 # DTB write misses -system.cpu.dtb.write_acv 395 # DTB write access violations -system.cpu.dtb.write_accesses 340478 # DTB write accesses -system.cpu.dtb.data_hits 16576904 # DTB hits -system.cpu.dtb.data_misses 53827 # DTB misses -system.cpu.dtb.data_acv 888 # DTB access violations -system.cpu.dtb.data_accesses 1297813 # DTB accesses -system.cpu.itb.fetch_hits 1339762 # ITB hits -system.cpu.itb.fetch_misses 37185 # ITB misses -system.cpu.itb.fetch_acv 1122 # ITB acv -system.cpu.itb.fetch_accesses 1376947 # ITB accesses +system.cpu.dtb.read_hits 9942716 # DTB read hits +system.cpu.dtb.read_misses 44791 # DTB read misses +system.cpu.dtb.read_acv 565 # DTB read access violations +system.cpu.dtb.read_accesses 947396 # DTB read accesses +system.cpu.dtb.write_hits 6623666 # DTB write hits +system.cpu.dtb.write_misses 10259 # DTB write misses +system.cpu.dtb.write_acv 393 # DTB write access violations +system.cpu.dtb.write_accesses 338396 # DTB write accesses +system.cpu.dtb.data_hits 16566382 # DTB hits +system.cpu.dtb.data_misses 55050 # DTB misses +system.cpu.dtb.data_acv 958 # DTB access violations +system.cpu.dtb.data_accesses 1285792 # DTB accesses +system.cpu.itb.fetch_hits 1328947 # ITB hits +system.cpu.itb.fetch_misses 38142 # ITB misses +system.cpu.itb.fetch_acv 1080 # ITB acv +system.cpu.itb.fetch_accesses 1367089 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -366,277 +174,277 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 124800831 # number of cpu cycles simulated +system.cpu.numCycles 112948398 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14048431 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11726244 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 450741 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10120037 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5916610 # Number of BTB hits +system.cpu.BPredUnit.lookups 13966796 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 938783 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45408 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31451408 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71430724 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14048431 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6855393 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13459712 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2155244 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43163669 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 276321 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 306226 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 194 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8835796 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303984 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 90109445 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.792711 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.123252 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76649733 85.06% 85.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 882120 0.98% 86.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1758761 1.95% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 855148 0.95% 88.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2774809 3.08% 92.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 597111 0.66% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671452 0.75% 93.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1010353 1.12% 94.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4909958 5.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 90109445 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.112567 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.572358 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32486072 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 42966960 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12232972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1046401 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1377039 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 612715 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43176 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70146735 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 131924 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1377039 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33631618 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17301504 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21458473 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11517889 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4822920 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66414787 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7289 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 750703 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1791896 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44375645 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80516952 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80027527 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 489425 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38131021 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6244616 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1698641 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251106 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12735763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10548926 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6961519 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1298320 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 905557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58829539 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2094293 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57137234 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 128634 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7593303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3942261 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1428853 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 90109445 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.634087 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.284474 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12232048 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11473805 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64286768 71.34% 71.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11995743 13.31% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5355125 5.94% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3438365 3.82% 94.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2611846 2.90% 97.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1326020 1.47% 98.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 685055 0.76% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 355852 0.39% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 54671 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 90109445 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 75508 9.96% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 363265 47.93% 57.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 319103 42.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38991069 68.24% 68.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61859 0.11% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25608 0.04% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10392240 18.19% 86.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6705676 11.74% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949855 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57137234 # Type of FU issued -system.cpu.iq.rate 0.457827 # Inst issue rate -system.cpu.iq.fu_busy_cnt 757876 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013264 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 204573341 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68190814 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55847999 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 697081 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 339930 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327759 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57523312 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 364507 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597966 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57074473 # Type of FU issued +system.cpu.iq.rate 0.505315 # Inst issue rate +system.cpu.iq.fu_busy_cnt 789329 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1464590 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2710 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13959 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 585881 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18028 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 111488 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1377039 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12355921 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 868580 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64490760 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 689025 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10548926 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6961519 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1842879 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 620807 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12564 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13959 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 241262 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 422502 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 663764 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56606739 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10022317 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 530494 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3566928 # number of nop insts executed -system.cpu.iew.exec_refs 16674247 # number of memory reference insts executed -system.cpu.iew.exec_branches 8979744 # Number of branches executed -system.cpu.iew.exec_stores 6651930 # Number of stores executed -system.cpu.iew.exec_rate 0.453577 # Inst execution rate -system.cpu.iew.wb_sent 56287349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56175758 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27690548 # num instructions producing a value -system.cpu.iew.wb_consumers 37534692 # num instructions consuming a value +system.cpu.iew.exec_nop 3555305 # number of nop insts executed +system.cpu.iew.exec_refs 16665522 # number of memory reference insts executed +system.cpu.iew.exec_branches 8969939 # Number of branches executed +system.cpu.iew.exec_stores 6649129 # Number of stores executed +system.cpu.iew.exec_rate 0.500679 # Inst execution rate +system.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56121532 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27804186 # num instructions producing a value +system.cpu.iew.wb_consumers 37617732 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.450123 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737732 # average fanout of values written-back +system.cpu.iew.wb_rate 0.496878 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8267625 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 665440 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 619184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 88732406 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.632394 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.547937 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67542246 76.12% 76.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8923750 10.06% 86.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4811841 5.42% 91.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2594320 2.92% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1447946 1.63% 96.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 597901 0.67% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 519027 0.58% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 475014 0.54% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1820361 2.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 88732406 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56113829 # Number of instructions committed -system.cpu.commit.committedOps 56113829 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56188905 # Number of instructions committed +system.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15459974 # Number of memory references committed -system.cpu.commit.loads 9084336 # Number of loads committed -system.cpu.commit.membars 226495 # Number of memory barriers committed -system.cpu.commit.branches 8440914 # Number of branches committed +system.cpu.commit.refs 15476867 # Number of memory references committed +system.cpu.commit.loads 9095415 # Number of loads committed +system.cpu.commit.membars 226300 # Number of memory barriers committed +system.cpu.commit.branches 8447820 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51962143 # Number of committed integer instructions. -system.cpu.commit.function_calls 739769 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1820361 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52034961 # Number of committed integer instructions. +system.cpu.commit.function_calls 740468 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 151043798 # The number of ROB reads -system.cpu.rob.rob_writes 130140767 # The number of ROB writes -system.cpu.timesIdled 1385278 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34691386 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3609940555 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52926469 # Number of Instructions Simulated -system.cpu.committedOps 52926469 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52926469 # Number of Instructions Simulated -system.cpu.cpi 2.358004 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.358004 # CPI: Total CPI of All Threads -system.cpu.ipc 0.424087 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.424087 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74197467 # number of integer regfile reads -system.cpu.int_regfile_writes 40518410 # number of integer regfile writes -system.cpu.fp_regfile_reads 166390 # number of floating regfile reads -system.cpu.fp_regfile_writes 166940 # number of floating regfile writes -system.cpu.misc_regfile_reads 1995246 # number of misc regfile reads -system.cpu.misc_regfile_writes 947641 # number of misc regfile writes +system.cpu.rob.rob_reads 141682968 # The number of ROB reads +system.cpu.rob.rob_writes 129465441 # The number of ROB writes +system.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52998368 # Number of Instructions Simulated +system.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52998368 # Number of Instructions Simulated +system.cpu.cpi 2.131167 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads +system.cpu.ipc 0.469226 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74144483 # number of integer regfile reads +system.cpu.int_regfile_writes 40484328 # number of integer regfile writes +system.cpu.fp_regfile_reads 165992 # number of floating regfile reads +system.cpu.fp_regfile_writes 167427 # number of floating regfile writes +system.cpu.misc_regfile_reads 1993361 # number of misc regfile reads +system.cpu.misc_regfile_writes 946826 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -668,245 +476,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1022327 # number of replacements -system.cpu.icache.tagsinuse 509.956829 # Cycle average of tags in use -system.cpu.icache.total_refs 7752117 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1022838 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.579027 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23896694000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.956829 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996009 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996009 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7752118 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7752118 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7752118 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7752118 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7752118 # number of overall hits -system.cpu.icache.overall_hits::total 7752118 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1083676 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1083676 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1083676 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1083676 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1083676 # number of overall misses -system.cpu.icache.overall_misses::total 1083676 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17473525489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17473525489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17473525489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17473525489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17473525489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17473525489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8835794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8835794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8835794 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8835794 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8835794 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8835794 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122646 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122646 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122646 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122646 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122646 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16124.307901 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16124.307901 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16124.307901 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16124.307901 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1701496 # number of cycles access was blocked +system.cpu.icache.replacements 1020348 # number of replacements +system.cpu.icache.tagsinuse 510.019758 # Cycle average of tags in use +system.cpu.icache.total_refs 7661720 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1020856 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.505192 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 22969954000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.019758 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996132 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996132 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7661721 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7661721 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7661721 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7661721 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7661721 # number of overall hits +system.cpu.icache.overall_hits::total 7661721 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1079749 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079749 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1079749 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1079749 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1079749 # number of overall misses +system.cpu.icache.overall_misses::total 1079749 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14523691994 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14523691994 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14523691994 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14523691994 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14523691994 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14523691994 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8741470 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8741470 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8741470 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8741470 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8741470 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8741470 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123520 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123520 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123520 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123520 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9098.909091 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60589 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60589 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60589 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60589 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60589 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60589 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1023087 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1023087 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1023087 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1023087 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1023087 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1023087 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13469506496 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13469506496 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13469506496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13469506496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13469506496 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13469506496 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115789 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115789 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115789 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115789 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115789 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115789 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13165.553365 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13165.553365 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13165.553365 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13165.553365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13165.553365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13165.553365 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58677 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 58677 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 58677 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 58677 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 58677 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # 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Average occupied blocks per requestor +system.cpu.dcache.replacements 1402622 # number of replacements +system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use +system.cpu.dcache.total_refs 11889704 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403134 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.473677 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 23228000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994917 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7252868 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7252868 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4173229 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4173229 # 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number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219522 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11479559 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11479559 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11479559 # number of overall hits +system.cpu.dcache.overall_hits::total 11479559 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1797475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1797475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1942414 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1942414 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23040 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23040 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3739889 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3739889 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3739889 # number of overall misses +system.cpu.dcache.overall_misses::total 3739889 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # 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miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107948 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 110012 # 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number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 76030 # number of writebacks +system.cpu.l2cache.writebacks::total 76030 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15150 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273885 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 289035 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115380 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115380 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15150 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389265 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404415 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.559322 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.559322 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383536 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383536 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6432 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211195 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74695 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 137 0.08% 41.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1890 1.04% 42.06% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105693 57.94% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182415 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73328 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 137 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1890 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73331 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148686 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1826702082500 97.82% 97.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 72077500 0.00% 97.83% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 572984500 0.03% 97.86% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 40025844000 2.14% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1867372988500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981699 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693811 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815097 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -972,32 +960,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.18% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175272 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6795 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5118 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed +system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192141 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2108 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 191902 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080645 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393483 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29935560000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2782423500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1834654997000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 3cd1cf5f9..a59fc99d0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.537930 # Number of seconds simulated -sim_ticks 2537929870500 # Number of ticks simulated -final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534231 # Number of seconds simulated +sim_ticks 2534231333000 # Number of ticks simulated +final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52642 # Simulator instruction rate (inst/s) -host_op_rate 67714 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2204296601 # Simulator tick rate (ticks/s) -host_mem_usage 387316 # Number of bytes of host memory used -host_seconds 1151.36 # Real time elapsed on the host -sim_insts 60609996 # Number of instructions simulated -sim_ops 77962726 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory +host_inst_rate 44913 # Simulator instruction rate (inst/s) +host_op_rate 57771 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1878262368 # Simulator tick rate (ticks/s) +host_mem_usage 387000 # Number of bytes of host memory used +host_seconds 1349.24 # Real time elapsed on the host +sim_insts 60598653 # Number of instructions simulated +sim_ops 77947265 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory +system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784256 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,273 +61,6 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 64349 # number of replacements -system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12176 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -336,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15052897 # DTB read hits -system.cpu.checker.dtb.read_misses 7321 # DTB read misses -system.cpu.checker.dtb.write_hits 11296410 # DTB write hits -system.cpu.checker.dtb.write_misses 2195 # DTB write misses +system.cpu.checker.dtb.read_hits 15049411 # DTB read hits +system.cpu.checker.dtb.read_misses 7302 # DTB read misses +system.cpu.checker.dtb.write_hits 11294478 # DTB write hits +system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15060218 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11298605 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056713 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296667 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26349307 # DTB hits -system.cpu.checker.dtb.misses 9516 # DTB misses -system.cpu.checker.dtb.accesses 26358823 # DTB accesses -system.cpu.checker.itb.inst_hits 61788771 # ITB inst hits +system.cpu.checker.dtb.hits 26343889 # DTB hits +system.cpu.checker.dtb.misses 9491 # DTB misses +system.cpu.checker.dtb.accesses 26353380 # DTB accesses +system.cpu.checker.itb.inst_hits 61777417 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -372,36 +105,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61793242 # ITB inst accesses -system.cpu.checker.itb.hits 61788771 # DTB hits +system.cpu.checker.itb.inst_accesses 61781888 # ITB inst accesses +system.cpu.checker.itb.hits 61777417 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61793242 # DTB accesses -system.cpu.checker.numCycles 78253308 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61781888 # DTB accesses +system.cpu.checker.numCycles 78237836 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51757171 # DTB read hits -system.cpu.dtb.read_misses 78755 # DTB read misses -system.cpu.dtb.write_hits 11824944 # DTB write hits -system.cpu.dtb.write_misses 17612 # DTB write misses +system.cpu.dtb.read_hits 51729232 # DTB read hits +system.cpu.dtb.read_misses 76957 # DTB read misses +system.cpu.dtb.write_hits 11808980 # DTB write hits +system.cpu.dtb.write_misses 17307 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7813 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7736 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51835926 # DTB read accesses -system.cpu.dtb.write_accesses 11842556 # DTB write accesses +system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51806189 # DTB read accesses +system.cpu.dtb.write_accesses 11826287 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63582115 # DTB hits -system.cpu.dtb.misses 96367 # DTB misses -system.cpu.dtb.accesses 63678482 # DTB accesses -system.cpu.itb.inst_hits 13115769 # ITB inst hits -system.cpu.itb.inst_misses 12252 # ITB inst misses +system.cpu.dtb.hits 63538212 # DTB hits +system.cpu.dtb.misses 94264 # DTB misses +system.cpu.dtb.accesses 63632476 # DTB accesses +system.cpu.itb.inst_hits 13079160 # ITB inst hits +system.cpu.itb.inst_misses 12175 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -410,538 +143,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5204 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5196 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13128021 # ITB inst accesses -system.cpu.itb.hits 13115769 # DTB hits -system.cpu.itb.misses 12252 # DTB misses -system.cpu.itb.accesses 13128021 # DTB accesses -system.cpu.numCycles 487049956 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13091335 # ITB inst accesses +system.cpu.itb.hits 13079160 # DTB hits +system.cpu.itb.misses 12175 # DTB misses +system.cpu.itb.accesses 13091335 # DTB accesses +system.cpu.numCycles 475963827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits +system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued -system.cpu.iq.rate 0.259310 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued +system.cpu.iq.rate 0.265193 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 226495 # number of nop insts executed -system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed -system.cpu.iew.exec_branches 11753944 # Number of branches executed -system.cpu.iew.exec_stores 12337385 # Number of stores executed -system.cpu.iew.exec_rate 0.252721 # Inst execution rate -system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47490892 # num instructions producing a value -system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value +system.cpu.iew.exec_nop 225525 # number of nop insts executed +system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed +system.cpu.iew.exec_branches 11734992 # Number of branches executed +system.cpu.iew.exec_stores 12321310 # Number of stores executed +system.cpu.iew.exec_rate 0.258373 # Inst execution rate +system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47712496 # num instructions producing a value +system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60760377 # Number of instructions committed -system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749034 # Number of instructions committed +system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27521116 # Number of memory references committed -system.cpu.commit.loads 15720306 # Number of loads committed -system.cpu.commit.membars 413361 # Number of memory barriers committed -system.cpu.commit.branches 10025135 # Number of branches committed +system.cpu.commit.refs 27515291 # Number of memory references committed +system.cpu.commit.loads 15716471 # Number of loads committed +system.cpu.commit.membars 413125 # Number of memory barriers committed +system.cpu.commit.branches 10023270 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69149691 # Number of committed integer instructions. -system.cpu.commit.function_calls 996276 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69135938 # Number of committed integer instructions. +system.cpu.commit.function_calls 996018 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2849213 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256258159 # The number of ROB reads -system.cpu.rob.rob_writes 209428063 # The number of ROB writes -system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60609996 # Number of Instructions Simulated -system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated -system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 557221655 # number of integer regfile reads -system.cpu.int_regfile_writes 90065137 # number of integer regfile writes -system.cpu.fp_regfile_reads 8220 # number of floating regfile reads -system.cpu.fp_regfile_writes 2852 # number of floating regfile writes -system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads -system.cpu.misc_regfile_writes 913466 # number of misc regfile writes -system.cpu.icache.replacements 990831 # number of replacements -system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use -system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits -system.cpu.icache.overall_hits::total 12036161 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses -system.cpu.icache.overall_misses::total 1075440 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked +system.cpu.rob.rob_reads 249559242 # The number of ROB reads +system.cpu.rob.rob_writes 208759201 # The number of ROB writes +system.cpu.timesIdled 1773088 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320203271 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592410806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60598653 # Number of Instructions Simulated +system.cpu.committedOps 77947265 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60598653 # Number of Instructions Simulated +system.cpu.cpi 7.854363 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.854363 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127318 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556742715 # number of integer regfile reads +system.cpu.int_regfile_writes 89972067 # number of integer regfile writes +system.cpu.fp_regfile_reads 8371 # number of floating regfile reads +system.cpu.fp_regfile_writes 2922 # number of floating regfile writes +system.cpu.misc_regfile_reads 133101437 # number of misc regfile reads +system.cpu.misc_regfile_writes 912914 # number of misc regfile writes +system.cpu.icache.replacements 989669 # number of replacements +system.cpu.icache.tagsinuse 511.593818 # Cycle average of tags in use +system.cpu.icache.total_refs 12001618 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990181 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.120630 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.593818 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12001618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12001618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12001618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12001618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12001618 # number of overall hits +system.cpu.icache.overall_hits::total 12001618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1073577 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1073577 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1073577 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1073577 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1073577 # number of overall misses +system.cpu.icache.overall_misses::total 1073577 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14108104991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14108104991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14108104991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14108104991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14108104991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14108104991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13075195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13075195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13075195 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13075195 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13075195 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13075195 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082108 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082108 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082108 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13141.213896 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13141.213896 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13141.213896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13141.213896 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2357994 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7993.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84051 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991389 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991389 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991389 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991389 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991389 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991389 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12620585492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12620585492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12620585492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12620585492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075612 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12730.205290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12730.205290 # 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Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13934718 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13934718 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7288473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7288473 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284342 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284342 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285730 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285730 # 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number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # 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average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609206 # number of writebacks +system.cpu.dcache.writebacks::total 609206 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339325 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 339325 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713436 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 506735998 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5793829994 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6302908992 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166730274500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166735566500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199259519261 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199264811261 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026667 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985863 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985863 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090356 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090356 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41054.524670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40455.603435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40776.100499 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40256.545723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40256.545723 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -963,16 +959,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307054297856 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307054297856 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index ebf3a5c17..2d955a00e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.537930 # Number of seconds simulated -sim_ticks 2537929870500 # Number of ticks simulated -final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534231 # Number of seconds simulated +sim_ticks 2534231333000 # Number of ticks simulated +final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62423 # Simulator instruction rate (inst/s) -host_op_rate 80294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2613828720 # Simulator tick rate (ticks/s) -host_mem_usage 387060 # Number of bytes of host memory used -host_seconds 970.96 # Real time elapsed on the host -sim_insts 60609996 # Number of instructions simulated -sim_ops 77962726 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory +host_inst_rate 58448 # Simulator instruction rate (inst/s) +host_op_rate 75181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2444289303 # Simulator tick rate (ticks/s) +host_mem_usage 386996 # Number of bytes of host memory used +host_seconds 1036.80 # Real time elapsed on the host +sim_insts 60598653 # Number of instructions simulated +sim_ops 77947265 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory +system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784256 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,273 +61,6 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 64349 # number of replacements -system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 389039 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1463658 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 609524 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 609524 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113135 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 977692 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 502174 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1576793 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 84751 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12176 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 977692 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 502174 # number of overall hits -system.cpu.l2cache.overall_hits::total 1576793 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10706 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133143 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12366 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143849 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156282 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 65 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12366 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143849 # number of overall misses -system.cpu.l2cache.overall_misses::total 156282 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8295680990 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1733075 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1733075 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.090176 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.090176 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53081.487247 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53081.487247 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59057 # number of writebacks -system.cpu.l2cache.writebacks::total 59057 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156212 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -336,27 +69,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51757171 # DTB read hits -system.cpu.dtb.read_misses 78755 # DTB read misses -system.cpu.dtb.write_hits 11824944 # DTB write hits -system.cpu.dtb.write_misses 17612 # DTB write misses +system.cpu.dtb.read_hits 51729232 # DTB read hits +system.cpu.dtb.read_misses 76957 # DTB read misses +system.cpu.dtb.write_hits 11808980 # DTB write hits +system.cpu.dtb.write_misses 17307 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4306 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4248 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51835926 # DTB read accesses -system.cpu.dtb.write_accesses 11842556 # DTB write accesses +system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51806189 # DTB read accesses +system.cpu.dtb.write_accesses 11826287 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63582115 # DTB hits -system.cpu.dtb.misses 96367 # DTB misses -system.cpu.dtb.accesses 63678482 # DTB accesses -system.cpu.itb.inst_hits 13115769 # ITB inst hits -system.cpu.itb.inst_misses 12252 # ITB inst misses +system.cpu.dtb.hits 63538212 # DTB hits +system.cpu.dtb.misses 94264 # DTB misses +system.cpu.dtb.accesses 63632476 # DTB accesses +system.cpu.itb.inst_hits 13079160 # ITB inst hits +system.cpu.itb.inst_misses 12175 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -365,538 +98,538 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2604 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2600 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13128021 # ITB inst accesses -system.cpu.itb.hits 13115769 # DTB hits -system.cpu.itb.misses 12252 # DTB misses -system.cpu.itb.accesses 13128021 # DTB accesses -system.cpu.numCycles 487049956 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13091335 # ITB inst accesses +system.cpu.itb.hits 13079160 # DTB hits +system.cpu.itb.misses 12175 # DTB misses +system.cpu.itb.accesses 13091335 # DTB accesses +system.cpu.numCycles 475963827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits +system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued -system.cpu.iq.rate 0.259310 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued +system.cpu.iq.rate 0.265193 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 226495 # number of nop insts executed -system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed -system.cpu.iew.exec_branches 11753944 # Number of branches executed -system.cpu.iew.exec_stores 12337385 # Number of stores executed -system.cpu.iew.exec_rate 0.252721 # Inst execution rate -system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47490892 # num instructions producing a value -system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value +system.cpu.iew.exec_nop 225525 # number of nop insts executed +system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed +system.cpu.iew.exec_branches 11734992 # Number of branches executed +system.cpu.iew.exec_stores 12321310 # Number of stores executed +system.cpu.iew.exec_rate 0.258373 # Inst execution rate +system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47712496 # num instructions producing a value +system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60760377 # Number of instructions committed -system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60749034 # Number of instructions committed +system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27521116 # Number of memory references committed -system.cpu.commit.loads 15720306 # Number of loads committed -system.cpu.commit.membars 413361 # Number of memory barriers committed -system.cpu.commit.branches 10025135 # Number of branches committed +system.cpu.commit.refs 27515291 # Number of memory references committed +system.cpu.commit.loads 15716471 # Number of loads committed +system.cpu.commit.membars 413125 # Number of memory barriers committed +system.cpu.commit.branches 10023270 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69149691 # Number of committed integer instructions. -system.cpu.commit.function_calls 996276 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69135938 # Number of committed integer instructions. +system.cpu.commit.function_calls 996018 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2849213 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256258159 # The number of ROB reads -system.cpu.rob.rob_writes 209428063 # The number of ROB writes -system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60609996 # Number of Instructions Simulated -system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated -system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 557221649 # number of integer regfile reads -system.cpu.int_regfile_writes 90065135 # number of integer regfile writes -system.cpu.fp_regfile_reads 8220 # number of floating regfile reads -system.cpu.fp_regfile_writes 2852 # number of floating regfile writes -system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads -system.cpu.misc_regfile_writes 913466 # number of misc regfile writes -system.cpu.icache.replacements 990831 # number of replacements -system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use -system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits -system.cpu.icache.overall_hits::total 12036161 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses -system.cpu.icache.overall_misses::total 1075440 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked +system.cpu.rob.rob_reads 249559242 # The number of ROB reads +system.cpu.rob.rob_writes 208759201 # The number of ROB writes +system.cpu.timesIdled 1773088 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320203271 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592410806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60598653 # Number of Instructions Simulated +system.cpu.committedOps 77947265 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60598653 # Number of Instructions Simulated +system.cpu.cpi 7.854363 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.854363 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127318 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 556742712 # number of integer regfile reads +system.cpu.int_regfile_writes 89972066 # number of integer regfile writes +system.cpu.fp_regfile_reads 8371 # number of floating regfile reads +system.cpu.fp_regfile_writes 2922 # number of floating regfile writes +system.cpu.misc_regfile_reads 133101437 # number of misc regfile reads +system.cpu.misc_regfile_writes 912914 # number of misc regfile writes +system.cpu.icache.replacements 989669 # number of replacements +system.cpu.icache.tagsinuse 511.593818 # Cycle average of tags in use +system.cpu.icache.total_refs 12001618 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990181 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.120630 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.593818 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12001618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12001618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12001618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12001618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12001618 # number of overall hits +system.cpu.icache.overall_hits::total 12001618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1073577 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1073577 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1073577 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1073577 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1073577 # number of overall misses +system.cpu.icache.overall_misses::total 1073577 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14108104991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14108104991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14108104991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14108104991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14108104991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14108104991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13075195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13075195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13075195 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13075195 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13075195 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13075195 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082108 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082108 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082108 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13141.213896 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13141.213896 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13141.213896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13141.213896 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13141.213896 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2357994 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7993.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # 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Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285827 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21154214 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21154214 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21154214 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14912254500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14912254500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129601345080 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129601345080 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222071000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222071000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 314500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 314500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144513599580 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144513599580 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144513599580 # 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number of replacements +system.cpu.dcache.tagsinuse 511.991712 # Cycle average of tags in use +system.cpu.dcache.total_refs 21796404 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645677 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.757442 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48877000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991712 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13934718 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13934718 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7288473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7288473 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 284342 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 284342 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285730 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285730 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21223191 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21223191 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21223191 # number of overall hits +system.cpu.dcache.overall_hits::total 21223191 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 726725 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 726725 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962478 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962478 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13561 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13561 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3689203 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3689203 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3689203 # number of overall misses +system.cpu.dcache.overall_misses::total 3689203 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9436874000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9436874000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104178007737 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104178007737 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180640000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180640000 # 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miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148087 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148087 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148087 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148087 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12985.481441 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12985.481441 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35165.833379 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35165.833379 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13320.551582 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13320.551582 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30796.592580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.592580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30796.592580 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12775922 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7850000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2526 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5057.768013 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27738.515901 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks -system.cpu.dcache.writebacks::total 609524 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609206 # number of writebacks +system.cpu.dcache.writebacks::total 609206 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339325 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 339325 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713436 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713436 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1355 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1355 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3052761 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3052761 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3052761 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3052761 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387400 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387400 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249042 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249042 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12206 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12206 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636442 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636442 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636442 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636442 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4757620458 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4757620458 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8541364957 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8541364957 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141415500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141415500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 332500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 332500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13298985415 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13298985415 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13298985415 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13298985415 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407548000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407548000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41944273253 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41944273253 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224351821253 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224351821253 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026423 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026423 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024295 # 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average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12280.899479 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.885493 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34296.885493 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11585.736523 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11585.736523 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -904,6 +637,269 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 64397 # number of replacements +system.cpu.l2cache.tagsinuse 51351.941492 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1929097 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129792 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.862988 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2499029961500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36885.832563 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 46.221263 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8173.888273 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6245.999155 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.562833 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000705 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32529244761 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5292000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 199259519261 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 199264811261 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026667 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985863 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985863 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.090356 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000687 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.090356 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41054.524670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40455.603435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40776.100499 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.926255 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40256.545723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40256.545723 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40263.157895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -918,16 +914,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307054297856 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307054297856 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f421b5375..978d3ed52 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,327 +1,84 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.163939 # Number of seconds simulated -sim_ticks 5163939423500 # Number of ticks simulated -final_tick 5163939423500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.125295 # Number of seconds simulated +sim_ticks 5125295451000 # Number of ticks simulated +final_tick 5125295451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202828 # Simulator instruction rate (inst/s) -host_op_rate 400952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2568035232 # Simulator tick rate (ticks/s) -host_mem_usage 368532 # Number of bytes of host memory used -host_seconds 2010.85 # Real time elapsed on the host -sim_insts 407858031 # Number of instructions simulated -sim_ops 806254969 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2460224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1069888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10576384 # Number of bytes read from this memory -system.physmem.bytes_read::total 14109824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1069888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1069888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9320448 # Number of bytes written to this memory -system.physmem.bytes_written::total 9320448 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38441 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165256 # Number of read requests responded to by this memory -system.physmem.num_reads::total 220466 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 145632 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145632 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 207184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2048123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2732376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 207184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 207184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1804910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1804910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1804910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 207184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2048123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4537286 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 109190 # number of replacements -system.cpu.l2cache.tagsinuse 64839.015299 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3984882 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 173424 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.977685 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 49968.765370 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 13.151051 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.155230 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3435.794855 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11421.148791 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.762463 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052426 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.174273 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989365 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103321 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8437 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1055749 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1347777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2515284 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1610495 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1610495 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 337 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 158131 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 158131 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 103321 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 8437 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1055749 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1505908 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2673415 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 103321 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 8437 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1055749 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1505908 # number of overall hits -system.cpu.l2cache.overall_hits::total 2673415 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16718 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35983 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52753 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3384 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3384 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130218 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130218 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16718 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166201 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 182971 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16718 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166201 # number of overall misses -system.cpu.l2cache.overall_misses::total 182971 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2414500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 312500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 887508500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1921141998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2811377498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 38315000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 38315000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6787419499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6787419499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2414500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 887508500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8708561497 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9598796997 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2414500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 312500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 887508500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8708561497 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9598796997 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103367 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8443 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1072467 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1383760 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2568037 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1610495 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1610495 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3721 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3721 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288349 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288349 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103367 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 8443 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1072467 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1672109 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2856386 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103367 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 8443 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1072467 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1672109 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2856386 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000445 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000711 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015588 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026004 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.020542 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.909433 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.909433 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.451599 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.451599 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000445 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000711 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015588 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.099396 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.064057 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000445 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000711 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015588 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.099396 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.064057 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52489.130435 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52083.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53087.002034 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53390.267571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53293.224992 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11322.399527 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11322.399527 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52123.512103 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52123.512103 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52460.756060 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52460.756060 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98965 # number of writebacks -system.cpu.l2cache.writebacks::total 98965 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1856000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683651500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1481312999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2167060499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 135806000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 135806000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5218894001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5218894001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1856000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683651500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6700207000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7385954500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1856000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683651500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6700207000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7385954500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88673398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88673398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308733000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308733000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90982131500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90982131500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026002 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020541 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.909433 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.909433 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.451599 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.451599 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.064056 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.064056 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40895.585332 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41169.311553 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41081.715621 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40131.796690 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40131.796690 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.130527 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40078.130527 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47573 # number of replacements -system.iocache.tagsinuse 0.184801 # Cycle average of tags in use +host_inst_rate 133696 # Simulator instruction rate (inst/s) +host_op_rate 264282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1679641336 # Simulator tick rate (ticks/s) +host_mem_usage 368820 # Number of bytes of host memory used +host_seconds 3051.42 # Real time elapsed on the host +sim_insts 407963822 # Number of instructions simulated +sim_ops 806434654 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2463488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1076608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10836416 # Number of bytes read from this memory +system.physmem.bytes_read::total 14379776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1076608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1076608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9553280 # Number of bytes written to this memory +system.physmem.bytes_written::total 9553280 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38492 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16822 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169319 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224684 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149270 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149270 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 480653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2114301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2805648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1863947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1863947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1863947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 480653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 210058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2114301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4669595 # Total bandwidth to/from this memory (bytes/s) +system.iocache.replacements 47577 # number of replacements +system.iocache.tagsinuse 0.091712 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996693675000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.184801 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.011550 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.011550 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses -system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.091712 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.005732 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.005732 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses -system.iocache.demand_misses::total 47628 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses -system.iocache.overall_misses::total 47628 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137681932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 137681932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9939428160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9939428160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10077110092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10077110092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10077110092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10077110092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses +system.iocache.demand_misses::total 47632 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses +system.iocache.overall_misses::total 47632 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138301932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 138301932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9924152160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9924152160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10062454092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10062454092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10062454092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10062454092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +87,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151632.083700 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 151632.083700 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212744.609589 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 212744.609589 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 211579.534979 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 211579.534979 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 72537008 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151646.855263 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 151646.855263 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212417.640411 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 212417.640411 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 211254.074824 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 211254.074824 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 71289012 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8981 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8825 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8076.718406 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8078.075014 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 908 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47628 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47628 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47628 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47628 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90434000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90434000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7509668946 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7509668946 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7600102946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7600102946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90847000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 90847000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7494384978 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7494384978 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7585231978 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7585231978 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,18 +129,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99596.916300 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 99596.916300 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160737.777098 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 160737.777098 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99612.938596 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 99612.938596 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160410.637372 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 160410.637372 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -393,141 +150,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 465816448 # number of cpu cycles simulated +system.cpu.numCycles 448616710 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86514848 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86514848 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1196192 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 82053392 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79452542 # Number of BTB hits +system.cpu.BPredUnit.lookups 86513922 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86513922 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1185612 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81821696 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79447101 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31181464 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427226624 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86514848 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79452542 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164016210 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5124580 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 155814 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 72471814 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36433 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 65503 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9296745 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 539923 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4055 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 271815204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.102878 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.406830 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27982708 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427301680 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86513922 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79447101 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164025545 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5056665 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 120243 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63002299 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 57009 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9269960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 518545 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3708 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 259058563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.256074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.417846 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 108229721 39.82% 39.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1589699 0.58% 40.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71960202 26.47% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971866 0.36% 67.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1623537 0.60% 67.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2454126 0.90% 68.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1122252 0.41% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1424890 0.52% 69.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82438911 30.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95463641 36.85% 36.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1593246 0.62% 37.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71955070 27.78% 65.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 970468 0.37% 65.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1621274 0.63% 66.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2451045 0.95% 67.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1124441 0.43% 67.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1422902 0.55% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82456476 31.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271815204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185727 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.917157 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34976255 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69906357 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159691682 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3353316 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3887594 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840157503 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1253 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3887594 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37933620 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43316590 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11886084 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159761513 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15029803 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836332638 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33622 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7171271 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5982447 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16586 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998051723 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816227596 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816227024 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 572 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964187470 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33864246 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 467105 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 474137 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 32047540 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17336278 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10273791 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1251259 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 987046 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829985579 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1254715 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824362930 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 185325 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23972130 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36446956 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 204607 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271815204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.032807 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.413784 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 259058563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192846 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.952487 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31703593 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60473195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159750936 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3297057 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3833782 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840221922 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1208 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3833782 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34472569 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37379630 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10860587 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159949927 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12562068 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836350803 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21427 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5922094 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4820401 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7659 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998159477 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816297556 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816296596 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 960 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964421570 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33737900 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 466538 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 473424 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28941579 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17313500 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10257423 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1154419 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 952791 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829902104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1256068 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824407567 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167070 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23703242 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36101298 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 203347 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 259058563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.182321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.385461 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82518813 30.36% 30.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18405041 6.77% 37.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10590940 3.90% 41.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7611334 2.80% 43.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75787785 27.88% 71.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3621369 1.33% 73.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72414876 26.64% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 725602 0.27% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 139444 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72075437 27.82% 27.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15729256 6.07% 33.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10360511 4.00% 37.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7565386 2.92% 40.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75947592 29.32% 70.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3904357 1.51% 71.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72537575 28.00% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 784064 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 154385 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271815204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 259058563 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 330736 32.15% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 548005 53.27% 85.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150045 14.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 356821 33.57% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553408 52.07% 85.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152587 14.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308450 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796558014 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 305253 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796599749 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -556,246 +313,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18020026 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9476440 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18032887 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9469678 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824362930 # Type of FU issued -system.cpu.iq.rate 1.769716 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1028786 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1921889039 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855222885 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819729616 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825083173 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1659720 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824407567 # Type of FU issued +system.cpu.iq.rate 1.837666 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1062816 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001289 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1909237330 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854871180 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819733271 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 242 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 64 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825165021 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1650397 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3372872 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25465 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11865 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1866399 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3332196 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26785 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11385 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1841480 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1917615 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21790 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932351 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11661 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3887594 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28830241 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2469402 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831240294 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 338803 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17336278 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10273791 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725681 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1777576 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17730 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11865 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 713088 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 629130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1342218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822392031 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17604275 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1970898 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3833782 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26055488 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2116129 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831158172 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342184 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17313500 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10257423 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 725671 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1616608 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15691 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11385 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 710592 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 622404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1332996 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822394271 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17607905 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2013295 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26833761 # number of memory reference insts executed -system.cpu.iew.exec_branches 83292230 # Number of branches executed -system.cpu.iew.exec_stores 9229486 # Number of stores executed -system.cpu.iew.exec_rate 1.765485 # Inst execution rate -system.cpu.iew.wb_sent 821862423 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819729668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639700217 # num instructions producing a value -system.cpu.iew.wb_consumers 1045258728 # num instructions consuming a value +system.cpu.iew.exec_refs 26830923 # number of memory reference insts executed +system.cpu.iew.exec_branches 83287562 # Number of branches executed +system.cpu.iew.exec_stores 9223018 # Number of stores executed +system.cpu.iew.exec_rate 1.833178 # Inst execution rate +system.cpu.iew.wb_sent 821886032 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819733335 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640537929 # num instructions producing a value +system.cpu.iew.wb_consumers 1046481965 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.759770 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612002 # average fanout of values written-back +system.cpu.iew.wb_rate 1.827247 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612087 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24883748 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050106 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1201289 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267943051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.009053 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.862554 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24617298 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052719 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1189640 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255240182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.159513 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.852385 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95668224 35.70% 35.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12347484 4.61% 40.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3939395 1.47% 41.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74898098 27.95% 69.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2419496 0.90% 70.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1554494 0.58% 71.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1057385 0.39% 71.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70928163 26.47% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5130312 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83212701 32.60% 32.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11927297 4.67% 37.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4018442 1.57% 38.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74971615 29.37% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2476707 0.97% 69.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1494205 0.59% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1000959 0.39% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70934027 27.79% 97.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5204229 2.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267943051 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407858031 # Number of instructions committed -system.cpu.commit.committedOps 806254969 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255240182 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407963822 # Number of instructions committed +system.cpu.commit.committedOps 806434654 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22370795 # Number of memory references committed -system.cpu.commit.loads 13963403 # Number of loads committed -system.cpu.commit.membars 471705 # Number of memory barriers committed -system.cpu.commit.branches 82181312 # Number of branches committed +system.cpu.commit.refs 22397244 # Number of memory references committed +system.cpu.commit.loads 13981301 # Number of loads committed +system.cpu.commit.membars 473469 # Number of memory barriers committed +system.cpu.commit.branches 82197284 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735195017 # Number of committed integer instructions. +system.cpu.commit.int_insts 735369790 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5130312 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5204229 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1093872885 # The number of ROB reads -system.cpu.rob.rob_writes 1666184214 # The number of ROB writes -system.cpu.timesIdled 1421273 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 194001244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9862059849 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407858031 # Number of Instructions Simulated -system.cpu.committedOps 806254969 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407858031 # Number of Instructions Simulated -system.cpu.cpi 1.142104 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.142104 # CPI: Total CPI of All Threads -system.cpu.ipc 0.875577 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.875577 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508209791 # number of integer regfile reads -system.cpu.int_regfile_writes 977816443 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.misc_regfile_reads 265196274 # number of misc regfile reads -system.cpu.misc_regfile_writes 402502 # number of misc regfile writes -system.cpu.icache.replacements 1071989 # number of replacements -system.cpu.icache.tagsinuse 510.817098 # Cycle average of tags in use -system.cpu.icache.total_refs 8149627 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1072501 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.598713 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 147426882000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.817098 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997690 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997690 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8149627 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8149627 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8149627 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8149627 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8149627 # number of overall hits -system.cpu.icache.overall_hits::total 8149627 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1147113 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1147113 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1147113 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1147113 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1147113 # number of overall misses -system.cpu.icache.overall_misses::total 1147113 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18981109491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18981109491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18981109491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18981109491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18981109491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18981109491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9296740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9296740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9296740 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9296740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9296740 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9296740 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123389 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123389 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123389 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123389 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123389 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123389 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16546.852395 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16546.852395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16546.852395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16546.852395 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3167993 # number of cycles access was blocked +system.cpu.rob.rob_reads 1081009655 # The number of ROB reads +system.cpu.rob.rob_writes 1665958243 # The number of ROB writes +system.cpu.timesIdled 1218536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189558147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9801971615 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407963822 # Number of Instructions Simulated +system.cpu.committedOps 806434654 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407963822 # Number of Instructions Simulated +system.cpu.cpi 1.099648 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.099648 # CPI: Total CPI of All Threads +system.cpu.ipc 0.909382 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.909382 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508373932 # number of integer regfile reads +system.cpu.int_regfile_writes 977906784 # number of integer regfile writes +system.cpu.fp_regfile_reads 64 # number of floating regfile reads +system.cpu.misc_regfile_reads 265175533 # number of misc regfile reads +system.cpu.misc_regfile_writes 402332 # number of misc regfile writes +system.cpu.icache.replacements 1068558 # number of replacements +system.cpu.icache.tagsinuse 510.894483 # Cycle average of tags in use +system.cpu.icache.total_refs 8130546 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1069070 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.605251 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.894483 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997841 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997841 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8130546 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8130546 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8130546 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8130546 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8130546 # number of overall hits +system.cpu.icache.overall_hits::total 8130546 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1139410 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1139410 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1139410 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1139410 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1139410 # number of overall misses +system.cpu.icache.overall_misses::total 1139410 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15243937992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15243937992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15243937992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15243937992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15243937992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15243937992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9269956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9269956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9269956 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9269956 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9269956 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9269956 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13378.799547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13378.799547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13378.799547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13378.799547 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2477494 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 401 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7900.231920 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9753.913386 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72595 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 72595 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 72595 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 72595 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 72595 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 72595 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074518 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1074518 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1074518 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1074518 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1074518 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1074518 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14814669993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14814669993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14814669993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14814669993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14814669993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14814669993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115580 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115580 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115580 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13787.270193 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13787.270193 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68152 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68152 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68152 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68152 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68152 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68152 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071258 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1071258 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1071258 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1071258 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1071258 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1071258 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12539776496 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12539776496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12539776496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12539776496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12539776496 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12539776496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115562 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115562 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115562 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11705.654937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11705.654937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9931 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.048032 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 33329 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9947 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.350658 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5125253660500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.048032 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.378002 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.378002 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 33326 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 33326 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9803 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.028064 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 28000 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9816 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.852486 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5098956249000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028064 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376754 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376754 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28010 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 28010 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 33329 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 33329 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 33329 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 33329 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10825 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10825 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10825 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10825 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10825 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10825 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 178140000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 178140000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 178140000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 178140000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 178140000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 178140000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 44151 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 44151 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28013 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 28013 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28013 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 28013 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10692 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10692 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10692 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10692 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10692 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10692 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117857500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117857500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117857500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 117857500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117857500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 117857500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38702 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38702 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 44154 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 44154 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 44154 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 44154 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.245181 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.245181 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.245165 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.245165 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.245165 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.245165 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16456.351039 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16456.351039 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16456.351039 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16456.351039 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38705 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38705 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38705 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38705 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.276265 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.276265 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.276243 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.276243 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.276243 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.276243 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11022.961092 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11022.961092 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11022.961092 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,78 +561,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10825 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10825 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10825 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10825 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10825 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10825 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 145034027 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 145034027 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 145034027 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 145034027 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 145034027 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 145034027 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245181 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245181 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245165 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245165 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13398.062540 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1616 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1616 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10692 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10692 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10692 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10692 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10692 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10692 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96471005 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96471005 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96471005 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96471005 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96471005 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96471005 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.276265 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.276265 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.276243 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.276243 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9022.727740 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109056 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.865602 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 139886 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109072 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.282511 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108962066000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.865602 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866600 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.866600 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139886 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 139886 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139886 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 139886 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139886 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 139886 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110096 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110096 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110096 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110096 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110096 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110096 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2001823500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2001823500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2001823500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2001823500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2001823500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2001823500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249982 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 249982 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249982 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 249982 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249982 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 249982 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.440416 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.440416 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.440416 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.440416 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.440416 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.440416 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18182.527067 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18182.527067 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18182.527067 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109091 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 11.986906 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 138731 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109107 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.271513 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.986906 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749182 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.749182 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138731 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 138731 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138731 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 138731 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138731 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 138731 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110113 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110113 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110113 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110113 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110113 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110113 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1378090500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1378090500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1378090500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1378090500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1378090500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1378090500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248844 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 248844 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248844 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 248844 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248844 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 248844 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442498 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442498 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442498 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442498 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442498 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442498 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12515.238891 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12515.238891 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12515.238891 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -884,146 +641,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35215 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35215 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110096 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110096 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110096 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110096 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110096 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110096 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1668892003 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1668892003 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1668892003 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.440416 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.440416 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.440416 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15158.516231 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 32856 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 32856 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110113 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110113 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110113 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110113 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110113 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110113 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1157860508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1157860508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1157860508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442498 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442498 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442498 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.202637 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1672208 # number of replacements -system.cpu.dcache.tagsinuse 511.998155 # Cycle average of tags in use -system.cpu.dcache.total_refs 19212274 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1672720 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.485649 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35774000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998155 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11127928 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11127928 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8079547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8079547 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19207475 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19207475 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19207475 # number of overall hits -system.cpu.dcache.overall_hits::total 19207475 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2271021 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2271021 # 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number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |