diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot')
8 files changed, 977 insertions, 953 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 2ecc483cf..97b29a376 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -11,11 +11,12 @@ type=LinuxX86System children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus acpi_description_table_pointer=system.acpi_description_table_pointer boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 +clock=1 e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -51,23 +52,21 @@ oem_table_id= [system.apicbridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 -write_ack=false master=system.membus.slave[0] slave=system.iobus.master[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[1] @@ -139,7 +138,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -173,6 +171,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -201,6 +200,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -209,6 +209,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -497,6 +498,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=true @@ -519,9 +521,10 @@ mem_side=system.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic +clock=1 int_latency=1000 pio_addr=2305843009213693952 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.membus.slave[4] int_slave=system.membus.master[3] @@ -535,6 +538,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker +clock=1 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -543,6 +547,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -945,6 +950,7 @@ type=BaseCache addr_ranges=0:134217727 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 is_top_level=false @@ -970,6 +976,7 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 is_top_level=false @@ -1004,9 +1011,10 @@ slave=system.apicbridge.master system.system_port system.iocache.mem_side system [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -1026,9 +1034,10 @@ system=system [system.pc.behind_pci] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854779128 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1043,8 +1052,9 @@ pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 children=terminal +clock=1 pio_addr=9223372036854776824 -pio_latency=1000 +pio_latency=100000 platform=system.pc system=system terminal=system.pc.com_1.terminal @@ -1066,9 +1076,10 @@ port=3456 [system.pc.fake_com_2] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776568 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1082,9 +1093,10 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776808 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1098,9 +1110,10 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776552 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1114,9 +1127,10 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854776818 -pio_latency=1000 +pio_latency=100000 pio_size=2 ret_bad_addr=false ret_data16=65535 @@ -1130,9 +1144,10 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake +clock=1 fake_mem=false pio_addr=9223372036854775936 -pio_latency=1000 +pio_latency=100000 pio_size=1 ret_bad_addr=false ret_data16=65535 @@ -1147,7 +1162,8 @@ pio=system.iobus.master[11] [system.pc.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1 +pio_latency=30000 platform=system.pc size=16777216 system=system @@ -1162,7 +1178,6 @@ io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 pic2=system.pc.south_bridge.pic2 -pio_latency=1000 pit=system.pc.south_bridge.pit platform=system.pc speaker=system.pc.south_bridge.speaker @@ -1170,9 +1185,10 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin +clock=1 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 -pio_latency=1000 +pio_latency=100000 system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.master[1] @@ -1182,8 +1198,9 @@ type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 +clock=1 pio_addr=9223372036854775808 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] @@ -1228,16 +1245,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=4 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.pc system=system config=system.iobus.master[4] @@ -1261,7 +1277,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1281,7 +1297,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1364,10 +1380,11 @@ number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 +clock=1 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 -pio_latency=1000 +pio_latency=100000 system=system int_master=system.iobus.slave[2] pio=system.iobus.master[10] @@ -1375,12 +1392,13 @@ pio=system.iobus.master[10] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin +clock=1 command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[5] @@ -1393,10 +1411,11 @@ type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output +clock=1 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 -pio_latency=1000 +pio_latency=100000 slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.master[6] @@ -1407,10 +1426,11 @@ type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output +clock=1 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 -pio_latency=1000 +pio_latency=100000 slave=Null system=system pio=system.iobus.master[7] @@ -1421,9 +1441,10 @@ type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin +clock=1 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[8] @@ -1432,14 +1453,16 @@ type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker +clock=1 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 98becac20..54a312ff8 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -8,7 +8,6 @@ warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc warn: instruction 'fxsave' unimplemented warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 22a267134..a7e5df44c 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:30:36 -gem5 started Jul 27 2012 00:44:18 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:31:43 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5172910256500 because m5_exit instruction encountered +Exiting @ tick 5167941639500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 2d55f3c33..199522594 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.172174 # Number of seconds simulated -sim_ticks 5172174196500 # Number of ticks simulated -final_tick 5172174196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.167942 # Number of seconds simulated +sim_ticks 5167941639500 # Number of ticks simulated +final_tick 5167941639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197854 # Simulator instruction rate (inst/s) -host_op_rate 391125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2509698416 # Simulator tick rate (ticks/s) -host_mem_usage 367744 # Number of bytes of host memory used -host_seconds 2060.87 # Real time elapsed on the host -sim_insts 407751921 # Number of instructions simulated -sim_ops 806059216 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2469504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1070336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10446016 # Number of bytes read from this memory -system.physmem.bytes_read::total 13989120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1070336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1070336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9206912 # Number of bytes written to this memory -system.physmem.bytes_written::total 9206912 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38586 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16724 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 163219 # Number of read requests responded to by this memory -system.physmem.num_reads::total 218580 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143858 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143858 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 477460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 206941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2019657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2704688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 206941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 206941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1780085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1780085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1780085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 477460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 206941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2019657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4484774 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 107330 # number of replacements -system.l2c.tagsinuse 64831.864344 # Cycle average of tags in use -system.l2c.total_refs 3982185 # Total number of references to valid blocks. -system.l2c.sampled_refs 171532 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.215406 # Average number of references to valid blocks. +host_inst_rate 128954 # Simulator instruction rate (inst/s) +host_op_rate 254914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1633898837 # Simulator tick rate (ticks/s) +host_mem_usage 412792 # Number of bytes of host memory used +host_seconds 3162.95 # Real time elapsed on the host +sim_insts 407876198 # Number of instructions simulated +sim_ops 806280456 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2473280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1074496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10579456 # Number of bytes read from this memory +system.physmem.bytes_read::total 14130624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1074496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1074496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9348288 # Number of bytes written to this memory +system.physmem.bytes_written::total 9348288 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38645 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16789 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165304 # Number of read requests responded to by this memory +system.physmem.num_reads::total 220791 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 146067 # Number of write requests responded to by this memory +system.physmem.num_writes::total 146067 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 478581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 207916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2047131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2734285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1808900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1808900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1808900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 478581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 207916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2047131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4543184 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 109808 # number of replacements +system.l2c.tagsinuse 64836.655656 # Cycle average of tags in use +system.l2c.total_refs 3979638 # Total number of references to valid blocks. +system.l2c.sampled_refs 173786 # Sample count of references to valid blocks. +system.l2c.avg_refs 22.899647 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50277.913573 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 9.980895 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.169682 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3388.636576 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11155.163618 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.767180 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000152 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051706 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.170214 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989256 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 111938 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8555 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1051956 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1345107 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2517556 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1612922 # number of Writeback hits -system.l2c.Writeback_hits::total 1612922 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 325 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 325 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 163659 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 163659 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 111938 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8555 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1051956 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1508766 # number of demand (read+write) hits -system.l2c.demand_hits::total 2681215 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 111938 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8555 # 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number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136172932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 136172932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6920648160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6920648160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7056821092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7056821092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7056821092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7056821092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses +system.iocache.demand_misses::total 47626 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses +system.iocache.overall_misses::total 47626 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136049932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 136049932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6913813160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6913813160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7049863092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7049863092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 7049863092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7049863092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,14 +330,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150135.536935 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 150135.536935 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148130.311644 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 148130.311644 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 148168.498793 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 148168.498793 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150165.487859 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 150165.487859 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147984.014555 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 147984.014555 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 148025.513207 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 148025.513207 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked @@ -348,22 +348,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88977000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88977000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4490887946 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4490887946 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4579864946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4579864946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88906000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88906000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4484057918 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4484057918 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4572963918 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4572963918 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4572963918 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4572963918 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98100.330761 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98100.330761 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96123.457748 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 96123.457748 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98130.242826 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 98130.242826 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95977.267080 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 95977.267080 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,411 +393,411 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 475031565 # number of cpu cycles simulated +system.cpu.numCycles 465854401 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86684856 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86684856 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1176632 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 82122133 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79543196 # Number of BTB hits +system.cpu.BPredUnit.lookups 86523106 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86523106 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1197724 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 82002674 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79454296 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31269539 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 428184771 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86684856 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79543196 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164289785 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5325147 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 164614 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 76824227 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37234 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 45914 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 429 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9378048 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 536886 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4957 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 276741596 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.053538 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.401990 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31142494 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427260156 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86523106 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79454296 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164033620 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5133412 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 157235 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 72542740 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 65499 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9290212 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 538342 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3947 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 271874324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.102439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.406784 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 112886536 40.79% 40.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1619655 0.59% 41.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71962795 26.00% 67.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 983886 0.36% 67.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1644119 0.59% 68.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2486257 0.90% 69.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1139995 0.41% 69.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1450599 0.52% 70.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82567754 29.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 108271510 39.82% 39.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1601345 0.59% 40.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71956301 26.47% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 975717 0.36% 67.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1623613 0.60% 67.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2452165 0.90% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1122687 0.41% 69.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1426947 0.52% 69.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82444039 30.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 276741596 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.182482 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.901382 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35010017 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 74311956 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159865423 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3444346 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4109854 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 841785392 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 993 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4109854 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38173067 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 41532647 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11823127 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159691932 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 21410969 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 837988743 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10561 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14331873 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3961467 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8380256 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1328629800 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2380702001 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2380701417 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 584 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1282020322 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46609471 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 469457 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 477289 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 33840968 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17569417 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10446486 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1246814 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1007946 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 831743249 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1259421 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823989117 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 123035 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26027822 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 53490149 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 209479 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 276741596 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.977468 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.409448 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 271874324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185730 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.917154 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34951113 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 69967599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159705810 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3354905 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3894897 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840212837 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1268 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3894897 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37909479 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43328722 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11932417 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159774211 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15034598 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836385126 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 33598 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7166437 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5990052 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 17455 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998119194 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816357971 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816357131 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 840 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964226207 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33892980 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 468339 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476044 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 32058525 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17336195 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10280230 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1246899 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 991215 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 830038809 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1256743 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824423080 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186157 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23985276 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36420028 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 206597 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 271874324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.032368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.413899 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 86092872 31.11% 31.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17946523 6.48% 37.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 12957239 4.68% 42.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7826219 2.83% 45.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 76249367 27.55% 72.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3109383 1.12% 73.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 71927366 25.99% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 520136 0.19% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 112491 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82559406 30.37% 30.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18414875 6.77% 37.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10591768 3.90% 41.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7608288 2.80% 43.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75794422 27.88% 71.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3619554 1.33% 73.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72418483 26.64% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 726775 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 140753 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 276741596 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 271874324 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 163103 18.01% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 583729 64.45% 82.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 158924 17.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 331331 32.21% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547593 53.24% 85.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 149610 14.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 296041 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796340985 96.64% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17916922 2.17% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9435169 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308279 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796609033 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18024617 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9481151 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823989117 # Type of FU issued -system.cpu.iq.rate 1.734599 # Inst issue rate -system.cpu.iq.fu_busy_cnt 905756 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001099 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1925886604 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 859041376 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819484767 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 824598744 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 88 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1578458 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824423080 # Type of FU issued +system.cpu.iq.rate 1.769701 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1028534 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001248 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1922068884 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 855291159 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819794003 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 201 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 398 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825143243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1662305 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3618337 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20593 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12016 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2047079 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3372855 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25441 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11901 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1870494 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1917340 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4451 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1917611 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21826 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4109854 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27168187 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1772103 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 833002670 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 300864 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17569417 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10446486 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 728436 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 974858 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15486 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12016 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 697910 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 625387 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1323297 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822095189 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17489841 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1893927 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3894897 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28837700 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2469058 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831295552 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 338895 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17336195 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10280230 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 727529 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1778064 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16969 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11901 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 715653 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 628490 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1344143 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822456639 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17610649 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1966440 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26681633 # number of memory reference insts executed -system.cpu.iew.exec_branches 83151598 # Number of branches executed -system.cpu.iew.exec_stores 9191792 # Number of stores executed -system.cpu.iew.exec_rate 1.730612 # Inst execution rate -system.cpu.iew.wb_sent 821608460 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819484817 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640296111 # num instructions producing a value -system.cpu.iew.wb_consumers 1828731330 # num instructions consuming a value +system.cpu.iew.exec_refs 26845315 # number of memory reference insts executed +system.cpu.iew.exec_branches 83298308 # Number of branches executed +system.cpu.iew.exec_stores 9234666 # Number of stores executed +system.cpu.iew.exec_rate 1.765480 # Inst execution rate +system.cpu.iew.wb_sent 821926439 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819794057 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639752157 # num instructions producing a value +system.cpu.iew.wb_consumers 1045352654 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.725117 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.350131 # average fanout of values written-back +system.cpu.iew.wb_rate 1.759765 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611996 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 407751921 # The number of committed instructions -system.cpu.commit.commitCommittedOps 806059216 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26839677 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1049940 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1181775 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 272647181 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.956419 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.843352 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 407876198 # The number of committed instructions +system.cpu.commit.commitCommittedOps 806280456 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24913133 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1050144 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1202812 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267994872 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.008567 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.862606 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 98573076 36.15% 36.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13223290 4.85% 41.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4246957 1.56% 42.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 75817327 27.81% 70.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2710299 0.99% 71.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1789124 0.66% 72.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1087866 0.40% 72.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71017917 26.05% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4181325 1.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95708063 35.71% 35.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12360558 4.61% 40.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3940570 1.47% 41.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74894252 27.95% 69.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2417220 0.90% 70.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1553799 0.58% 71.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1057768 0.39% 71.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70929617 26.47% 98.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5133025 1.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 272647181 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407751921 # Number of instructions committed -system.cpu.commit.committedOps 806059216 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267994872 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407876198 # Number of instructions committed +system.cpu.commit.committedOps 806280456 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22350484 # Number of memory references committed -system.cpu.commit.loads 13951077 # Number of loads committed -system.cpu.commit.membars 471695 # Number of memory barriers committed -system.cpu.commit.branches 82163258 # Number of branches committed +system.cpu.commit.refs 22373073 # Number of memory references committed +system.cpu.commit.loads 13963337 # Number of loads committed +system.cpu.commit.membars 471701 # Number of memory barriers committed +system.cpu.commit.branches 82186197 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735013406 # Number of committed integer instructions. +system.cpu.commit.int_insts 735221140 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4181325 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5133025 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1101286190 # The number of ROB reads -system.cpu.rob.rob_writes 1669922447 # The number of ROB writes -system.cpu.timesIdled 1659907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 198289969 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9869314281 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407751921 # Number of Instructions Simulated -system.cpu.committedOps 806059216 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407751921 # Number of Instructions Simulated -system.cpu.cpi 1.165001 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.165001 # CPI: Total CPI of All Threads -system.cpu.ipc 0.858368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.858368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2053713870 # number of integer regfile reads -system.cpu.int_regfile_writes 1297159076 # number of integer regfile writes -system.cpu.fp_regfile_reads 50 # number of floating regfile reads -system.cpu.misc_regfile_reads 265135377 # number of misc regfile reads -system.cpu.misc_regfile_writes 402339 # number of misc regfile writes -system.cpu.icache.replacements 1068223 # number of replacements -system.cpu.icache.tagsinuse 510.418027 # Cycle average of tags in use -system.cpu.icache.total_refs 8239400 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1068735 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.709488 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 57281567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.418027 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996910 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996910 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8239400 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8239400 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8239400 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8239400 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8239400 # number of overall hits -system.cpu.icache.overall_hits::total 8239400 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1138645 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1138645 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1138645 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1138645 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1138645 # number of overall misses -system.cpu.icache.overall_misses::total 1138645 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18814976480 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18814976480 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18814976480 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18814976480 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18814976480 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18814976480 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9378045 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9378045 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9378045 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9378045 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9378045 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9378045 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121416 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121416 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121416 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121416 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121416 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121416 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16524.005709 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16524.005709 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16524.005709 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16524.005709 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3200487 # number of cycles access was blocked +system.cpu.rob.rob_reads 1093976833 # The number of ROB reads +system.cpu.rob.rob_writes 1666301286 # The number of ROB writes +system.cpu.timesIdled 1419086 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 193980077 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9870026331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407876198 # Number of Instructions Simulated +system.cpu.committedOps 806280456 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407876198 # Number of Instructions Simulated +system.cpu.cpi 1.142147 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.142147 # CPI: Total CPI of All Threads +system.cpu.ipc 0.875544 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.875544 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508347107 # number of integer regfile reads +system.cpu.int_regfile_writes 977902256 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.misc_regfile_reads 265221380 # number of misc regfile reads +system.cpu.misc_regfile_writes 402568 # number of misc regfile writes +system.cpu.icache.replacements 1070981 # number of replacements +system.cpu.icache.tagsinuse 510.788530 # Cycle average of tags in use +system.cpu.icache.total_refs 8144587 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1071493 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.601157 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 147426882000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.788530 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997634 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997634 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8144587 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8144587 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8144587 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8144587 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8144587 # number of overall hits +system.cpu.icache.overall_hits::total 8144587 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1145619 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1145619 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1145619 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1145619 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1145619 # number of overall misses +system.cpu.icache.overall_misses::total 1145619 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18957217490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18957217490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18957217490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18957217490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18957217490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18957217490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9290206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9290206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9290206 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9290206 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9290206 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9290206 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123315 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123315 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123315 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123315 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123315 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123315 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16547.576018 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16547.576018 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16547.576018 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16547.576018 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16547.576018 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16547.576018 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3193494 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 386 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8291.417098 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7885.170370 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69787 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69787 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69787 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69787 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69787 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69787 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1068858 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1068858 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1068858 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1068858 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1068858 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1068858 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14704003987 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14704003987 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14704003987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14704003987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14704003987 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14704003987 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113975 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.113975 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.113975 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13756.742230 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13756.742230 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72182 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 72182 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 72182 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 72182 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 72182 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 72182 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1073437 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1073437 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1073437 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1073437 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1073437 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1073437 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14797672994 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14797672994 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14797672994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14797672994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14797672994 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14797672994 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115545 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115545 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115545 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115545 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115545 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115545 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13785.320418 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13785.320418 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13785.320418 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13785.320418 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13785.320418 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13785.320418 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10021 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.028958 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 32291 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10034 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.218158 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5136098133000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028958 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376810 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376810 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 32310 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 32310 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9807 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.044173 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 32941 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9822 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 3.353798 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5136134294000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.044173 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377761 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.377761 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 32940 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 32940 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 32313 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 32313 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 32313 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 32313 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10911 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10911 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10911 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10911 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10911 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10911 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183901500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183901500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183901500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 183901500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183901500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 183901500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 32943 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 32943 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 32943 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 32943 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10696 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10696 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10696 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10696 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10696 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10696 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176478000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176478000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176478000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 176478000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176478000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 176478000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43636 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 43636 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43224 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 43224 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43224 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 43224 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.252447 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.252447 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.252429 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.252429 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.252429 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.252429 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16854.687930 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16854.687930 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16854.687930 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16854.687930 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43639 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 43639 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43639 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 43639 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.245119 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.245119 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.245102 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.245102 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.245102 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.245102 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16499.439043 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16499.439043 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16499.439043 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16499.439043 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16499.439043 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16499.439043 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,78 +806,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1563 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1563 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10911 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10911 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10911 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10911 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10911 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10911 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 150559535 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 150559535 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 150559535 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 150559535 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 150559535 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 150559535 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.252447 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.252447 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.252429 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.252429 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13798.875905 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1799 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1799 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10696 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10696 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10696 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10696 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10696 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10696 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143761538 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143761538 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143761538 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143761538 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143761538 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143761538 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245119 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245119 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245102 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245102 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13440.682311 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 116564 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.971477 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 137576 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 116580 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.180100 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5113123336000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.971477 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810717 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.810717 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137576 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 137576 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137576 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 137576 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137576 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 137576 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117614 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 117614 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117614 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 117614 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117614 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 117614 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2140596500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2140596500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2140596500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2140596500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2140596500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2140596500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255190 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 255190 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255190 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 255190 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255190 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 255190 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.460888 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.460888 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.460888 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.460888 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.460888 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.460888 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18200.184502 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18200.184502 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18200.184502 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18200.184502 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109374 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.962684 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 139077 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109389 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.271398 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5108961672000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.962684 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810168 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.810168 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139087 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 139087 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139087 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 139087 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139087 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 139087 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110364 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110364 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110364 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110364 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110364 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110364 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2009314000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2009314000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2009314000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2009314000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2009314000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2009314000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249451 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 249451 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249451 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 249451 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249451 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 249451 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442428 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442428 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442428 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442428 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442428 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442428 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18206.244790 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18206.244790 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18206.244790 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18206.244790 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,146 +886,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 39184 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 39184 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117614 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117614 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117614 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 117614 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117614 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 117614 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1785080011 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1785080011 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1785080011 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.460888 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.460888 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.460888 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15177.444956 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35688 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35688 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110364 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110364 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110364 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110364 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110364 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110364 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1675589507 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1675589507 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1675589507 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442428 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442428 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442428 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15182.391967 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673020 # number of replacements -system.cpu.dcache.tagsinuse 511.997654 # Cycle average of tags in use -system.cpu.dcache.total_refs 19008279 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673532 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.358181 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997654 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10932679 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10932679 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8073031 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8073031 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19005710 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19005710 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19005710 # number of overall hits -system.cpu.dcache.overall_hits::total 19005710 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2430444 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2430444 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317095 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317095 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2747539 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2747539 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2747539 # number of overall misses -system.cpu.dcache.overall_misses::total 2747539 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45216991000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45216991000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10602716492 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10602716492 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55819707492 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55819707492 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55819707492 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55819707492 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13363123 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13363123 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8390126 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8390126 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21753249 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21753249 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21753249 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21753249 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181877 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.181877 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037794 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037794 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.126305 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.126305 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.126305 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.126305 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18604.415901 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18604.415901 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33437.034617 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33437.034617 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20316.256654 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20316.256654 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27551492 # number of cycles access was blocked +system.cpu.dcache.replacements 1671342 # number of replacements +system.cpu.dcache.tagsinuse 511.998194 # Cycle average of tags in use +system.cpu.dcache.total_refs 19219573 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1671854 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.495964 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35774000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.998194 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11132776 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11132776 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8081984 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8081984 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19214760 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19214760 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19214760 # number of overall hits +system.cpu.dcache.overall_hits::total 19214760 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2269875 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2269875 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318465 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318465 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2588340 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2588340 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2588340 # number of overall misses +system.cpu.dcache.overall_misses::total 2588340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48782293500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48782293500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10759861985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10759861985 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 59542155485 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 59542155485 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 59542155485 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 59542155485 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13402651 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13402651 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8400449 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8400449 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21803100 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21803100 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21803100 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21803100 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169360 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169360 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037910 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037910 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21491.180572 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21491.180572 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33786.638987 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33786.638987 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23003.993094 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23003.993094 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 188390485 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4916 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 47569 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5604.453214 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3960.362526 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1572175 # number of writebacks -system.cpu.dcache.writebacks::total 1572175 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1048961 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1048961 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22710 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22710 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1071671 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1071671 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1071671 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1071671 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381483 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1381483 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294385 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 294385 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1675868 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1675868 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1675868 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1675868 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23305790513 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23305790513 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9339566493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9339566493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32645357006 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32645357006 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32645357006 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32645357006 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96733569500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96733569500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2477085000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2477085000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99210654500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99210654500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103380 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103380 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077040 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16870.124723 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16870.124723 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31725.687426 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31725.687426 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1572665 # number of writebacks +system.cpu.dcache.writebacks::total 1572665 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885789 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 885789 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26582 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26582 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912371 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912371 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912371 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912371 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1384086 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1384086 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291883 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291883 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1675969 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1675969 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1675969 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1675969 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25963695523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25963695523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9454770488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9454770488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35418466011 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 35418466011 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35418466011 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 35418466011 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96735790500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96735790500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2476089500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2476089500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99211880000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99211880000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034746 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076868 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076868 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076868 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076868 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18758.729965 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18758.729965 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32392.330105 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32392.330105 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21133.127171 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21133.127171 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21133.127171 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21133.127171 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 6a8db2c50..0bbc8945c 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -39,7 +39,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812499
+result 7812531
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats index 5488faf0f..094befb99 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,24 +1,24 @@ -Real time: Sep/10/2012 12:39:22 +Real time: Sep/10/2012 23:29:19 Profiler Stats -------------- -Elapsed_time_in_seconds: 743 -Elapsed_time_in_minutes: 12.3833 -Elapsed_time_in_hours: 0.206389 -Elapsed_time_in_days: 0.00859954 +Elapsed_time_in_seconds: 752 +Elapsed_time_in_minutes: 12.5333 +Elapsed_time_in_hours: 0.208889 +Elapsed_time_in_days: 0.0087037 -Virtual_time_in_seconds: 741.97 -Virtual_time_in_minutes: 12.3662 -Virtual_time_in_hours: 0.206103 -Virtual_time_in_days: 0.00858762 +Virtual_time_in_seconds: 751.42 +Virtual_time_in_minutes: 12.5237 +Virtual_time_in_hours: 0.208728 +Virtual_time_in_days: 0.00869699 Ruby_current_time: 10410013848 Ruby_start_time: 0 Ruby_cycles: 10410013848 -mbytes_resident: 256.176 -mbytes_total: 493.555 -resident_ratio: 0.51905 +mbytes_resident: 256.566 +mbytes_total: 493.43 +resident_ratio: 0.519973 ruby_cycles_executed: [ 10410013849 10410013849 ] @@ -87,13 +87,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4899404 average: 0.0429665 | Resource Usage -------------- page_size: 4096 -user_time: 741 +user_time: 751 system_time: 0 -page_reclaims: 56598 +page_reclaims: 57058 page_faults: 18 swaps: 0 -block_inputs: 28712 -block_outputs: 496 +block_inputs: 16016 +block_outputs: 528 Network Stats ------------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index 7cba7ff73..a4aaa0fce 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-bo gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 12:26:53 -gem5 started Sep 10 2012 12:26:58 +gem5 compiled Sep 10 2012 23:16:41 +gem5 started Sep 10 2012 23:16:46 gem5 executing on ribera.cs.wisc.edu command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory warning: add_child('terminal'): child 'terminal' already has parent diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index 2c7da93fe..ccb436843 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.205007 # Nu sim_ticks 5205006924000 # Number of ticks simulated final_tick 5205006924000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145510 # Simulator instruction rate (inst/s) -host_op_rate 279202 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7001191594 # Simulator tick rate (ticks/s) -host_mem_usage 505404 # Number of bytes of host memory used -host_seconds 743.45 # Real time elapsed on the host +host_inst_rate 143770 # Simulator instruction rate (inst/s) +host_op_rate 275863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6917470976 # Simulator tick rate (ticks/s) +host_mem_usage 505276 # Number of bytes of host memory used +host_seconds 752.44 # Real time elapsed on the host sim_insts 108178578 # Number of instructions simulated sim_ops 207571464 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory @@ -125,8 +125,8 @@ system.cpu0.num_func_calls 0 # nu system.cpu0.num_conditional_control_insts 16553172 # number of instructions that are conditional controls system.cpu0.num_int_insts 169447650 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 526613811 # number of times the integer registers were read -system.cpu0.num_int_register_writes 279904453 # number of times the integer registers were written +system.cpu0.num_int_register_reads 418656867 # number of times the integer registers were read +system.cpu0.num_int_register_writes 211655789 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written system.cpu0.num_mem_refs 20197632 # number of memory refs @@ -149,8 +149,8 @@ system.cpu1.num_func_calls 0 # nu system.cpu1.num_conditional_control_insts 1864532 # number of instructions that are conditional controls system.cpu1.num_int_insts 27537877 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 83543948 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39599816 # number of times the integer registers were written +system.cpu1.num_int_register_reads 71380294 # number of times the integer registers were read +system.cpu1.num_int_register_writes 31003707 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written system.cpu1.num_mem_refs 6975131 # number of memory refs |