diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot')
12 files changed, 3336 insertions, 3226 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 35fda0d55..f66d752af 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,13 +10,15 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +clock=1 +dtb_filename= early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -37,12 +39,11 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] @@ -63,7 +64,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -134,7 +135,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -184,7 +184,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -201,8 +200,8 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[5] @@ -214,8 +213,8 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[4] @@ -227,16 +226,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -255,8 +256,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -528,16 +529,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -559,8 +562,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -586,16 +589,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 +hit_latency=50000 is_top_level=false -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50000 size=1024 subblock_size=0 system=system @@ -611,16 +616,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=92 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=4194304 subblock_size=0 system=system @@ -645,9 +652,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -661,8 +669,9 @@ pio=system.membus.default [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=true -file= in_addr_map=true latency=30000 latency_var=0 @@ -682,17 +691,19 @@ system=system [system.realview.a9scu] type=A9SCU +clock=1 pio_addr=520093696 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268451840 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -736,16 +747,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=2 disks=system.cf0 io_shift=1 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=2 pci_dev=7 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.realview system=system config=system.iobus.master[8] @@ -758,8 +768,6 @@ amba_id=1315089 clock=41667 gic=system.realview.gic int_num=55 -max_backoff_delay=10000000 -min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 system=system @@ -770,17 +778,19 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268632064 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake +clock=1 fake_mem=true pio_addr=1073741824 -pio_latency=1000 +pio_latency=100000 pio_size=536870912 ret_bad_addr=false ret_data16=65535 @@ -794,6 +804,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic +clock=1 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -807,39 +818,43 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268513280 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268517376 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268521472 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=52 is_mouse=false pio_addr=268460032 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[5] @@ -847,21 +862,23 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=53 is_mouse=true pio_addr=268464128 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake +clock=1 fake_mem=false pio_addr=520101888 -pio_latency=1000 +pio_latency=100000 pio_size=4095 ret_bad_addr=false ret_data16=65535 @@ -880,23 +897,25 @@ gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268455936 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 @@ -907,9 +926,10 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl +clock=1 idreg=0 pio_addr=268435456 -pio_latency=1000 +pio_latency=100000 proc_id0=201326592 proc_id1=201327138 system=system @@ -918,11 +938,12 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 +clock=1 gic=system.realview.gic int_delay=100000 int_num=42 pio_addr=268529664 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] @@ -930,73 +951,80 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268492800 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=269357056 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=true pio_addr=268439552 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268488704 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=36 int_num1=36 pio_addr=268505088 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=37 int_num1=37 pio_addr=268509184 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[3] [system.realview.uart] type=Pl011 +clock=1 end_on_eot=false gic=system.realview.gic int_delay=100000 int_num=44 pio_addr=268472320 -pio_latency=1000 +pio_latency=100000 platform=system.realview system=system terminal=system.terminal @@ -1005,36 +1033,40 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268476416 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268480512 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268484608 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268500992 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[15] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 8990e0cd7..3e85e4166 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -4,8 +4,40 @@ warn: Sockets disabled, not accepting gdb connections warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -panic: Not supported on checker! - @ cycle 197694500 -[getInstPort:build/ARM/cpu/checker/cpu.hh, line 130] -Memory Usage: 355632 KBytes -Program aborted at cycle 197694500 +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: 6471379000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 6479236500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 6488789500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 6527432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6543641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 7089434000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 12809896500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 12854316500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 13169361500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 14424922500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 14474529500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 15519752500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 15669382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: LCD dual screen mode not supported +warn: 54391557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: 816692532000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +warn: 2486377425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2500398254500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2501706856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2523057678500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2523647855500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2529994034500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2530576345500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2531219324500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2531220454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 8772dfecb..5011d2336 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:40:00 -gem5 started Jul 27 2012 02:25:32 -gem5 executing on zizzer +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:35:22 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 2537929870500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index e2d527772..30432f4d1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538087 # Number of seconds simulated -sim_ticks 2538087368500 # Number of ticks simulated -final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.537930 # Number of seconds simulated +sim_ticks 2537929870500 # Number of ticks simulated +final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75387 # Simulator instruction rate (inst/s) -host_op_rate 96971 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3156986836 # Simulator tick rate (ticks/s) -host_mem_usage 390016 # Number of bytes of host memory used -host_seconds 803.96 # Real time elapsed on the host -sim_insts 60608307 # Number of instructions simulated -sim_ops 77960925 # Number of ops (including micro ops) simulated +host_inst_rate 52642 # Simulator instruction rate (inst/s) +host_op_rate 67714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2204296601 # Simulator tick rate (ticks/s) +host_mem_usage 387316 # Number of bytes of host memory used +host_seconds 1151.36 # Real time elapsed on the host +sim_insts 60609996 # Number of instructions simulated +sim_ops 77962726 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory +system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,153 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64372 # number of replacements -system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use -system.l2c.total_refs 1967256 # Total number of references to valid blocks. -system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy +system.l2c.replacements 64349 # number of replacements +system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use +system.l2c.total_refs 1931844 # Total number of references to valid blocks. +system.l2c.sampled_refs 129748 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.889201 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits -system.l2c.Writeback_hits::total 608347 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits -system.l2c.overall_hits::cpu.inst 978266 # number of overall hits -system.l2c.overall_hits::cpu.data 500583 # number of overall hits -system.l2c.overall_hits::total 1613985 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits +system.l2c.Writeback_hits::total 609524 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113135 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 502174 # number of demand (read+write) hits +system.l2c.demand_hits::total 1576793 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 84751 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 12176 # number of overall hits +system.l2c.overall_hits::cpu.inst 977692 # number of overall hits +system.l2c.overall_hits::cpu.data 502174 # number of overall hits +system.l2c.overall_hits::total 1576793 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu.data 10706 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23139 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2920 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133143 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143884 # number of demand (read+write) misses -system.l2c.demand_misses::total 156312 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses +system.l2c.demand_misses::cpu.data 143849 # number of demand (read+write) misses +system.l2c.demand_misses::total 156282 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 65 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses system.l2c.overall_misses::cpu.inst 12366 # number of overall misses -system.l2c.overall_misses::cpu.data 143884 # number of overall misses -system.l2c.overall_misses::total 156312 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3194000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 658485498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 561949499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1223688997 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 1101000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1101000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7073691498 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7073691498 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3194000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 658485498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7635640997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8297380495 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 3194000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 658485498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7635640997 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8297380495 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 123491 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11707 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 990632 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 398377 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1524207 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608347 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608347 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2947 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2947 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246090 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246090 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 123491 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11707 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 990632 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 644467 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1770297 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 123491 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11707 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 990632 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 644467 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1770297 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000494 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.026821 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015164 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985748 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.985748 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541261 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541261 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000494 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.223260 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088297 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000494 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.223260 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.088297 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52360.655738 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53249.676371 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52592.372391 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52943.754467 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 379.001721 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 379.001721 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 53106.190722 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53106.190722 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52360.655738 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53249.676371 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 53068.033951 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53082.172162 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52360.655738 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53249.676371 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 53068.033951 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53082.172162 # average overall miss latency +system.l2c.overall_misses::cpu.data 143849 # number of overall misses +system.l2c.overall_misses::total 156282 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8295680990 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1733075 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1733075 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.090176 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.090176 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53081.487247 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53081.487247 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,109 +216,109 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59128 # number of writebacks -system.l2c.writebacks::total 59128 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 67 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12359 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10625 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2905 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2905 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 59057 # number of writebacks +system.l2c.writebacks::total 59057 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133199 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133199 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12359 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143824 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156245 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12359 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143824 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156245 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2446000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507249999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 429957000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 939700999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116421500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116421500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156212 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5439851998 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5439851998 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2446000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 507249999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5869808998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6379552997 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2446000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 507249999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5869808998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6379552997 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5320000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745798500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166751118500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32081918388 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32081918388 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5320000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 198827716888 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 198833036888 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026671 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015120 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,9 +336,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15052368 # DTB read hits -system.cpu.checker.dtb.read_misses 7317 # DTB read misses -system.cpu.checker.dtb.write_hits 11296020 # DTB write hits +system.cpu.checker.dtb.read_hits 15052897 # DTB read hits +system.cpu.checker.dtb.read_misses 7321 # DTB read misses +system.cpu.checker.dtb.write_hits 11296410 # DTB write hits system.cpu.checker.dtb.write_misses 2195 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -345,13 +349,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15059685 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11298215 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15060218 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11298605 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26348388 # DTB hits -system.cpu.checker.dtb.misses 9512 # DTB misses -system.cpu.checker.dtb.accesses 26357900 # DTB accesses -system.cpu.checker.itb.inst_hits 61787075 # ITB inst hits +system.cpu.checker.dtb.hits 26349307 # DTB hits +system.cpu.checker.dtb.misses 9516 # DTB misses +system.cpu.checker.dtb.accesses 26358823 # DTB accesses +system.cpu.checker.itb.inst_hits 61788771 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -368,36 +372,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61791546 # ITB inst accesses -system.cpu.checker.itb.hits 61787075 # DTB hits +system.cpu.checker.itb.inst_accesses 61793242 # ITB inst accesses +system.cpu.checker.itb.hits 61788771 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61791546 # DTB accesses -system.cpu.checker.numCycles 78251500 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61793242 # DTB accesses +system.cpu.checker.numCycles 78253308 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51778790 # DTB read hits -system.cpu.dtb.read_misses 81353 # DTB read misses -system.cpu.dtb.write_hits 11881898 # DTB write hits -system.cpu.dtb.write_misses 18166 # DTB write misses +system.cpu.dtb.read_hits 51757171 # DTB read hits +system.cpu.dtb.read_misses 78755 # DTB read misses +system.cpu.dtb.write_hits 11824944 # DTB write hits +system.cpu.dtb.write_misses 17612 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8033 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7813 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860143 # DTB read accesses -system.cpu.dtb.write_accesses 11900064 # DTB write accesses +system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51835926 # DTB read accesses +system.cpu.dtb.write_accesses 11842556 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63660688 # DTB hits -system.cpu.dtb.misses 99519 # DTB misses -system.cpu.dtb.accesses 63760207 # DTB accesses -system.cpu.itb.inst_hits 13142674 # ITB inst hits -system.cpu.itb.inst_misses 12012 # ITB inst misses +system.cpu.dtb.hits 63582115 # DTB hits +system.cpu.dtb.misses 96367 # DTB misses +system.cpu.dtb.accesses 63678482 # DTB accesses +system.cpu.itb.inst_hits 13115769 # ITB inst hits +system.cpu.itb.inst_misses 12252 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -406,538 +410,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5318 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5204 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13154686 # ITB inst accesses -system.cpu.itb.hits 13142674 # DTB hits -system.cpu.itb.misses 12012 # DTB misses -system.cpu.itb.accesses 13154686 # DTB accesses -system.cpu.numCycles 487300785 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13128021 # ITB inst accesses +system.cpu.itb.hits 13115769 # DTB hits +system.cpu.itb.misses 12252 # DTB misses +system.cpu.itb.accesses 13128021 # DTB accesses +system.cpu.numCycles 487049956 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits +system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued -system.cpu.iq.rate 0.259577 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued +system.cpu.iq.rate 0.259310 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255111 # number of nop insts executed -system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed -system.cpu.iew.exec_branches 11930392 # Number of branches executed -system.cpu.iew.exec_stores 12393079 # Number of stores executed -system.cpu.iew.exec_rate 0.253002 # Inst execution rate -system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47523827 # num instructions producing a value -system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value +system.cpu.iew.exec_nop 226495 # number of nop insts executed +system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed +system.cpu.iew.exec_branches 11753944 # Number of branches executed +system.cpu.iew.exec_stores 12337385 # Number of stores executed +system.cpu.iew.exec_rate 0.252721 # Inst execution rate +system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47490892 # num instructions producing a value +system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758688 # Number of instructions committed -system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60760377 # Number of instructions committed +system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520186 # Number of memory references committed -system.cpu.commit.loads 15719769 # Number of loads committed -system.cpu.commit.membars 413359 # Number of memory barriers committed -system.cpu.commit.branches 10163898 # Number of branches committed +system.cpu.commit.refs 27521116 # Number of memory references committed +system.cpu.commit.loads 15720306 # Number of loads committed +system.cpu.commit.membars 413361 # Number of memory barriers committed +system.cpu.commit.branches 10025135 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. -system.cpu.commit.function_calls 996262 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69149691 # Number of committed integer instructions. +system.cpu.commit.function_calls 996276 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256700614 # The number of ROB reads -system.cpu.rob.rob_writes 209796185 # The number of ROB writes -system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608307 # Number of Instructions Simulated -system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated -system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558050325 # number of integer regfile reads -system.cpu.int_regfile_writes 90161621 # number of integer regfile writes -system.cpu.fp_regfile_reads 8290 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads -system.cpu.misc_regfile_writes 913390 # number of misc regfile writes -system.cpu.icache.replacements 991554 # number of replacements -system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use -system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits -system.cpu.icache.overall_hits::total 12061582 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses -system.cpu.icache.overall_misses::total 1076715 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked +system.cpu.rob.rob_reads 256258159 # The number of ROB reads +system.cpu.rob.rob_writes 209428063 # The number of ROB writes +system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60609996 # Number of Instructions Simulated +system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated +system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557221655 # number of integer regfile reads +system.cpu.int_regfile_writes 90065137 # number of integer regfile writes +system.cpu.fp_regfile_reads 8220 # number of floating regfile reads +system.cpu.fp_regfile_writes 2852 # number of floating regfile writes +system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads +system.cpu.misc_regfile_writes 913466 # number of misc regfile writes +system.cpu.icache.replacements 990831 # number of replacements +system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use +system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits +system.cpu.icache.overall_hits::total 12036161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses +system.cpu.icache.overall_misses::total 1075440 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84051 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991389 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991389 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991389 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991389 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991389 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991389 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12620585492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12620585492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12620585492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12620585492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075612 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12730.205290 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12730.205290 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643955 # number of replacements -system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use -system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor +system.cpu.dcache.replacements 645511 # number of replacements +system.cpu.dcache.tagsinuse 511.991460 # Cycle average of tags in use +system.cpu.dcache.total_refs 21729121 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 646023 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.635213 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50910000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991460 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908098 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13908098 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258651 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258651 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283641 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283641 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285792 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285792 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21166749 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21166749 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21166749 # number of overall hits -system.cpu.dcache.overall_hits::total 21166749 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 765710 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 765710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2993785 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2993785 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13813 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13813 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3759495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3759495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3759495 # number of overall misses -system.cpu.dcache.overall_misses::total 3759495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14876538000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14876538000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129441839072 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129441839072 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224157500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224157500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 359000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 359000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144318377072 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144318377072 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144318377072 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144318377072 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14673808 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14673808 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10252436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10252436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285808 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285808 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24926244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24926244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24926244 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24926244 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052182 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052182 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292007 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292007 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046437 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046437 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150825 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150825 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150825 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150825 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19428.423293 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19428.423293 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43236.852036 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43236.852036 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16228.009846 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16228.009846 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22437.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 22437.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38387.702889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38387.702889 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33577415 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7376000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7440 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285827 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21154214 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21154214 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21154214 # number of overall hits +system.cpu.dcache.overall_hits::total 21154214 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 767038 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 767038 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2998364 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2998364 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13689 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13689 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3765402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3765402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3765402 # number of overall misses +system.cpu.dcache.overall_misses::total 3765402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14912254500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14912254500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129601345080 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129601345080 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222071000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222071000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 314500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 314500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144513599580 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144513599580 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144513599580 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144513599580 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14666823 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14666823 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10252793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10252793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 299549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285840 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285840 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24919616 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24919616 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24919616 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24919616 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052297 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052297 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292444 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045699 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045699 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000045 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.151102 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.151102 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.151102 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.151102 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19441.350363 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19441.350363 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43224.019859 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43224.019859 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 34382405 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7145000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7505 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4581.266489 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25070.175439 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608347 # number of writebacks -system.cpu.dcache.writebacks::total 608347 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379574 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379574 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744878 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744878 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3124452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3124452 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3124452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3124452 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386136 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks +system.cpu.dcache.writebacks::total 609524 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -959,16 +963,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 7a79f323f..f00ea7875 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,13 +10,15 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +clock=1 +dtb_filename= early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -37,12 +39,11 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] @@ -63,7 +64,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -134,7 +135,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -168,16 +168,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -196,8 +198,8 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -469,16 +471,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -500,8 +504,8 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -576,7 +580,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -610,16 +613,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -638,8 +643,8 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -911,16 +916,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -942,8 +949,8 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -969,16 +976,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 +hit_latency=50000 is_top_level=false -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50000 size=1024 subblock_size=0 system=system @@ -994,16 +1003,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=92 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=4194304 subblock_size=0 system=system @@ -1028,9 +1039,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -1044,8 +1056,9 @@ pio=system.membus.default [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=true -file= in_addr_map=true latency=30000 latency_var=0 @@ -1065,17 +1078,19 @@ system=system [system.realview.a9scu] type=A9SCU +clock=1 pio_addr=520093696 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268451840 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1119,16 +1134,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=2 disks=system.cf0 io_shift=1 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=2 pci_dev=7 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.realview system=system config=system.iobus.master[8] @@ -1141,8 +1155,6 @@ amba_id=1315089 clock=41667 gic=system.realview.gic int_num=55 -max_backoff_delay=10000000 -min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 system=system @@ -1153,17 +1165,19 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268632064 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake +clock=1 fake_mem=true pio_addr=1073741824 -pio_latency=1000 +pio_latency=100000 pio_size=536870912 ret_bad_addr=false ret_data16=65535 @@ -1177,6 +1191,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic +clock=1 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -1190,39 +1205,43 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268513280 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268517376 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268521472 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=52 is_mouse=false pio_addr=268460032 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[5] @@ -1230,21 +1249,23 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=53 is_mouse=true pio_addr=268464128 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake +clock=1 fake_mem=false pio_addr=520101888 -pio_latency=1000 +pio_latency=100000 pio_size=4095 ret_bad_addr=false ret_data16=65535 @@ -1263,23 +1284,25 @@ gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268455936 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 @@ -1290,9 +1313,10 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl +clock=1 idreg=0 pio_addr=268435456 -pio_latency=1000 +pio_latency=100000 proc_id0=201326592 proc_id1=201327138 system=system @@ -1301,11 +1325,12 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 +clock=1 gic=system.realview.gic int_delay=100000 int_num=42 pio_addr=268529664 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] @@ -1313,73 +1338,80 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268492800 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=269357056 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=true pio_addr=268439552 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268488704 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=36 int_num1=36 pio_addr=268505088 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=37 int_num1=37 pio_addr=268509184 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[3] [system.realview.uart] type=Pl011 +clock=1 end_on_eot=false gic=system.realview.gic int_delay=100000 int_num=44 pio_addr=268472320 -pio_latency=1000 +pio_latency=100000 platform=system.realview system=system terminal=system.terminal @@ -1388,36 +1420,40 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268476416 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268480512 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268484608 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268500992 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[15] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 523f8a126..04178bb32 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -13,7 +13,6 @@ warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 904402304..4c598b20c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:40:00 -gem5 started Jul 27 2012 02:25:35 -gem5 executing on zizzer +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:18:35 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582310281500 because m5_exit instruction encountered +Exiting @ tick 2616878893500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 37534da99..8459be5ac 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.617165 # Number of seconds simulated -sim_ticks 2617165375500 # Number of ticks simulated -final_tick 2617165375500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616879 # Number of seconds simulated +sim_ticks 2616878893500 # Number of ticks simulated +final_tick 2616878893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89131 # Simulator instruction rate (inst/s) -host_op_rate 114699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3698456604 # Simulator tick rate (ticks/s) -host_mem_usage 391036 # Number of bytes of host memory used -host_seconds 707.64 # Real time elapsed on the host -sim_insts 63072219 # Number of instructions simulated -sim_ops 81165616 # Number of ops (including micro ops) simulated +host_inst_rate 63327 # Simulator instruction rate (inst/s) +host_op_rate 81506 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2627232906 # Simulator tick rate (ticks/s) +host_mem_usage 387740 # Number of bytes of host memory used +host_seconds 996.06 # Real time elapsed on the host +sim_insts 63077499 # Number of instructions simulated +sim_ops 81184436 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 397632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4358324 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 424512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5245616 # Number of bytes read from this memory +system.physmem.bytes_read::total 131538596 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 397632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 424512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4254848 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7283984 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6213 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6633 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15301853 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66482 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823766 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46280525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 73 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1665466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 162221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2004531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50265450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151949 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 162221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1625925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1151041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2783462 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1625925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46280525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 151949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1671963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 162221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3155573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53048913 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -29,310 +84,237 @@ system.realview.nvmem.bw_inst_read::total 171 # I system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 388160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4317812 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 434112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5305072 # Number of bytes read from this memory -system.physmem.bytes_read::total 131557540 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 388160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 434112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4272576 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7301712 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82918 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302149 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66759 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824043 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46275459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 148313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1649805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 165871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2027030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50267186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 148313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 165871 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1632520 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1150915 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2789931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1632520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46275459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 148313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1656300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 165871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3177945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53057118 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72943 # number of replacements -system.l2c.tagsinuse 53116.867697 # Cycle average of tags in use -system.l2c.total_refs 1971460 # Total number of references to valid blocks. -system.l2c.sampled_refs 138142 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.271257 # Average number of references to valid blocks. +system.l2c.replacements 72648 # number of replacements +system.l2c.tagsinuse 53148.103120 # Cycle average of tags in use +system.l2c.total_refs 1925510 # Total number of references to valid blocks. +system.l2c.sampled_refs 137845 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.968660 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37786.311031 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.267723 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000236 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4199.901742 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2938.535340 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 12.943065 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.004375 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4043.458423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4131.445760 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.576573 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000065 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064085 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.044838 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000197 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061698 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.063041 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.810499 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 37150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4929 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 329878 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 130970 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 97479 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7353 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 687490 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 235857 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1531106 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583482 # number of Writeback hits -system.l2c.Writeback_hits::total 583482 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 871 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 957 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1828 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 218 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 135 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 38368 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 68483 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106851 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 37150 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4929 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 329878 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 169338 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 97479 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7353 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 687490 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 304340 # number of demand (read+write) hits -system.l2c.demand_hits::total 1637957 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 37150 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4929 # number of overall hits -system.l2c.overall_hits::cpu0.inst 329878 # number of overall hits -system.l2c.overall_hits::cpu0.data 169338 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 97479 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7353 # number of overall hits -system.l2c.overall_hits::cpu1.inst 687490 # number of overall hits -system.l2c.overall_hits::cpu1.data 304340 # number of overall hits -system.l2c.overall_hits::total 1637957 # number of overall hits +system.l2c.occ_blocks::writebacks 37769.007236 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.653962 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.872957 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4238.981277 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2955.984743 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 14.025683 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4027.816705 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4137.760558 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.576309 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000056 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.064682 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045105 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061460 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.063137 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.810976 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 34723 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5721 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 398866 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166115 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 54785 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6733 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 615111 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 202597 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1484651 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 585034 # number of Writeback hits +system.l2c.Writeback_hits::total 585034 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1035 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 803 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1838 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48272 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58996 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107268 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 34723 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5721 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 398866 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214387 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 54785 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6733 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 615111 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 261593 # number of demand (read+write) hits +system.l2c.demand_hits::total 1591919 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 34723 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5721 # number of overall hits +system.l2c.overall_hits::cpu0.inst 398866 # number of overall hits +system.l2c.overall_hits::cpu0.data 214387 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 54785 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6733 # number of overall hits +system.l2c.overall_hits::cpu1.inst 615111 # number of overall hits +system.l2c.overall_hits::cpu1.data 261593 # number of overall hits +system.l2c.overall_hits::total 1591919 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5936 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6281 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6745 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6387 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25378 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4577 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5411 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9988 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 789 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 588 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1377 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 62166 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 78219 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140385 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6086 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6313 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6595 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6354 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25379 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5710 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4349 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 10059 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 787 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1376 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63248 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76888 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140136 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5936 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 68447 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6745 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 84606 # number of demand (read+write) misses -system.l2c.demand_misses::total 165763 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6086 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69561 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6595 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83242 # number of demand (read+write) misses +system.l2c.demand_misses::total 165515 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5936 # number of overall misses -system.l2c.overall_misses::cpu0.data 68447 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6745 # number of overall misses -system.l2c.overall_misses::cpu1.data 84606 # number of overall misses -system.l2c.overall_misses::total 165763 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 470500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 316492998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 329723499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 951500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 358728999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 335824498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1342303994 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 17317975 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 30484500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 47802475 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1723000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6877500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 8600500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3309650478 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4148841993 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7458492471 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 470500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 316492998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3639373977 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 951500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 52000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 358728999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4484666491 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8800796465 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 470500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 60000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 316492998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3639373977 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 951500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 52000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 358728999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4484666491 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8800796465 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 37159 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4930 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 335814 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 137251 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 97497 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7354 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 694235 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 242244 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1556484 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 583482 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 583482 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5448 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 6368 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11816 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1007 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 723 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1730 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 100534 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 146702 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247236 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 37159 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4930 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 335814 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 237785 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 97497 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7354 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 694235 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 388946 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1803720 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 37159 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4930 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 335814 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 237785 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 97497 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7354 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 694235 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 388946 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1803720 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000242 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000203 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.017676 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.045763 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000185 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000136 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009716 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.026366 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016305 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.840125 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.849717 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.845295 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783515 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.813278 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.795954 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.618358 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.533183 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.567818 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000242 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000203 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.017676 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.287852 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000185 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000136 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009716 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.217526 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091901 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000242 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000203 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.017676 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.287852 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000185 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000136 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009716 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.217526 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091901 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53317.553571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52495.382742 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52861.111111 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53184.432765 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52579.379677 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52892.426275 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3783.695652 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5633.801515 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4785.990689 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2183.776933 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11696.428571 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 6245.824256 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53238.916417 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53041.358148 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53128.841906 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 53317.553571 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 53170.686473 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52861.111111 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 53184.432765 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 53006.482885 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53092.647123 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52277.777778 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 53317.553571 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 53170.686473 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52861.111111 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 53184.432765 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 53006.482885 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53092.647123 # average overall miss latency +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6086 # number of overall misses +system.l2c.overall_misses::cpu0.data 69561 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6595 # number of overall misses +system.l2c.overall_misses::cpu1.data 83242 # number of overall misses +system.l2c.overall_misses::total 165515 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 469500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 164500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 324649999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 331479497 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 999000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 350737499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 334001499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1342501494 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 20494467 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27361999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 47856466 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1618500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6981500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 8600000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3367787487 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4076466989 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7444254476 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 469500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 164500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 324649999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3699266984 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 999000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 350737499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4410468488 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8786755970 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 469500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 164500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 324649999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3699266984 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 999000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 350737499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4410468488 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8786755970 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 34732 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 5724 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 404952 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 172428 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 54804 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6733 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 621706 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 208951 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1510030 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 585034 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 585034 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6745 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5152 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11897 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 997 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 755 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1752 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111520 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135884 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247404 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 34732 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 5724 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 404952 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 283948 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 54804 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6733 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 621706 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 344835 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1757434 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 34732 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 5724 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 404952 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 283948 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 54804 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6733 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 621706 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 344835 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1757434 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000259 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000524 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015029 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036612 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000347 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010608 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030409 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016807 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.846553 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.844138 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.845507 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.789368 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.780132 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.785388 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.567145 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.565836 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566426 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000259 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000524 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015029 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.244978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000347 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010608 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.241397 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.094180 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000259 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000524 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015029 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.244978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000347 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010608 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.241397 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.094180 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52166.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 54833.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53343.739566 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52507.444480 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52578.947368 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53182.334951 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52565.549103 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52898.124197 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3589.223643 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6291.561049 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4757.576896 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2056.543837 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11853.140917 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 6250 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53247.335679 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53018.247178 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53121.642376 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 54833.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53343.739566 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 53180.186944 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52578.947368 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53182.334951 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52983.691982 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53087.369544 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 54833.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53343.739566 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 53180.186944 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52578.947368 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53182.334951 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52983.691982 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53087.369544 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,180 +323,168 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66759 # number of writebacks -system.l2c.writebacks::total 66759 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 40 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 66482 # number of writebacks +system.l2c.writebacks::total 66482 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5932 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6241 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6738 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6363 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25303 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4577 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5411 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 9988 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 789 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 588 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1377 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 62166 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 78219 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140385 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6081 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6275 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6588 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6330 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25305 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5710 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4349 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10059 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 787 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 589 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1376 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63248 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76888 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140136 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5932 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 68407 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6738 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 84582 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165688 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6081 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69523 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6588 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83218 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165441 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5932 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 68407 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6738 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 84582 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165688 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6081 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69523 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6588 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83218 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165441 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 48000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 243887498 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 252067500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 733500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 276182999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 257217500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1030536997 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 183213000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 216585500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 399798500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31577000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23526500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 55103500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2553542997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3188267494 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5741810491 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 128000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 250196499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253577000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 768500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270011999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 255801000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1030842998 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 228550000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 174127500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 402677500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31488000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23619500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 55107500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2598832997 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3131766991 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5730599988 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 48000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 243887498 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2805610497 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 733500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 276182999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3445484994 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6772347488 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 128000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 250196499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2852409997 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 768500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 270011999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3387567991 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6761442986 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 48000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 243887498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2805610497 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 733500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 276182999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3445484994 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6772347488 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5576000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11089188500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 128000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 250196499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2852409997 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 768500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 270011999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3387567991 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6761442986 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5530000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12326566000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2170500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155938912500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167035847500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1148012499 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31165946489 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32313958988 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5576000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12237200999 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154699599000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167033865500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1153697499 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31138895772 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32292593271 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5530000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13480263499 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2170500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 187104858989 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 199349806488 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000203 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017665 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045471 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026267 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016257 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.840125 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.849717 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.845295 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783515 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.813278 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.795954 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618358 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.533183 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567818 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000203 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017665 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.287684 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.217465 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091859 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000242 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000203 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017665 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.287684 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000185 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000136 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009706 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.217465 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091859 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185838494772 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 199326458771 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036392 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030294 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016758 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.846553 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.844138 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.845507 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.789368 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.780132 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.785388 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567145 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565836 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566426 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.241327 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.094138 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241327 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.094138 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40388.960103 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40423.935251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40727.858238 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.058335 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.889669 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40027.883460 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.546261 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.054422 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40017.066086 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41076.199160 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40760.780552 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40900.455825 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40410.677291 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40410.900474 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40736.731792 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.269702 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.514601 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40031.563774 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.165184 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40101.018676 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40049.055233 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41089.568002 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40731.544467 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40893.132300 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -537,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7439931 # DTB read hits -system.cpu0.dtb.read_misses 24509 # DTB read misses -system.cpu0.dtb.write_hits 4439969 # DTB write hits -system.cpu0.dtb.write_misses 3332 # DTB write misses +system.cpu0.dtb.read_hits 9084291 # DTB read hits +system.cpu0.dtb.read_misses 36586 # DTB read misses +system.cpu0.dtb.write_hits 5291622 # DTB write hits +system.cpu0.dtb.write_misses 6420 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1349 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2157 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7464440 # DTB read accesses -system.cpu0.dtb.write_accesses 4443301 # DTB write accesses +system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9120877 # DTB read accesses +system.cpu0.dtb.write_accesses 5298042 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11879900 # DTB hits -system.cpu0.dtb.misses 27841 # DTB misses -system.cpu0.dtb.accesses 11907741 # DTB accesses -system.cpu0.itb.inst_hits 3552097 # ITB inst hits -system.cpu0.itb.inst_misses 3937 # ITB inst misses +system.cpu0.dtb.hits 14375913 # DTB hits +system.cpu0.dtb.misses 43006 # DTB misses +system.cpu0.dtb.accesses 14418919 # DTB accesses +system.cpu0.itb.inst_hits 4432740 # ITB inst hits +system.cpu0.itb.inst_misses 5766 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -566,538 +536,542 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1406 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 929 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1571 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 3556034 # ITB inst accesses -system.cpu0.itb.hits 3552097 # DTB hits -system.cpu0.itb.misses 3937 # DTB misses -system.cpu0.itb.accesses 3556034 # DTB accesses -system.cpu0.numCycles 63548405 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4438506 # ITB inst accesses +system.cpu0.itb.hits 4432740 # DTB hits +system.cpu0.itb.misses 5766 # DTB misses +system.cpu0.itb.accesses 4438506 # DTB accesses +system.cpu0.numCycles 73427885 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5090505 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 3902323 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 231356 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3310708 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2517095 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6227156 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4741082 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 330435 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3793257 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3054809 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 576022 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 23707 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 10651881 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 26843573 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5090505 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3093117 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 6356133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1209317 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 66372 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20477375 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 36616 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 72183 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 3550824 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 136175 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2156 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 38533087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.905766 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.281431 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 703344 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 32160 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12941361 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 33277959 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6227156 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3758153 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7819599 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1599392 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 82441 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 23494459 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 62047 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 92342 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 197 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4430967 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 174323 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2958 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 45648361 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.940627 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.320252 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 32183362 83.52% 83.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 497864 1.29% 84.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 649099 1.68% 86.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 569855 1.48% 87.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 713173 1.85% 89.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 461238 1.20% 91.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 562037 1.46% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 306432 0.80% 93.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2590027 6.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 37836918 82.89% 82.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 627349 1.37% 84.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 824369 1.81% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 703980 1.54% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 786046 1.72% 89.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 579188 1.27% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 721067 1.58% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 372009 0.81% 93.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3197435 7.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 38533087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.080104 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.422411 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 11016691 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20495843 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 5693231 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512184 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 815138 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 784502 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 52422 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 33794983 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 170156 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 815138 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 11512212 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6110309 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12456624 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 5662288 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1976516 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 32836773 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1958 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 434728 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1081609 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 147 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 32827027 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 148293172 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 148253410 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 39762 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 25938752 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6888275 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 379434 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 344458 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4684493 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6313022 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4948082 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 931233 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 932024 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 31038582 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 848484 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 31613010 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 68951 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5311616 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10469723 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 281141 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 38533087 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.820412 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.447904 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 45648361 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.084806 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.453206 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 13430389 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 23511343 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7018661 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 602696 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1085272 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 979924 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65913 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 41505511 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 215463 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1085272 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 14040409 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6748642 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14460031 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6960379 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2353628 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 40289777 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2418 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 473813 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1332712 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 81 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40678861 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 182059364 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 182024641 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34723 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31700311 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8978549 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 462421 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 418498 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5663645 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7939186 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5895346 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1154000 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1239736 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 38066358 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 944329 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 38270432 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 91181 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6810597 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14485199 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 255192 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 45648361 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.838375 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.464052 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 25332313 65.74% 65.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5318332 13.80% 79.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2653261 6.89% 86.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2120070 5.50% 91.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1758280 4.56% 96.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 743996 1.93% 98.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 416585 1.08% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 146664 0.38% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 43586 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 29755811 65.18% 65.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6343756 13.90% 79.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3236490 7.09% 86.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2520305 5.52% 91.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2106581 4.61% 96.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 935116 2.05% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 513948 1.13% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 183643 0.40% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52711 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 38533087 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 45648361 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 17185 1.90% 1.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.05% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 711308 78.54% 80.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 176706 19.51% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27042 2.53% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 464 0.04% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 835512 78.03% 80.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207702 19.40% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 39793 0.13% 0.13% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 18975009 60.02% 60.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 42063 0.13% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 2 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 627 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7818427 24.73% 85.02% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4737084 14.98% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22977707 60.04% 60.18% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 50299 0.13% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9565645 24.99% 85.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5623724 14.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 31613010 # Type of FU issued -system.cpu0.iq.rate 0.497463 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 905651 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028648 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 102751361 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 37203152 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 29110459 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 9929 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5392 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4352 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 32473546 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5322 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 253493 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 38270432 # Type of FU issued +system.cpu0.iq.rate 0.521198 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070720 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.027978 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 123385364 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45829388 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35329971 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8465 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4764 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3918 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 39284390 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 323676 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1084760 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3550 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10332 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 476904 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1511954 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3775 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13508 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 616210 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1893731 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4858 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149507 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5450 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 815138 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4299477 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 104449 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 31945570 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 72737 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6313022 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4948082 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 576088 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 33936 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17434 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10332 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 115531 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 108245 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 223776 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 31278568 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7699224 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 334442 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1085272 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4652854 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 126877 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 39130245 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 91852 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7939186 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5895346 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 610877 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 49621 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17387 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13508 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 175421 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 130280 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 305701 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37846246 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9402583 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 424186 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 58504 # number of nop insts executed -system.cpu0.iew.exec_refs 12394115 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4158454 # Number of branches executed -system.cpu0.iew.exec_stores 4694891 # Number of stores executed -system.cpu0.iew.exec_rate 0.492201 # Inst execution rate -system.cpu0.iew.wb_sent 31120630 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 29114811 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 15418480 # num instructions producing a value -system.cpu0.iew.wb_consumers 29202336 # num instructions consuming a value +system.cpu0.iew.exec_nop 119558 # number of nop insts executed +system.cpu0.iew.exec_refs 14967440 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4996145 # Number of branches executed +system.cpu0.iew.exec_stores 5564857 # Number of stores executed +system.cpu0.iew.exec_rate 0.515421 # Inst execution rate +system.cpu0.iew.wb_sent 37628600 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35333889 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18696932 # num instructions producing a value +system.cpu0.iew.wb_consumers 35648829 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.458152 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.527988 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.481205 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.524475 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5043051 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 567343 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 195875 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 37746791 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.699150 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.656907 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6705821 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 689137 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 265687 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 44599494 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.717911 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.673991 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 27673007 73.31% 73.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5099673 13.51% 86.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1632700 4.33% 91.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 816219 2.16% 93.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 659263 1.75% 95.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 376754 1.00% 96.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 343613 0.91% 96.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 170043 0.45% 97.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 975519 2.58% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32451965 72.76% 72.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6077972 13.63% 86.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1948934 4.37% 90.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1034999 2.32% 93.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 805126 1.81% 94.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 506776 1.14% 96.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 402342 0.90% 96.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 201836 0.45% 97.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1169544 2.62% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 37746791 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 19900047 # Number of instructions committed -system.cpu0.commit.committedOps 26390683 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 44599494 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24278814 # Number of instructions committed +system.cpu0.commit.committedOps 32018477 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 9699440 # Number of memory references committed -system.cpu0.commit.loads 5228262 # Number of loads committed -system.cpu0.commit.membars 194354 # Number of memory barriers committed -system.cpu0.commit.branches 3620828 # Number of branches committed -system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 23422561 # Number of committed integer instructions. -system.cpu0.commit.function_calls 422942 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 975519 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11706368 # Number of memory references committed +system.cpu0.commit.loads 6427232 # Number of loads committed +system.cpu0.commit.membars 234590 # Number of memory barriers committed +system.cpu0.commit.branches 4349138 # Number of branches committed +system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 28284672 # Number of committed integer instructions. +system.cpu0.commit.function_calls 500279 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1169544 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 67501483 # The number of ROB reads -system.cpu0.rob.rob_writes 63684069 # The number of ROB writes -system.cpu0.timesIdled 366948 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25015318 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5170100782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 19875493 # Number of Instructions Simulated -system.cpu0.committedOps 26366129 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 19875493 # Number of Instructions Simulated -system.cpu0.cpi 3.197325 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.197325 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.312761 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.312761 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 145756307 # number of integer regfile reads -system.cpu0.int_regfile_writes 28747856 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4243 # number of floating regfile reads -system.cpu0.fp_regfile_writes 404 # number of floating regfile writes -system.cpu0.misc_regfile_reads 38262536 # number of misc regfile reads -system.cpu0.misc_regfile_writes 444175 # number of misc regfile writes -system.cpu0.icache.replacements 335591 # number of replacements -system.cpu0.icache.tagsinuse 511.578004 # Cycle average of tags in use -system.cpu0.icache.total_refs 3187209 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 336103 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.482834 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7275076000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.578004 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999176 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999176 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3187209 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3187209 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3187209 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3187209 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3187209 # number of overall hits -system.cpu0.icache.overall_hits::total 3187209 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 363477 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 363477 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 363477 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 363477 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 363477 # number of overall misses -system.cpu0.icache.overall_misses::total 363477 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5925752494 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5925752494 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5925752494 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5925752494 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5925752494 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5925752494 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 3550686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 3550686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 3550686 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 3550686 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 3550686 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 3550686 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102368 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.102368 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102368 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.102368 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102368 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.102368 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16302.964133 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16302.964133 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16302.964133 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16302.964133 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1276494 # number of cycles access was blocked +system.cpu0.rob.rob_reads 81269635 # The number of ROB reads +system.cpu0.rob.rob_writes 78536158 # The number of ROB writes +system.cpu0.timesIdled 427323 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27779524 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5160286096 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24198072 # Number of Instructions Simulated +system.cpu0.committedOps 31937735 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24198072 # Number of Instructions Simulated +system.cpu0.cpi 3.034452 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.034452 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.329549 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.329549 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 176614966 # number of integer regfile reads +system.cpu0.int_regfile_writes 35097459 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3370 # number of floating regfile reads +system.cpu0.fp_regfile_writes 922 # number of floating regfile writes +system.cpu0.misc_regfile_reads 47564974 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527822 # number of misc regfile writes +system.cpu0.icache.replacements 405114 # number of replacements +system.cpu0.icache.tagsinuse 511.561657 # Cycle average of tags in use +system.cpu0.icache.total_refs 3991755 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 405626 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.840974 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 7272099000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.561657 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3991755 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3991755 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3991755 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3991755 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3991755 # number of overall hits +system.cpu0.icache.overall_hits::total 3991755 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 439070 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 439070 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 439070 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 439070 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 439070 # number of overall misses +system.cpu0.icache.overall_misses::total 439070 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7078203996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7078203996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7078203996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7078203996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7078203996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7078203996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4430825 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4430825 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4430825 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4430825 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4430825 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4430825 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099094 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.099094 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099094 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.099094 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099094 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.099094 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16120.900986 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16120.900986 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16120.900986 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16120.900986 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1491997 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 156 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8182.653846 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8776.452941 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 27366 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 27366 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 27366 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 27366 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 27366 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 27366 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 336111 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 336111 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 336111 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 336111 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 336111 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 336111 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4556806494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4556806494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4556806494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4556806494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4556806494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4556806494 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8394000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8394000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8394000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8394000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.094661 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.094661 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.094661 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13557.445290 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33429 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 33429 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 33429 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 33429 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 33429 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 33429 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405641 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 405641 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 405641 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 405641 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 405641 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 405641 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5425368997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5425368997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5425368997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5425368997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5425368997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5425368997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8328000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8328000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8328000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8328000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091550 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.091550 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.091550 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13374.804315 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 225959 # number of replacements -system.cpu0.dcache.tagsinuse 476.340528 # Cycle average of tags in use -system.cpu0.dcache.total_refs 7674381 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 226327 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.908376 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 51455000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.340528 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.930353 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.930353 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4719087 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4719087 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2610456 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2610456 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 155489 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 155489 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152427 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 152427 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7329543 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7329543 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7329543 # number of overall hits -system.cpu0.dcache.overall_hits::total 7329543 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 331165 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 331165 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1441313 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1441313 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8607 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8607 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7989 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7989 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1772478 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1772478 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1772478 # number of overall misses -system.cpu0.dcache.overall_misses::total 1772478 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6024148000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6024148000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68192376390 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 68192376390 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105659500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 105659500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 91795500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 91795500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 74216524390 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 74216524390 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 74216524390 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 74216524390 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5050252 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5050252 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4051769 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4051769 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 164096 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 164096 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160416 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 160416 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9102021 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9102021 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9102021 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9102021 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.065574 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.065574 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.355724 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.355724 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049802 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049802 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.194735 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.194735 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.194735 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.194735 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18190.774991 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18190.774991 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47312.676976 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 47312.676976 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12275.996282 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12275.996282 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11490.236575 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11490.236575 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41871.619501 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41871.619501 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 5649995 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1774500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1210 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 93 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4669.417355 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 19080.645161 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275935 # number of replacements +system.cpu0.dcache.tagsinuse 476.765535 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9559328 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276447 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.579243 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 51426000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 476.765535 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.931183 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.931183 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5939119 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5939119 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3227738 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3227738 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174834 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174834 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171593 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171593 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9166857 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9166857 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9166857 # number of overall hits +system.cpu0.dcache.overall_hits::total 9166857 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 401304 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 401304 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1595717 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1595717 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8980 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8980 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7781 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7781 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1997021 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1997021 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1997021 # number of overall misses +system.cpu0.dcache.overall_misses::total 1997021 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7282608500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 7282608500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71716653343 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71716653343 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113510500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 113510500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 89966000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 89966000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 78999261843 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 78999261843 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 78999261843 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 78999261843 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6340423 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6340423 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4823455 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4823455 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183814 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183814 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179374 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179374 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11163878 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11163878 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11163878 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11163878 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063293 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063293 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330824 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330824 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048854 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048854 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043379 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043379 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178882 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178882 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178882 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178882 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18147.360854 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18147.360854 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44943.215710 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44943.215710 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12640.367483 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12640.367483 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11562.267061 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11562.267061 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39558.553387 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39558.553387 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39558.553387 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39558.553387 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7775987 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1662000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1508 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 96 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5156.490053 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 17312.500000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 209818 # number of writebacks -system.cpu0.dcache.writebacks::total 209818 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 177491 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 177491 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1323875 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1323875 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 700 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1501366 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1501366 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1501366 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1501366 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 153674 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 153674 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 117438 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 117438 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7907 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7907 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7979 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7979 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 271112 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 271112 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 271112 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 271112 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2311816775 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2311816775 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4408331005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4408331005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70347504 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70347504 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 66656537 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66656537 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6720147780 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6720147780 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6720147780 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6720147780 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12100601500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12100601500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1292553399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1292553399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13393154899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13393154899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030429 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030429 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048185 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.048185 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049739 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049739 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029786 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029786 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15043.642874 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15043.642874 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37537.517711 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37537.517711 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8896.864045 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8896.864045 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8353.996365 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8353.996365 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256111 # number of writebacks +system.cpu0.dcache.writebacks::total 256111 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211639 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 211639 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1464558 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1464558 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 529 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 529 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1676197 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1676197 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1676197 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1676197 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189665 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189665 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131159 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131159 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7774 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7774 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320824 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320824 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320824 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320824 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2812273446 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2812273446 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4676498504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4676498504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79208005 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79208005 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65545528 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65545528 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7488771950 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7488771950 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7488771950 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7488771950 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13454662000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13454662000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1295219899 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1295219899 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14749881899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14749881899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029914 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029914 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027192 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027192 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043340 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043340 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028738 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028738 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14827.582559 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14827.582559 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35655.185721 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35655.185721 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9372.619217 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9372.619217 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8431.377412 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8431.377412 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1107,27 +1081,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 45088968 # DTB read hits -system.cpu1.dtb.read_misses 60619 # DTB read misses -system.cpu1.dtb.write_hits 7938217 # DTB write hits -system.cpu1.dtb.write_misses 15813 # DTB write misses +system.cpu1.dtb.read_hits 43437526 # DTB read hits +system.cpu1.dtb.read_misses 44897 # DTB read misses +system.cpu1.dtb.write_hits 7020721 # DTB write hits +system.cpu1.dtb.write_misses 11707 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2729 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3748 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2363 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 4220 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 316 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 727 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 45149587 # DTB read accesses -system.cpu1.dtb.write_accesses 7954030 # DTB write accesses +system.cpu1.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43482423 # DTB read accesses +system.cpu1.dtb.write_accesses 7032428 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 53027185 # DTB hits -system.cpu1.dtb.misses 76432 # DTB misses -system.cpu1.dtb.accesses 53103617 # DTB accesses -system.cpu1.itb.inst_hits 10093689 # ITB inst hits -system.cpu1.itb.inst_misses 8052 # ITB inst misses +system.cpu1.dtb.hits 50458247 # DTB hits +system.cpu1.dtb.misses 56604 # DTB misses +system.cpu1.dtb.accesses 50514851 # DTB accesses +system.cpu1.itb.inst_hits 9182577 # ITB inst hits +system.cpu1.itb.inst_misses 6227 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1136,542 +1110,538 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1586 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2426 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1649 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10101741 # ITB inst accesses -system.cpu1.itb.hits 10093689 # DTB hits -system.cpu1.itb.misses 8052 # DTB misses -system.cpu1.itb.accesses 10101741 # DTB accesses -system.cpu1.numCycles 430376404 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9188804 # ITB inst accesses +system.cpu1.itb.hits 9182577 # DTB hits +system.cpu1.itb.misses 6227 # DTB misses +system.cpu1.itb.accesses 9188804 # DTB accesses +system.cpu1.numCycles 420121858 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 11102078 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 9036479 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 529963 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7542756 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 6181694 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9688118 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7965440 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 469703 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6737081 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5659691 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 958293 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 57467 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 24500240 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 78456444 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 11102078 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 7139987 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 16800094 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5031478 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 107954 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 84138717 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 105572 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 161210 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10091008 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 896138 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 4286 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 129269647 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.735584 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.091589 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 834304 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 51249 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 22081738 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71759711 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9688118 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6493995 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15294978 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4586075 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 88967 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 80951772 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5897 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 52783 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 142728 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9180482 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 856181 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3761 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 121742103 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.711584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.060066 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 112479856 87.01% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 952035 0.74% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1186228 0.92% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2188812 1.69% 90.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1732150 1.34% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 728800 0.56% 92.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2428875 1.88% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 531185 0.41% 94.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 7041706 5.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 106455334 87.44% 87.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 840434 0.69% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1014558 0.83% 88.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2075766 1.71% 90.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1622971 1.33% 92.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 608124 0.50% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2270082 1.86% 94.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 458736 0.38% 94.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6396098 5.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 129269647 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.025796 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.182297 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 26260600 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 83914684 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15106265 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 652780 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3335318 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1450901 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 116510 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 88966869 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 389379 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3335318 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 27931781 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34696050 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 44327698 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 14003132 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4975668 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 82212740 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 21319 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 759400 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3532141 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33925 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 86942184 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 378153831 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 378105448 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 48383 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 55944710 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 30997473 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 570448 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 494970 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9410070 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15640035 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 9547074 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1284923 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1813164 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 74425843 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1310750 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 98630822 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 132915 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 20366425 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 57377380 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 269048 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 129269647 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.762985 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.495609 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 121742103 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.023060 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.170807 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23726811 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 80682083 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13746238 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 564864 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3022107 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1180909 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102849 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 80937245 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 340282 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3022107 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 25270664 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33976360 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 42200569 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12677087 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4595316 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74576204 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 20275 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 711120 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3286160 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33636 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 79110058 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 343673709 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 343614714 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58995 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50196787 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28913271 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 480316 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 419400 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8402630 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14031046 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8540774 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1078770 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1484758 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 67259946 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1207834 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 91753969 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 112690 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18841154 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53684147 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 287920 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 121742103 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.753675 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.492082 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 94766617 73.31% 73.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10139907 7.84% 81.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 5158815 3.99% 85.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4427747 3.43% 88.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 11055431 8.55% 97.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2157635 1.67% 98.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1155512 0.89% 99.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 316791 0.25% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 91192 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 89993106 73.92% 73.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9114072 7.49% 81.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4553910 3.74% 85.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4000568 3.29% 88.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10707495 8.80% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1970764 1.62% 98.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1044074 0.86% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 282783 0.23% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75331 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 129269647 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 121742103 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 39597 0.49% 0.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1008 0.01% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7696421 95.46% 95.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 325487 4.04% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28572 0.36% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 997 0.01% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7569076 95.94% 96.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 290938 3.69% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 326092 0.33% 0.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 43501050 44.10% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 69634 0.07% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 16 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1718 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 46384595 47.03% 91.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 8347697 8.46% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313802 0.34% 0.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39340328 42.88% 43.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61412 0.07% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1696 0.00% 43.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44630775 48.64% 91.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7405942 8.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 98630822 # Type of FU issued -system.cpu1.iq.rate 0.229173 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 8062513 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.081744 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 334791339 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 96121166 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 62008917 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11647 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6672 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5500 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 106361230 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6013 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 441985 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 91753969 # Type of FU issued +system.cpu1.iq.rate 0.218398 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7889583 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.085986 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 313294010 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 87318397 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55594578 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14739 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6796 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 99322053 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7697 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 360033 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4452276 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7115 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 25628 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1723414 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4037305 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4422 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 18147 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1519259 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 32221586 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1050708 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965400 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1049364 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3335318 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26012639 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 434151 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 75941872 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 151121 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15640035 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 9547074 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 940187 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 96009 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 15502 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 25628 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 268769 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 233332 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 502101 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 95691641 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 45532774 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2939181 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3022107 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25590166 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 410250 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68573370 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132853 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14031046 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8540774 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 897358 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 85617 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 14991 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 18147 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 245880 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 172266 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 418146 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 88914677 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43821187 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2839292 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 205279 # number of nop insts executed -system.cpu1.iew.exec_refs 53793996 # number of memory reference insts executed -system.cpu1.iew.exec_branches 8312135 # Number of branches executed -system.cpu1.iew.exec_stores 8261222 # Number of stores executed -system.cpu1.iew.exec_rate 0.222344 # Inst execution rate -system.cpu1.iew.wb_sent 94462198 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 62014417 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 34071785 # num instructions producing a value -system.cpu1.iew.wb_consumers 60996509 # num instructions consuming a value +system.cpu1.iew.exec_nop 105590 # number of nop insts executed +system.cpu1.iew.exec_refs 51148287 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7278596 # Number of branches executed +system.cpu1.iew.exec_stores 7327100 # Number of stores executed +system.cpu1.iew.exec_rate 0.211640 # Inst execution rate +system.cpu1.iew.wb_sent 87750200 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55601374 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30754041 # num instructions producing a value +system.cpu1.iew.wb_consumers 54503523 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.144093 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.558586 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.132346 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.564258 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 20655264 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1041702 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 445913 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 125990352 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.435949 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.396620 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 18816555 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 919914 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 368704 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 118768431 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.415231 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.371949 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 106643597 84.64% 84.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9506424 7.55% 92.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2528568 2.01% 94.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1530167 1.21% 95.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1425850 1.13% 96.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 711007 0.56% 97.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1063442 0.84% 97.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 518210 0.41% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 2063087 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 101503583 85.46% 85.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8523872 7.18% 92.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2201888 1.85% 94.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1303888 1.10% 95.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1288434 1.08% 96.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 587085 0.49% 97.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 997227 0.84% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 495127 0.42% 98.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1867327 1.57% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 125990352 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 43322553 # Number of instructions committed -system.cpu1.commit.committedOps 54925314 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 118768431 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38949066 # Number of instructions committed +system.cpu1.commit.committedOps 49316340 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 19011419 # Number of memory references committed -system.cpu1.commit.loads 11187759 # Number of loads committed -system.cpu1.commit.membars 242679 # Number of memory barriers committed -system.cpu1.commit.branches 7019269 # Number of branches committed -system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 48550450 # Number of committed integer instructions. -system.cpu1.commit.function_calls 633769 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 2063087 # number cycles where commit BW limit reached +system.cpu1.commit.refs 17015256 # Number of memory references committed +system.cpu1.commit.loads 9993741 # Number of loads committed +system.cpu1.commit.membars 202364 # Number of memory barriers committed +system.cpu1.commit.branches 6138465 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43706861 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556456 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1867327 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 198211439 # The number of ROB reads -system.cpu1.rob.rob_writes 154591902 # The number of ROB writes -system.cpu1.timesIdled 1579473 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 301106757 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4803892671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 43196726 # Number of Instructions Simulated -system.cpu1.committedOps 54799487 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 43196726 # Number of Instructions Simulated -system.cpu1.cpi 9.963172 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 9.963172 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.100370 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.100370 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 429674423 # number of integer regfile reads -system.cpu1.int_regfile_writes 64872300 # number of integer regfile writes -system.cpu1.fp_regfile_reads 3964 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1982 # number of floating regfile writes -system.cpu1.misc_regfile_reads 101230364 # number of misc regfile reads -system.cpu1.misc_regfile_writes 513642 # number of misc regfile writes -system.cpu1.icache.replacements 694768 # number of replacements -system.cpu1.icache.tagsinuse 498.623067 # Cycle average of tags in use -system.cpu1.icache.total_refs 9339186 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 695280 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.432266 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 75785789000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.623067 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.973873 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.973873 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 9339186 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9339186 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9339186 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9339186 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9339186 # number of overall hits -system.cpu1.icache.overall_hits::total 9339186 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 751768 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 751768 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 751768 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 751768 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 751768 # number of overall misses -system.cpu1.icache.overall_misses::total 751768 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11830653994 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11830653994 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11830653994 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11830653994 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11830653994 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11830653994 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10090954 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10090954 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10090954 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10090954 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10090954 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10090954 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074499 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.074499 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074499 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.074499 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074499 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.074499 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15737.107717 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15737.107717 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15737.107717 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15737.107717 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1257996 # number of cycles access was blocked +system.cpu1.rob.rob_reads 183919327 # The number of ROB reads +system.cpu1.rob.rob_writes 139377269 # The number of ROB writes +system.cpu1.timesIdled 1519096 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 298379755 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4813097636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38879427 # Number of Instructions Simulated +system.cpu1.committedOps 49246701 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38879427 # Number of Instructions Simulated +system.cpu1.cpi 10.805763 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.805763 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092543 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092543 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 397952991 # number of integer regfile reads +system.cpu1.int_regfile_writes 58412580 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4851 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2298 # number of floating regfile writes +system.cpu1.misc_regfile_reads 91535746 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429838 # number of misc regfile writes +system.cpu1.icache.replacements 621848 # number of replacements +system.cpu1.icache.tagsinuse 498.728003 # Cycle average of tags in use +system.cpu1.icache.total_refs 8507924 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 622360 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.670422 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 75775782000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.728003 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974078 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974078 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8507924 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8507924 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8507924 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8507924 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8507924 # number of overall hits +system.cpu1.icache.overall_hits::total 8507924 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 672506 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 672506 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 672506 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 672506 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 672506 # number of overall misses +system.cpu1.icache.overall_misses::total 672506 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10595189995 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10595189995 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10595189995 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10595189995 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10595189995 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10595189995 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9180430 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9180430 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9180430 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9180430 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9180430 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9180430 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073254 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.073254 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073254 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.073254 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073254 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.073254 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15754.788797 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15754.788797 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15754.788797 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15754.788797 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15754.788797 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15754.788797 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1171995 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 215 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 180 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 5851.144186 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6511.083333 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 56459 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 56459 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 56459 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 56459 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 56459 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 56459 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 695309 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 695309 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 695309 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 695309 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 695309 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 695309 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9048159496 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 9048159496 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9048159496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 9048159496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9048159496 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 9048159496 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3211500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068904 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.068904 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.068904 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13013.148824 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50115 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 50115 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 50115 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 50115 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 50115 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 50115 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622391 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 622391 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 622391 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 622391 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 622391 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 622391 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8107387995 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8107387995 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8107387995 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8107387995 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8107387995 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8107387995 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3209000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3209000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3209000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3209000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067795 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.067795 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.067795 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13026.197350 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13026.197350 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13026.197350 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13026.197350 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13026.197350 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13026.197350 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 413009 # number of replacements -system.cpu1.dcache.tagsinuse 487.394187 # Cycle average of tags in use -system.cpu1.dcache.total_refs 14990250 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 413521 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.250275 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 71474582000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.394187 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951942 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951942 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 9825576 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9825576 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4872589 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4872589 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123205 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 123205 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 119861 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 119861 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 14698165 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 14698165 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 14698165 # number of overall hits -system.cpu1.dcache.overall_hits::total 14698165 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 478795 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 478795 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1745196 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1745196 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14728 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14728 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10805 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10805 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2223991 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2223991 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2223991 # number of overall misses -system.cpu1.dcache.overall_misses::total 2223991 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9322511500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9322511500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 69699331710 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 69699331710 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 175643000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 175643000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94845500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 94845500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 79021843210 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 79021843210 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 79021843210 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 79021843210 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10304371 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10304371 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6617785 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6617785 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137933 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 137933 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130666 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 130666 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16922156 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16922156 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16922156 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16922156 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046465 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046465 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263713 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.263713 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106776 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106776 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.082692 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.082692 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131425 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.131425 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131425 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.131425 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19470.778726 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19470.778726 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39937.824582 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39937.824582 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11925.787615 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11925.787615 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8777.926886 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8777.926886 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 35531.548109 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 35531.548109 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 31184009 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5513500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4502.455819 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 33213.855422 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 364389 # number of replacements +system.cpu1.dcache.tagsinuse 487.304887 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13108660 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 364763 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.937472 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 71473892000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.304887 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951767 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951767 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8608527 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8608527 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4253626 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4253626 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105088 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 105088 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100770 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100770 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12862153 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12862153 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12862153 # number of overall hits +system.cpu1.dcache.overall_hits::total 12862153 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 413506 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 413506 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1597634 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1597634 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14294 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14294 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10915 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10915 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2011140 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2011140 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2011140 # number of overall misses +system.cpu1.dcache.overall_misses::total 2011140 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8210381000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8210381000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66162469729 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 66162469729 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166851000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 166851000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95119500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 95119500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 74372850729 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 74372850729 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 74372850729 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 74372850729 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9022033 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9022033 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5851260 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5851260 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119382 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 119382 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 111685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14873293 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14873293 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14873293 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14873293 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045833 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045833 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273041 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273041 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119733 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119733 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097730 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097730 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135218 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135218 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135218 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135218 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19855.530512 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19855.530512 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41412.782733 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41412.782733 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11672.799776 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11672.799776 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8714.567109 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8714.567109 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 36980.444290 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 36980.444290 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29857004 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5566500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6768 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4411.495863 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33133.928571 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 373664 # number of writebacks -system.cpu1.dcache.writebacks::total 373664 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211355 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 211355 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1568704 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1568704 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1302 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1302 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1780059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1780059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1780059 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1780059 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267440 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 267440 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 176492 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 176492 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13426 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13426 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10800 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10800 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 443932 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 443932 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 443932 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 443932 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4040609191 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4040609191 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5818534579 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5818534579 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 114031007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 114031007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61142007 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61142007 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9859143770 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9859143770 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9859143770 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9859143770 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170666816500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170666816500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40957900116 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40957900116 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 211624716616 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 211624716616 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025954 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025954 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097337 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097337 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.082653 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.082653 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026234 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026234 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15108.469904 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15108.469904 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32967.695867 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32967.695867 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8493.297110 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8493.297110 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5661.296944 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5661.296944 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 328923 # number of writebacks +system.cpu1.dcache.writebacks::total 328923 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180962 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 180962 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1434656 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1434656 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1453 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1615618 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1615618 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1615618 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1615618 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 232544 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 232544 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162978 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162978 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12841 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12841 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 395522 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 395522 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 395522 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 395522 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3583215887 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3583215887 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5542320073 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5542320073 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104521007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104521007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61064509 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61064509 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9125535960 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9125535960 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9125535960 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9125535960 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169307109000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169307109000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40930247169 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40930247169 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210237356169 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210237356169 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025775 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025775 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107562 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107562 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097677 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097677 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026593 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026593 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15408.765167 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15408.765167 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34006.553480 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34006.553480 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8139.631415 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8139.631415 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5597.626639 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5597.626639 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1693,18 +1663,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323290279244 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323290279244 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1322950372611 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1322950372611 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 36101 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43807 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 61677 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53930 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 9e6ff3218..e428e398a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,13 +10,15 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +clock=1 +dtb_filename= early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -37,12 +39,11 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] @@ -63,7 +64,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -134,7 +135,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -168,16 +168,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -196,8 +198,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -469,16 +471,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -500,8 +504,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -527,16 +531,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 +hit_latency=50000 is_top_level=false -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50000 size=1024 subblock_size=0 system=system @@ -552,16 +558,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=92 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=4194304 subblock_size=0 system=system @@ -586,9 +594,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -602,8 +611,9 @@ pio=system.membus.default [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=true -file= in_addr_map=true latency=30000 latency_var=0 @@ -623,17 +633,19 @@ system=system [system.realview.a9scu] type=A9SCU +clock=1 pio_addr=520093696 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268451840 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -677,16 +689,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=2 disks=system.cf0 io_shift=1 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=2 pci_dev=7 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.realview system=system config=system.iobus.master[8] @@ -699,8 +710,6 @@ amba_id=1315089 clock=41667 gic=system.realview.gic int_num=55 -max_backoff_delay=10000000 -min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 system=system @@ -711,17 +720,19 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268632064 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake +clock=1 fake_mem=true pio_addr=1073741824 -pio_latency=1000 +pio_latency=100000 pio_size=536870912 ret_bad_addr=false ret_data16=65535 @@ -735,6 +746,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic +clock=1 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -748,39 +760,43 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268513280 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268517376 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268521472 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=52 is_mouse=false pio_addr=268460032 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[5] @@ -788,21 +804,23 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=53 is_mouse=true pio_addr=268464128 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake +clock=1 fake_mem=false pio_addr=520101888 -pio_latency=1000 +pio_latency=100000 pio_size=4095 ret_bad_addr=false ret_data16=65535 @@ -821,23 +839,25 @@ gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268455936 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 @@ -848,9 +868,10 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl +clock=1 idreg=0 pio_addr=268435456 -pio_latency=1000 +pio_latency=100000 proc_id0=201326592 proc_id1=201327138 system=system @@ -859,11 +880,12 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 +clock=1 gic=system.realview.gic int_delay=100000 int_num=42 pio_addr=268529664 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] @@ -871,73 +893,80 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268492800 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=269357056 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=true pio_addr=268439552 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268488704 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=36 int_num1=36 pio_addr=268505088 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=37 int_num1=37 pio_addr=268509184 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[3] [system.realview.uart] type=Pl011 +clock=1 end_on_eot=false gic=system.realview.gic int_delay=100000 int_num=44 pio_addr=268472320 -pio_latency=1000 +pio_latency=100000 platform=system.realview system=system terminal=system.terminal @@ -946,36 +975,40 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268476416 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268480512 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268484608 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268500992 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[15] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index ab2c07a7f..affb69ad6 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -13,7 +13,6 @@ warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c9f3d2864..304caa505 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:40:00 -gem5 started Jul 27 2012 02:23:14 -gem5 executing on zizzer +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:10:34 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503329223500 because m5_exit instruction encountered +Exiting @ tick 2537929870500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 5e48f5c5e..5eb2280fd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538087 # Number of seconds simulated -sim_ticks 2538087368500 # Number of ticks simulated -final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.537930 # Number of seconds simulated +sim_ticks 2537929870500 # Number of ticks simulated +final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89486 # Simulator instruction rate (inst/s) -host_op_rate 115106 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3747392596 # Simulator tick rate (ticks/s) -host_mem_usage 390008 # Number of bytes of host memory used -host_seconds 677.29 # Real time elapsed on the host -sim_insts 60608307 # Number of instructions simulated -sim_ops 77960925 # Number of ops (including micro ops) simulated +host_inst_rate 62423 # Simulator instruction rate (inst/s) +host_op_rate 80294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2613828720 # Simulator tick rate (ticks/s) +host_mem_usage 387060 # Number of bytes of host memory used +host_seconds 970.96 # Real time elapsed on the host +sim_insts 60609996 # Number of instructions simulated +sim_ops 77962726 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory +system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,153 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64372 # number of replacements -system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use -system.l2c.total_refs 1967256 # Total number of references to valid blocks. -system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy +system.l2c.replacements 64349 # number of replacements +system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use +system.l2c.total_refs 1931844 # Total number of references to valid blocks. +system.l2c.sampled_refs 129748 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.889201 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits -system.l2c.Writeback_hits::total 608347 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits -system.l2c.overall_hits::cpu.inst 978266 # number of overall hits -system.l2c.overall_hits::cpu.data 500583 # number of overall hits -system.l2c.overall_hits::total 1613985 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits +system.l2c.Writeback_hits::total 609524 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113135 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 502174 # number of demand (read+write) hits +system.l2c.demand_hits::total 1576793 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 84751 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 12176 # number of overall hits +system.l2c.overall_hits::cpu.inst 977692 # number of overall hits +system.l2c.overall_hits::cpu.data 502174 # number of overall hits +system.l2c.overall_hits::total 1576793 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu.data 10706 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23139 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2920 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133143 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143884 # number of demand (read+write) misses -system.l2c.demand_misses::total 156312 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses +system.l2c.demand_misses::cpu.data 143849 # number of demand (read+write) misses +system.l2c.demand_misses::total 156282 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 65 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses system.l2c.overall_misses::cpu.inst 12366 # number of overall misses -system.l2c.overall_misses::cpu.data 143884 # number of overall misses -system.l2c.overall_misses::total 156312 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3194000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 658485498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 561949499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1223688997 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 1101000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1101000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7073691498 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7073691498 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3194000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 658485498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7635640997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8297380495 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 3194000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 658485498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7635640997 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8297380495 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 123491 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11707 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 990632 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 398377 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1524207 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608347 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608347 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2947 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2947 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246090 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246090 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 123491 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11707 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 990632 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 644467 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1770297 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 123491 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11707 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 990632 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 644467 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1770297 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000494 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.026821 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015164 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985748 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.985748 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541261 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541261 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000494 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.223260 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088297 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000494 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.223260 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.088297 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52360.655738 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53249.676371 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52592.372391 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52943.754467 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 379.001721 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 379.001721 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 53106.190722 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53106.190722 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52360.655738 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53249.676371 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 53068.033951 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53082.172162 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52360.655738 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53249.676371 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 53068.033951 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53082.172162 # average overall miss latency +system.l2c.overall_misses::cpu.data 143849 # number of overall misses +system.l2c.overall_misses::total 156282 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8295680990 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1733075 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1733075 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.090176 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.090176 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53081.487247 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53081.487247 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,109 +216,109 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59128 # number of writebacks -system.l2c.writebacks::total 59128 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 67 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12359 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10625 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2905 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2905 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 59057 # number of writebacks +system.l2c.writebacks::total 59057 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133199 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133199 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12359 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143824 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156245 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12359 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143824 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156245 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2446000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507249999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 429957000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 939700999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116421500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116421500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156212 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5439851998 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5439851998 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2446000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 507249999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5869808998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6379552997 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2446000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 507249999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5869808998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6379552997 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5320000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745798500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166751118500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32081918388 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32081918388 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5320000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 198827716888 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 198833036888 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026671 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015120 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,27 +336,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51778790 # DTB read hits -system.cpu.dtb.read_misses 81353 # DTB read misses -system.cpu.dtb.write_hits 11881898 # DTB write hits -system.cpu.dtb.write_misses 18166 # DTB write misses +system.cpu.dtb.read_hits 51757171 # DTB read hits +system.cpu.dtb.read_misses 78755 # DTB read misses +system.cpu.dtb.write_hits 11824944 # DTB write hits +system.cpu.dtb.write_misses 17612 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4472 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4306 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860143 # DTB read accesses -system.cpu.dtb.write_accesses 11900064 # DTB write accesses +system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51835926 # DTB read accesses +system.cpu.dtb.write_accesses 11842556 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63660688 # DTB hits -system.cpu.dtb.misses 99519 # DTB misses -system.cpu.dtb.accesses 63760207 # DTB accesses -system.cpu.itb.inst_hits 13142674 # ITB inst hits -system.cpu.itb.inst_misses 12012 # ITB inst misses +system.cpu.dtb.hits 63582115 # DTB hits +system.cpu.dtb.misses 96367 # DTB misses +system.cpu.dtb.accesses 63678482 # DTB accesses +system.cpu.itb.inst_hits 13115769 # ITB inst hits +system.cpu.itb.inst_misses 12252 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -361,538 +365,538 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2661 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2604 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13154686 # ITB inst accesses -system.cpu.itb.hits 13142674 # DTB hits -system.cpu.itb.misses 12012 # DTB misses -system.cpu.itb.accesses 13154686 # DTB accesses -system.cpu.numCycles 487300785 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13128021 # ITB inst accesses +system.cpu.itb.hits 13115769 # DTB hits +system.cpu.itb.misses 12252 # DTB misses +system.cpu.itb.accesses 13128021 # DTB accesses +system.cpu.numCycles 487049956 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits +system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued -system.cpu.iq.rate 0.259577 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued +system.cpu.iq.rate 0.259310 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255111 # number of nop insts executed -system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed -system.cpu.iew.exec_branches 11930392 # Number of branches executed -system.cpu.iew.exec_stores 12393079 # Number of stores executed -system.cpu.iew.exec_rate 0.253002 # Inst execution rate -system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47523827 # num instructions producing a value -system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value +system.cpu.iew.exec_nop 226495 # number of nop insts executed +system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed +system.cpu.iew.exec_branches 11753944 # Number of branches executed +system.cpu.iew.exec_stores 12337385 # Number of stores executed +system.cpu.iew.exec_rate 0.252721 # Inst execution rate +system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47490892 # num instructions producing a value +system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758688 # Number of instructions committed -system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60760377 # Number of instructions committed +system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520186 # Number of memory references committed -system.cpu.commit.loads 15719769 # Number of loads committed -system.cpu.commit.membars 413359 # Number of memory barriers committed -system.cpu.commit.branches 10163898 # Number of branches committed +system.cpu.commit.refs 27521116 # Number of memory references committed +system.cpu.commit.loads 15720306 # Number of loads committed +system.cpu.commit.membars 413361 # Number of memory barriers committed +system.cpu.commit.branches 10025135 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. -system.cpu.commit.function_calls 996262 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69149691 # Number of committed integer instructions. +system.cpu.commit.function_calls 996276 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256700614 # The number of ROB reads -system.cpu.rob.rob_writes 209796185 # The number of ROB writes -system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608307 # Number of Instructions Simulated -system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated -system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558050322 # number of integer regfile reads -system.cpu.int_regfile_writes 90161620 # number of integer regfile writes -system.cpu.fp_regfile_reads 8290 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads -system.cpu.misc_regfile_writes 913390 # number of misc regfile writes -system.cpu.icache.replacements 991554 # number of replacements -system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use -system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits -system.cpu.icache.overall_hits::total 12061582 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses -system.cpu.icache.overall_misses::total 1076715 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked +system.cpu.rob.rob_reads 256258159 # The number of ROB reads +system.cpu.rob.rob_writes 209428063 # The number of ROB writes +system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60609996 # Number of Instructions Simulated +system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated +system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557221649 # number of integer regfile reads +system.cpu.int_regfile_writes 90065135 # number of integer regfile writes +system.cpu.fp_regfile_reads 8220 # number of floating regfile reads +system.cpu.fp_regfile_writes 2852 # number of floating regfile writes +system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads +system.cpu.misc_regfile_writes 913466 # number of misc regfile writes +system.cpu.icache.replacements 990831 # number of replacements +system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use +system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits +system.cpu.icache.overall_hits::total 12036161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses +system.cpu.icache.overall_misses::total 1075440 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84051 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991389 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991389 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991389 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991389 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991389 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991389 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12620585492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12620585492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12620585492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12620585492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075612 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12730.205290 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12730.205290 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643955 # number of replacements -system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use -system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor +system.cpu.dcache.replacements 645511 # number of replacements +system.cpu.dcache.tagsinuse 511.991460 # Cycle average of tags in use +system.cpu.dcache.total_refs 21729121 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 646023 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.635213 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50910000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991460 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908098 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13908098 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258651 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258651 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283641 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283641 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285792 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285792 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21166749 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21166749 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21166749 # number of overall hits -system.cpu.dcache.overall_hits::total 21166749 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 765710 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 765710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2993785 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2993785 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13813 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13813 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3759495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3759495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3759495 # number of overall misses -system.cpu.dcache.overall_misses::total 3759495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14876538000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14876538000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129441839072 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129441839072 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224157500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224157500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 359000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 359000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144318377072 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144318377072 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144318377072 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144318377072 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14673808 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14673808 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10252436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10252436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285808 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285808 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24926244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24926244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24926244 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24926244 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052182 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052182 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292007 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292007 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046437 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046437 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150825 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150825 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150825 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150825 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19428.423293 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19428.423293 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43236.852036 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43236.852036 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16228.009846 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16228.009846 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22437.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 22437.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38387.702889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38387.702889 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33577415 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7376000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7440 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285827 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21154214 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21154214 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21154214 # number of overall hits +system.cpu.dcache.overall_hits::total 21154214 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 767038 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 767038 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2998364 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2998364 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13689 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13689 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3765402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3765402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3765402 # number of overall misses +system.cpu.dcache.overall_misses::total 3765402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14912254500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14912254500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129601345080 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129601345080 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222071000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222071000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 314500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 314500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144513599580 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144513599580 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144513599580 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144513599580 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14666823 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14666823 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10252793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10252793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 299549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285840 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285840 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24919616 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24919616 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24919616 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24919616 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052297 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052297 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292444 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045699 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045699 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000045 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.151102 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.151102 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.151102 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.151102 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19441.350363 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19441.350363 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43224.019859 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43224.019859 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 34382405 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7145000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7505 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4581.266489 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25070.175439 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608347 # number of writebacks -system.cpu.dcache.writebacks::total 608347 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379574 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379574 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744878 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744878 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3124452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3124452 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3124452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3124452 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386136 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks +system.cpu.dcache.writebacks::total 609524 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -914,16 +918,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |