diff options
Diffstat (limited to 'tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini')
| -rw-r--r-- | tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini | 135 |
1 files changed, 127 insertions, 8 deletions
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 76f5cbc67..8fe2ef1b7 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -14,13 +14,14 @@ children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false hypervisor_addr=1099243257856 -hypervisor_bin=/dist/m5/system/binaries/q_new.bin +hypervisor_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin hypervisor_desc=system.hypervisor_desc hypervisor_desc_addr=133446500352 -hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin +hypervisor_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin init_param=0 kernel= kernel_addr_check=true @@ -34,17 +35,22 @@ multi_thread=false num_work_ids=16 nvram=system.nvram nvram_addr=133429198848 -nvram_bin=/dist/m5/system/binaries/nvram1 +nvram_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1 openboot_addr=1099243716608 -openboot_bin=/dist/m5/system/binaries/openboot_new.bin +openboot_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 partition_desc=system.partition_desc partition_desc_addr=133445976064 -partition_desc_bin=/dist/m5/system/binaries/1up-md.bin -readfile=/z/stever/hg/gem5/tests/halt.sh +partition_desc_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin +readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh reset_addr=1099243192320 -reset_bin=/dist/m5/system/binaries/reset_new.bin +reset_bin=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin rom=system.rom symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -57,8 +63,12 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=100 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463 req_size=16 resp_size=16 @@ -80,6 +90,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -96,6 +107,9 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 profile=0 progress_interval=0 simpoint_start_insts= @@ -144,8 +158,12 @@ voltage_domain=system.voltage_domain type=MmDisk children=image clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 image=system.disk0.image +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=134217728000 pio_latency=200 system=system @@ -163,7 +181,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/disk.s10hw2 +image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2 read_only=true [system.dvfs_handler] @@ -179,11 +197,15 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=60 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 range=133446500352:133446508543 port=system.membus.master[5] @@ -195,9 +217,13 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 response_latency=2 use_default_range=false width=16 @@ -208,9 +234,14 @@ slave=system.bridge.master type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -224,8 +255,12 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=0 pio_latency=200 pio_size=8 @@ -244,11 +279,15 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=60 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 range=133429198848:133429207039 port=system.membus.master[4] @@ -257,11 +296,15 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=60 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 range=133445976064:133445984255 port=system.membus.master[6] @@ -270,11 +313,15 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=60 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 range=1048576:68157439 port=system.membus.master[7] @@ -283,11 +330,15 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=60 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 range=2147483648:2415919103 port=system.membus.master[8] @@ -296,11 +347,15 @@ type=SimpleMemory bandwidth=0.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=60 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 range=1099243192320:1099251580927 port=system.membus.master[3] @@ -314,8 +369,12 @@ system=system [system.t1000.fake_clk] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=644245094400 pio_latency=200 pio_size=4294967296 @@ -332,8 +391,12 @@ pio=system.iobus.master[0] [system.t1000.fake_jbi] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=549755813888 pio_latency=200 pio_size=4294967296 @@ -350,8 +413,12 @@ pio=system.iobus.master[11] [system.t1000.fake_l2_1] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=725849473024 pio_latency=200 pio_size=8 @@ -368,8 +435,12 @@ pio=system.iobus.master[2] [system.t1000.fake_l2_2] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=725849473088 pio_latency=200 pio_size=8 @@ -386,8 +457,12 @@ pio=system.iobus.master[3] [system.t1000.fake_l2_3] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=725849473152 pio_latency=200 pio_size=8 @@ -404,8 +479,12 @@ pio=system.iobus.master[4] [system.t1000.fake_l2_4] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=725849473216 pio_latency=200 pio_size=8 @@ -422,8 +501,12 @@ pio=system.iobus.master[5] [system.t1000.fake_l2esr_1] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=734439407616 pio_latency=200 pio_size=8 @@ -440,8 +523,12 @@ pio=system.iobus.master[6] [system.t1000.fake_l2esr_2] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=734439407680 pio_latency=200 pio_size=8 @@ -458,8 +545,12 @@ pio=system.iobus.master[7] [system.t1000.fake_l2esr_3] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=734439407744 pio_latency=200 pio_size=8 @@ -476,8 +567,12 @@ pio=system.iobus.master[8] [system.t1000.fake_l2esr_4] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=734439407808 pio_latency=200 pio_size=8 @@ -494,8 +589,12 @@ pio=system.iobus.master[9] [system.t1000.fake_membnks] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=648540061696 pio_latency=200 pio_size=16384 @@ -512,8 +611,12 @@ pio=system.iobus.master[1] [system.t1000.fake_ssi] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=1095216660480 pio_latency=200 pio_size=268435456 @@ -538,7 +641,11 @@ port=3456 [system.t1000.htod] type=DumbTOD clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=1099255906296 pio_latency=200 system=system @@ -548,7 +655,11 @@ pio=system.membus.master[1] [system.t1000.hvuart] type=Uart8250 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=1099255955456 pio_latency=200 platform=system.t1000 @@ -559,7 +670,11 @@ pio=system.iobus.master[13] [system.t1000.iob] type=Iob clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_latency=2 platform=system.t1000 system=system @@ -576,7 +691,11 @@ port=3456 [system.t1000.puart0] type=Uart8250 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=2000000000 +p_state_clk_gate_min=2 pio_addr=133412421632 pio_latency=200 platform=system.t1000 |