diff options
Diffstat (limited to 'tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json')
| -rw-r--r-- | tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json | 563 |
1 files changed, 341 insertions, 222 deletions
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json index d144b080a..00d9dd136 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json @@ -9,12 +9,16 @@ "range": "1099243192320:1099251580927", "latency": 60, "name": "rom", + "p_state_clk_gate_min": 2, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 2000000000, "path": "system.rom", "null": false, "type": "SimpleMemory", @@ -37,6 +41,9 @@ "role": "SLAVE" }, "name": "bridge", + "p_state_clk_gate_min": 2, + "p_state_clk_gate_bins": 20, + "cxx_class": "Bridge", "req_size": 16, "clk_domain": "system.clk_domain", "delay": 100, @@ -45,12 +52,14 @@ "peer": "system.iobus.slave[0]", "role": "MASTER" }, - "cxx_class": "Bridge", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "path": "system.bridge", "resp_size": 16, "type": "Bridge" }, "iobus": { + "forward_latency": 1, "slave": { "peer": [ "system.bridge.master" @@ -58,7 +67,9 @@ "role": "SLAVE" }, "name": "iobus", - "forward_latency": 1, + "p_state_clk_gate_min": 2, + "p_state_clk_gate_bins": 20, + "cxx_class": "NoncoherentXBar", "clk_domain": "system.clk_domain", "width": 16, "eventq_index": 0, @@ -83,7 +94,8 @@ "role": "MASTER" }, "response_latency": 2, - "cxx_class": "NoncoherentXBar", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "path": "system.iobus", "type": "NoncoherentXBar", "use_default_range": false, @@ -92,110 +104,130 @@ "t1000": { "htod": { "name": "htod", + "p_state_clk_gate_min": 2, "pio": { "peer": "system.membus.master[1]", "role": "SLAVE" }, - "time": "Thu Jan 1 00:00:00 2009", + "p_state_clk_gate_bins": 20, + "cxx_class": "DumbTOD", "pio_latency": 200, "clk_domain": "system.clk_domain", "system": "system", "eventq_index": 0, - "cxx_class": "DumbTOD", + "time": "Thu Jan 1 00:00:00 2009", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "path": "system.t1000.htod", "pio_addr": 1099255906296, "type": "DumbTOD" }, "puart0": { "name": "puart0", + "p_state_clk_gate_min": 2, "pio": { "peer": "system.iobus.master[12]", "role": "SLAVE" }, + "p_state_clk_gate_bins": 20, + "cxx_class": "Uart8250", "pio_latency": 200, "clk_domain": "system.clk_domain", "system": "system", "terminal": "system.t1000.pterm", "platform": "system.t1000", "eventq_index": 0, - "cxx_class": "Uart8250", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "path": "system.t1000.puart0", "pio_addr": 133412421632, "type": "Uart8250" }, "fake_membnks": { - "system": "system", - "ret_data8": 255, - "name": "fake_membnks", - "warn_access": "", "pio": { "peer": "system.iobus.master[1]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 16384, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, "ret_data64": 0, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_membnks", "pio_addr": 648540061696, + "update_data": false, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_membnks", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_membnks", + "ret_bad_addr": false, + "pio_size": 16384, + "p_state_clk_gate_bins": 20 }, "cxx_class": "T1000", "fake_jbi": { - "system": "system", - "ret_data8": 255, - "name": "fake_jbi", - "warn_access": "", "pio": { "peer": "system.iobus.master[11]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 4294967296, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, "ret_data64": 18446744073709551615, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_jbi", "pio_addr": 549755813888, + "update_data": false, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_jbi", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_jbi", + "ret_bad_addr": false, + "pio_size": 4294967296, + "p_state_clk_gate_bins": 20 }, "intrctrl": "system.intrctrl", "fake_l2esr_2": { - "system": "system", - "ret_data8": 255, - "name": "fake_l2esr_2", - "warn_access": "", "pio": { "peer": "system.iobus.master[7]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": true, "ret_data64": 0, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_l2esr_2", "pio_addr": 734439407680, + "update_data": true, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_l2esr_2", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_l2esr_2", + "ret_bad_addr": false, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, "system": "system", "eventq_index": 0, @@ -212,100 +244,116 @@ }, "type": "T1000", "fake_l2_4": { - "system": "system", - "ret_data8": 255, - "name": "fake_l2_4", - "warn_access": "", "pio": { "peer": "system.iobus.master[5]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": true, "ret_data64": 1, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_l2_4", "pio_addr": 725849473216, + "update_data": true, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_l2_4", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_l2_4", + "ret_bad_addr": false, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, "fake_l2_1": { - "system": "system", - "ret_data8": 255, - "name": "fake_l2_1", - "warn_access": "", "pio": { "peer": "system.iobus.master[2]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": true, "ret_data64": 1, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_l2_1", "pio_addr": 725849473024, + "update_data": true, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_l2_1", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_l2_1", + "ret_bad_addr": false, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, "fake_l2_2": { - "system": "system", - "ret_data8": 255, - "name": "fake_l2_2", - "warn_access": "", "pio": { "peer": "system.iobus.master[3]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": true, "ret_data64": 1, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_l2_2", "pio_addr": 725849473088, + "update_data": true, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_l2_2", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_l2_2", + "ret_bad_addr": false, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, "fake_l2_3": { - "system": "system", - "ret_data8": 255, - "name": "fake_l2_3", - "warn_access": "", "pio": { "peer": "system.iobus.master[4]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": true, "ret_data64": 1, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_l2_3", "pio_addr": 725849473152, + "update_data": true, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_l2_3", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_l2_3", + "ret_bad_addr": false, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, "pterm": { "name": "pterm", @@ -321,171 +369,203 @@ "path": "system.t1000", "iob": { "name": "iob", + "p_state_clk_gate_min": 2, "pio": { "peer": "system.membus.master[0]", "role": "SLAVE" }, + "p_state_clk_gate_bins": 20, + "cxx_class": "Iob", "pio_latency": 2, "clk_domain": "system.clk_domain", "system": "system", "platform": "system.t1000", "eventq_index": 0, - "cxx_class": "Iob", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "path": "system.t1000.iob", "type": "Iob" }, "hvuart": { "name": "hvuart", + "p_state_clk_gate_min": 2, "pio": { "peer": "system.iobus.master[13]", "role": "SLAVE" }, + "p_state_clk_gate_bins": 20, + "cxx_class": "Uart8250", "pio_latency": 200, "clk_domain": "system.clk_domain", "system": "system", "terminal": "system.t1000.hterm", "platform": "system.t1000", "eventq_index": 0, - "cxx_class": "Uart8250", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "path": "system.t1000.hvuart", "pio_addr": 1099255955456, "type": "Uart8250" }, "name": "t1000", "fake_l2esr_3": { - "system": "system", - "ret_data8": 255, - "name": "fake_l2esr_3", - "warn_access": "", "pio": { "peer": "system.iobus.master[8]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": true, "ret_data64": 0, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_l2esr_3", "pio_addr": 734439407744, + "update_data": true, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_l2esr_3", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_l2esr_3", + "ret_bad_addr": false, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, "fake_ssi": { - "system": "system", - "ret_data8": 255, - "name": "fake_ssi", - "warn_access": "", "pio": { "peer": "system.iobus.master[10]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 268435456, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, "ret_data64": 18446744073709551615, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_ssi", "pio_addr": 1095216660480, + "update_data": false, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_ssi", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_ssi", + "ret_bad_addr": false, + "pio_size": 268435456, + "p_state_clk_gate_bins": 20 }, "fake_l2esr_1": { - "system": "system", - "ret_data8": 255, - "name": "fake_l2esr_1", - "warn_access": "", "pio": { "peer": "system.iobus.master[6]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": true, "ret_data64": 0, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_l2esr_1", "pio_addr": 734439407616, + "update_data": true, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_l2esr_1", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_l2esr_1", + "ret_bad_addr": false, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, "fake_l2esr_4": { - "system": "system", - "ret_data8": 255, - "name": "fake_l2esr_4", - "warn_access": "", "pio": { "peer": "system.iobus.master[9]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": true, "ret_data64": 0, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_l2esr_4", "pio_addr": 734439407808, + "update_data": true, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_l2esr_4", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_l2esr_4", + "ret_bad_addr": false, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, "fake_clk": { - "system": "system", - "ret_data8": 255, - "name": "fake_clk", - "warn_access": "", "pio": { "peer": "system.iobus.master[0]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 4294967296, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, "ret_data64": 18446744073709551615, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.t1000.fake_clk", "pio_addr": 644245094400, + "update_data": false, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.t1000.fake_clk", + "ret_data16": 65535, + "ret_data8": 255, + "name": "fake_clk", + "ret_bad_addr": false, + "pio_size": 4294967296, + "p_state_clk_gate_bins": 20 } }, "partition_desc_addr": 133445976064, "symbolfile": "", - "readfile": "/z/stever/hg/gem5/tests/halt.sh", + "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh", + "thermal_model": null, "hypervisor_addr": 1099243257856, "mem_ranges": [ "1048576:68157439", "2147483648:2415919103" ], "cxx_class": "SparcSystem", + "work_begin_cpu_id_exit": -1, "load_offset": 0, - "reset_bin": "/dist/m5/system/binaries/reset_new.bin", - "openboot_addr": 1099243716608, + "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin", "work_end_ckpt_count": 0, + "work_begin_exit_count": 0, + "openboot_addr": 1099243716608, + "p_state_clk_gate_min": 2, "nvram_addr": 133429198848, "memories": [ "system.hypervisor_desc", @@ -500,12 +580,16 @@ "range": "133445976064:133445984255", "latency": 60, "name": "partition_desc", + "p_state_clk_gate_min": 2, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 2000000000, "path": "system.partition_desc", "null": false, "type": "SimpleMemory", @@ -532,12 +616,16 @@ "range": "133446500352:133446508543", "latency": 60, "name": "hypervisor_desc", + "p_state_clk_gate_min": 2, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 2000000000, "path": "system.hypervisor_desc", "null": false, "type": "SimpleMemory", @@ -548,49 +636,44 @@ "in_addr_map": true }, "membus": { - "default": { - "peer": "system.membus.badaddr_responder.pio", - "role": "MASTER" - }, - "slave": { - "peer": [ - "system.system_port", - "system.cpu.icache_port", - "system.cpu.dcache_port" - ], - "role": "SLAVE" - }, - "name": "membus", + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", "badaddr_responder": { - "system": "system", - "ret_data8": 255, - "name": "badaddr_responder", - "warn_access": "", "pio": { "peer": "system.membus.default", "role": "SLAVE" }, - "ret_bad_addr": true, - "pio_latency": 200, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, "ret_data64": 18446744073709551615, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.membus.badaddr_responder", "pio_addr": 0, + "update_data": false, + "warn_access": "", + "pio_latency": 200, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 2, + "ret_data32": 4294967295, + "path": "system.membus.badaddr_responder", + "ret_data16": 65535, + "ret_data8": 255, + "name": "badaddr_responder", + "ret_bad_addr": true, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, - "snoop_filter": null, "forward_latency": 4, "clk_domain": "system.clk_domain", - "system": "system", "width": 16, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "master": { "peer": [ "system.t1000.iob.pio", @@ -605,24 +688,42 @@ ], "role": "MASTER" }, - "response_latency": 2, - "cxx_class": "CoherentXBar", + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 2, + "snoop_filter": null, "path": "system.membus", "snoop_response_latency": 4, - "type": "CoherentXBar", - "use_default_range": false, - "frontend_latency": 3 + "name": "membus", + "default": { + "peer": "system.membus.badaddr_responder.pio", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "use_default_range": false }, "nvram": { "range": "133429198848:133429207039", "latency": 60, "name": "nvram", + "p_state_clk_gate_min": 2, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 2000000000, "path": "system.nvram", "null": false, "type": "SimpleMemory", @@ -633,7 +734,8 @@ "in_addr_map": true }, "eventq_index": 0, - "work_begin_cpu_id_exit": -1, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "dvfs_handler": { "enable": false, "name": "dvfs_handler", @@ -646,8 +748,8 @@ "type": "DVFSHandler" }, "work_end_exit_count": 0, - "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin", - "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin", + "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin", + "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin", "voltage_domain": { "name": "voltage_domain", "eventq_index": 0, @@ -669,12 +771,16 @@ "range": "1048576:68157439", "latency": 60, "name": "physmem0", + "p_state_clk_gate_min": 2, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 2000000000, "path": "system.physmem0", "null": false, "type": "SimpleMemory", @@ -688,12 +794,16 @@ "range": "2147483648:2415919103", "latency": 60, "name": "physmem1", + "p_state_clk_gate_min": 2, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 2000000000, "path": "system.physmem1", "null": false, "type": "SimpleMemory", @@ -705,9 +815,9 @@ } ], "work_cpus_ckpt_count": 0, - "work_begin_exit_count": 0, + "thermal_components": [], "path": "system", - "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin", + "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin", "cpu_clk_domain": { "name": "cpu_clk_domain", "clock": [ @@ -721,12 +831,12 @@ "type": "SrcClockDomain", "domain_id": -1 }, - "nvram_bin": "/dist/m5/system/binaries/nvram1", + "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1", "mem_mode": "atomic", "name": "system", "init_param": 0, "type": "SparcSystem", - "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin", + "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin", "load_addr_mask": 1099511627775, "cpu": { "do_statistics_insts": true, @@ -751,6 +861,8 @@ "width": 1, "checker": null, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "do_quiesce": true, "type": "AtomicSimpleCPU", "fastmem": false, @@ -759,6 +871,8 @@ "peer": "system.membus.slave[1]", "role": "MASTER" }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 2, "interrupts": [ { "eventq_index": 0, @@ -819,10 +933,12 @@ }, "disk0": { "name": "disk0", + "p_state_clk_gate_min": 2, "pio": { "peer": "system.iobus.master[14]", "role": "SLAVE" }, + "p_state_clk_gate_bins": 20, "image": { "read_only": false, "name": "image", @@ -834,7 +950,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.disk0.image.child", - "image_file": "/dist/m5/system/disks/disk.s10hw2", + "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2", "type": "RawDiskImage" }, "path": "system.disk0.image", @@ -842,17 +958,20 @@ "type": "CowDiskImage", "table_size": 65536 }, + "cxx_class": "MmDisk", "pio_latency": 200, "clk_domain": "system.clk_domain", "system": "system", "eventq_index": 0, - "cxx_class": "MmDisk", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 2000000000, "path": "system.disk0", "pio_addr": 134217728000, "type": "MmDisk" }, "multi_thread": false, "reset_addr": 1099243192320, + "p_state_clk_gate_bins": 20, "hypervisor_desc_addr": 133446500352, "num_work_ids": 16, "work_item_id": -1, |